386 lines
14 KiB
C
386 lines
14 KiB
C
#include <stdint.h>
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typedef unsigned short API;
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typedef signed short API_SIGNED;
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#define FAR
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#define CHIPSET 12
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#define DSP 36
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#define ANLG_FAM 2 /* Iota */
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/* MFTAB */
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#define L1_MAX_FCT 5 /* Max number of fctions in a frame */
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#define MFTAB_SIZE 20
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#define NBMAX_CARRIER 174+374 /* Number of carriers (GSM-Ext + DCS */
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#define DPAGC_FIFO_LEN 4
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#define SIZE_HIST 10
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#if !L1_GPRS
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# define NBR_DL_L1S_TASKS 32
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#else
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# define NBR_DL_L1S_TASKS 45
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#endif
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#define NBR_L1A_PROCESSES 46
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#define W_A_DSP_IDLE3 1
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// Identifier for all DSP tasks.
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// ...RX & TX tasks identifiers.
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#define NO_DSP_TASK 0 // No task.
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#define NP_DSP_TASK 21 // Normal Paging reading task.
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#define EP_DSP_TASK 22 // Extended Paging reading task.
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#define NBS_DSP_TASK 19 // Normal BCCH serving reading task.
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#define EBS_DSP_TASK 20 // Extended BCCH serving reading task.
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#define NBN_DSP_TASK 17 // Normal BCCH neighbour reading task.
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#define EBN_DSP_TASK 18 // Extended BCCH neighbour reading task.
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#define ALLC_DSP_TASK 24 // CCCH reading task while performing FULL BCCH/CCCH reading task.
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#define CB_DSP_TASK 25 // CBCH reading task.
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#define DDL_DSP_TASK 26 // SDCCH/D (data) reading task.
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#define ADL_DSP_TASK 27 // SDCCH/A (SACCH) reading task.
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#define DUL_DSP_TASK 12 // SDCCH/D (data) transmit task.
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#define AUL_DSP_TASK 11 // SDCCH/A (SACCH) transmit task.
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#define RACH_DSP_TASK 10 // RACH transmit task.
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#define TCHT_DSP_TASK 13 // TCH Traffic data DSP task id (RX or TX)
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#define TCHA_DSP_TASK 14 // TCH SACCH data DSP task id (RX or TX)
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#define TCHD_DSP_TASK 28 // TCH Traffic data DSP task id (RX or TX)
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#define TCH_DTX_UL 15 // Replace UL task in DSP->MCU com. to say "burst not transmitted".
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#if (L1_GPRS)
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// Identifier for DSP tasks Packet dedicated.
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// ...RX & TX tasks identifiers.
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//------------------------------------------------------------------------
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// WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
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//------------------------------------------------------------------------
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#define PNP_DSP_TASK 30
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#define PEP_DSP_TASK 31
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#define PALLC_DSP_TASK 32
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#define PBS_DSP_TASK 33
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#define PTCCH_DSP_TASK 33
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#endif
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// Identifier for measurement, FB / SB search tasks.
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// Values 1,2,3 reserved for "number of measurements".
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#define FB_DSP_TASK 5 // Freq. Burst reading task in Idle mode.
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#define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode.
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#define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode.
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#define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode.
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#define IDLE1 1
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// Debug tasks
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#define CHECKSUM_DSP_TASK 33
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#define TST_NDB 35 // Checksum DSP->MCU
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#define TST_DB 36 // DB communication check
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#define INIT_VEGA 37
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#define DSP_LOOP_C 38
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// Identifier for measurement, FB / SB search tasks.
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// Values 1,2,3 reserved for "number of measurements".
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#define TCH_LOOP_A 31
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#define TCH_LOOP_B 32
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// bits in d_gsm_bgd_mgt - background task management
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#define B_DSPBGD_RECO 1 // start of reco in dsp background
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#define B_DSPBGD_UPD 2 // start of alignment update in dsp background
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#define B_DSPBGD_STOP_RECO 256 // stop of reco in dsp background
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#define B_DSPBGD_STOP_UPD 512 // stop of alignment update in dsp background
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// bit in d_pll_config
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#define B_32KHZ_CALIB (1 << 14) // force DSP in Idle1 during 32 khz calibration
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// ****************************************************************
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// NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
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// ****************************************************************
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// bits in d_tch_mode
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#define B_EOTD (1 << 0) // EOTD mode
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#define B_PLAY_UL (1 << 3) // Play UL
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#define B_DCO_ON (1 << 4) // DCO ON/OFF
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#define B_AUDIO_ASYNC (1 << 1) // WCP reserved
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// ****************************************************************
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// PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
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// ****************************************************************
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#define C_POND_RED 1L
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// below values are defined in the file l1_time.h
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//#define D_NSUBB_IDLE 296L
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//#define D_NSUBB_DEDIC 30L
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#define D_FB_THR_DET_IACQ 0x3333L
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#define D_FB_THR_DET_TRACK 0x28f6L
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#define D_DC_OFF_THRES 0x7fffL
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#define D_DUMMY_THRES 17408L
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#define D_DEM_POND_GEWL 26624L
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#define D_DEM_POND_RED 20152L
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#define D_HOLE 0L
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#define D_TRANSFER_RATE 0x6666L
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// Full Rate vocoder definitions.
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#define D_MACCTHRESH1 7872L
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#define D_MLDT -4L
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#define D_MACCTHRESH 7872L
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#define D_GU 5772L
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#define D_GO 7872L
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#define D_ATTMAX 53L
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#define D_SM -892L
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#define D_B 208L
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#define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
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#define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
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#define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
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#define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
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#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
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// Frequency burst definitions
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#define D_FB_MARGIN_BEG 24
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#define D_FB_MARGIN_END 22
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// V42bis definitions
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#define D_V42B_SWITCH_HYST 16L
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#define D_V42B_SWITCH_MIN 64L
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#define D_V42B_SWITCH_MAX 250L
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#define D_V42B_RESET_DELAY 10L
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// Latencies definitions
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#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
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// C.f. BUG1404
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#define D_LAT_MCU_BRIDGE 0x000FL
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#else
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#define D_LAT_MCU_BRIDGE 0x0009L
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#endif
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#define D_LAT_MCU_HOM2SAM 0x000CL
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#define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
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#define D_LAT_DSP_AFTER_SAM 0x0004L
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// Background Task in GSM mode: Initialization.
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#define D_GSM_BGD_MGT 0L
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#if (CHIPSET == 4)
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#define D_MISC_CONFIG 0L
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#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
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#define D_MISC_CONFIG 1L
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#else
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#define D_MISC_CONFIG 0L
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#endif
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#endif
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// Hall Rate vocoder and ched definitions.
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#define D_SD_MIN_THR_TCHHS 37L
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#define D_MA_MIN_THR_TCHHS 344L
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#define D_MD_MAX_THR_TCHHS 2175L
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#define D_MD1_MAX_THR_TCHHS 138L
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#define D_SD_AV_THR_TCHHS 1845L
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#define D_WED_FIL_TC 0x7c00L
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#define D_WED_FIL_INI 4650L
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#define D_X_MIN 15L
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#define D_X_MAX 23L
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#define D_Y_MIN 703L
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#define D_Y_MAX 2460L
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#define D_SLOPE 135L
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#define D_WED_DIFF_THRESHOLD 406L
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#define D_MABFI_MIN_THR_TCHHS 5320L
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#define D_LDT_HR -5
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#define D_MACCTRESH_HR 6500
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#define D_MACCTRESH1_HR 6500
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#define D_GU_HR 2620
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#define D_GO_HR 3700
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#define D_B_HR 182
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#define D_SM_HR -1608
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#define D_ATTMAX_HR 53
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// Enhanced Full Rate vocoder and ched definitions.
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#define C_MLDT_EFR -4
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#define C_MACCTHRESH_EFR 8000
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#define C_MACCTHRESH1_EFR 8000
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#define C_GU_EFR 4522
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#define C_GO_EFR 6500
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#define C_B_EFR 174
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#define C_SM_EFR -878
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#define C_ATTMAX_EFR 53
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#define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
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#define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
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#define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
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#define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
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// Integrated Data Services definitions.
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#define D_MAX_OVSPD_UL 8
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// Detect frames containing 90% of 1s as synchro frames
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#define D_SYNC_THRES 0x3f50
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// IDLE frames are only frames with 100 % of 1s
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#define D_IDLE_THRES 0x4000
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#define D_M1_THRES 5
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#define D_MAX_OVSP_DL 8
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// d_ra_act: bit field definition
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#define B_F48BLK 5
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// Mask for b_itc information (d_ra_conf)
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#define CE_MASK 0x04
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#define D_FACCH_THR 0
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#define D_DSP_TEST 0
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#define D_VERSION_NUMBER 0
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#define D_TI_VERSION 0
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/*------------------------------------------------------------------------------*/
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/* */
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/* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
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/* ++++++++++++++++++++++++++++++++++++++++++ */
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/* */
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/*------------------------------------------------------------------------------*/
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// COMMUNICATION Interrupt definition
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//------------------------------------
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#define ALL_16BIT 0xffffL
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#define B_GSM_PAGE (1 << 0)
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#define B_GSM_TASK (1 << 1)
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#define B_MISC_PAGE (1 << 2)
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#define B_MISC_TASK (1 << 3)
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#define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
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#define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
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#define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
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#define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
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// Common definition
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//----------------------------------
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// Index to *_DEMOD* arrays.
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#define D_TOA 0 // Time Of Arrival.
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#define D_PM 1 // Power Measurement.
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#define D_ANGLE 2 // Angle (AFC correction)
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#define D_SNR 3 // Signal / Noise Ratio.
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// Bit name/position definitions.
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#define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
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#define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
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#define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
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#define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
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#define B_AF 14 // Activity bit: 1 if data block is valid.
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#define B_BFI 2 // Bad Frame Indicator
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#define B_UFI 0 // UNRELIABLE FRAME Indicator
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#define B_ECRC 9 // Enhanced full rate CRC bit
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#define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
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#if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
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#define FACCH_GOOD 10
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#define FACCH_BAD 11
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#endif
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#if (AMR == 1)
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// Place of the RX type in the AMR block header
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#define RX_TYPE_SHIFT 3
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#define RX_TYPE_MASK 0x0038
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// Place of the vocoder type in the AMR block header
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#define VOCODER_TYPE_SHIFT 0
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#define VOCODER_TYPE_MASK 0x0007
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// List of the possible RX types in a_dd block
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#define SPEECH_GOOD 0
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#define SPEECH_DEGRADED 1
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#define ONSET 2
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#define SPEECH_BAD 3
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#define SID_FIRST 4
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#define SID_UPDATE 5
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#define SID_BAD 6
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#define AMR_NO_DATA 7
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#define AMR_INHIBIT 8
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// List of possible RX types in RATSCCH block
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#define C_RATSCCH_GOOD 5
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// List of the possible AMR channel rate
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#define AMR_CHANNEL_4_75 0
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#define AMR_CHANNEL_5_15 1
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#define AMR_CHANNEL_5_9 2
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#define AMR_CHANNEL_6_7 3
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#define AMR_CHANNEL_7_4 4
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#define AMR_CHANNEL_7_95 5
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#define AMR_CHANNEL_10_2 6
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#define AMR_CHANNEL_12_2 7
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// Types of RATSCCH blocks
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#define C_RATSCCH_UNKNOWN 0
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#define C_RATSCCH_CMI_PHASE_REQ 1
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#define C_RATSCCH_AMR_CONFIG_REQ_MAIN 2
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#define C_RATSCCH_AMR_CONFIG_REQ_ALT 3
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#define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4 // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
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#define C_RATSCCH_THRES_REQ 5
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// These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
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#define C_AMR_CHANGE_CMIP 0
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#define C_AMR_CHANGE_ACS 1
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#define C_AMR_CHANGE_ICM 2
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#define C_AMR_CHANGE_THR1 3
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#define C_AMR_CHANGE_THR2 4
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#define C_AMR_CHANGE_THR3 5
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#define C_AMR_CHANGE_HYST1 6
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#define C_AMR_CHANGE_HYST2 7
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#define C_AMR_CHANGE_HYST3 8
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// CMIP default value
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#define C_AMR_CMIP_DEFAULT 1 // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
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#endif
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// "d_ctrl_tch" bits positions for TCH configuration.
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#define B_CHAN_MODE 0
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#define B_CHAN_TYPE 4
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#define B_RESET_SACCH 6
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#define B_VOCODER_ON 7
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#define B_SYNC_TCH_UL 8
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#if (AMR == 1)
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#define B_SYNC_AMR 9
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#else
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#define B_SYNC_TCH_DL 9
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#endif
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#define B_STOP_TCH_UL 10
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#define B_STOP_TCH_DL 11
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#define B_TCH_LOOP 12
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#define B_SUBCHANNEL 15
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// "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
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#define B_RAMP 0
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#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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#define B_BULRAMPDEL 3 // Note: this name is changed
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#define B_BULRAMPDEL2 2 // Note: this name is changed
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#define B_BULRAMPDEL_BIS 9
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#define B_BULRAMPDEL2_BIS 10
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#endif
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#define B_AFC 4
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// "d_ctrl_system" bits positions.
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#define B_TSQ 0
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#define B_BCCH_FREQ_IND 3
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#define B_TASK_ABORT 15 // Abort RF tasks for DSP.
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/* Channel type definitions for DEDICATED mode */
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#define INVALID_CHANNEL 0
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#define TCH_F 1
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#define TCH_H 2
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#define SDCCH_4 3
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#define SDCCH_8 4
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/* Channel mode definitions for DEDICATED mode */
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#define SIG_ONLY_MODE 0 // signalling only
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#define TCH_FS_MODE 1 // speech full rate
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#define TCH_HS_MODE 2 // speech half rate
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#define TCH_96_MODE 3 // data 9,6 kb/s
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#define TCH_48F_MODE 4 // data 4,8 kb/s full rate
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#define TCH_48H_MODE 5 // data 4,8 kb/s half rate
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#define TCH_24F_MODE 6 // data 2,4 kb/s full rate
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#define TCH_24H_MODE 7 // data 2,4 kb/s half rate
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#define TCH_EFR_MODE 8 // enhanced full rate
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#define TCH_144_MODE 9 // data 14,4 kb/s half rate
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