439 lines
9.7 KiB
C
439 lines
9.7 KiB
C
/* Calypso DBB internal UART Driver */
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/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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* (C) 2010 by Ingo Albrecht <prom@berlin.ccc.de>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <debug.h>
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#include <memory.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdio.h>
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#include <defines.h>
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#include <console.h>
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#include <comm/sercomm.h>
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#include <calypso/irq.h>
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#include <uart.h>
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#define BASE_ADDR_UART_MODEM 0xffff5000
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#define OFFSET_IRDA 0x800
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#define UART_REG(n,m) (BASE_ADDR_UART_MODEM + ((n)*OFFSET_IRDA)+(m))
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#define LCR7BIT 0x80
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#define LCRBFBIT 0x40
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#define MCR6BIT 0x20
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#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT))
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/* read access LCR[7] = 0 */
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enum uart_reg {
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RHR = 0,
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IER = 1,
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IIR = 2,
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LCR = 3,
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MCR = 4,
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LSR = 5,
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MSR = 6,
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SPR = 7,
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MDR1 = 8,
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DMR2 = 9,
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SFLSR = 0x0a,
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RESUME = 0x0b,
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SFREGL = 0x0c,
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SFREGH = 0x0d,
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BLR = 0x0e,
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ACREG = 0x0f,
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SCR = 0x10,
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SSR = 0x11,
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EBLR = 0x12,
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/* read access LCR[7] = 1 */
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DLL = RHR | LCR7BIT,
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DLH = IER | LCR7BIT,
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DIV1_6 = ACREG | LCR7BIT,
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/* read/write access LCR[7:0] = 0xbf */
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EFR = IIR | LCRBFBIT,
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XON1 = MCR | LCRBFBIT,
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XON2 = LSR | LCRBFBIT,
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XOFF1 = MSR | LCRBFBIT,
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XOFF2 = SPR | LCRBFBIT,
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/* read/write access if EFR[4] = 1 and MCR[6] = 1 */
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TCR = MSR | MCR6BIT,
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TLR = SPR | MCR6BIT,
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};
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/* write access LCR[7] = 0 */
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#define THR RHR
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#define FCR IIR /* only if EFR[4] = 1 */
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#define TXFLL SFLSR
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#define TXFLH RESUME
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#define RXFLL SFREGL
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#define RXFLH SFREGH
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enum fcr_bits {
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FIFO_EN = (1 << 0),
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RX_FIFO_CLEAR = (1 << 1),
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TX_FIFO_CLEAR = (1 << 2),
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DMA_MODE = (1 << 3),
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};
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#define TX_FIFO_TRIG_SHIFT 4
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#define RX_FIFO_TRIG_SHIFT 6
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enum iir_bits {
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IIR_INT_PENDING = 0x01,
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IIR_INT_TYPE = 0x3E,
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IIR_INT_TYPE_RX_STATUS_ERROR = 0x06,
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IIR_INT_TYPE_RX_TIMEOUT = 0x0C,
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IIR_INT_TYPE_RHR = 0x04,
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IIR_INT_TYPE_THR = 0x02,
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IIR_INT_TYPE_MSR = 0x00,
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IIR_INT_TYPE_XOFF = 0x10,
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IIR_INT_TYPE_FLOW = 0x20,
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IIR_FCR0_MIRROR = 0xC0,
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};
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#define UART_REG_UIR 0xffff6000
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/* enable or disable the divisor latch for access to DLL, DLH */
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static void uart_set_lcr7bit(int uart, int on)
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{
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uint8_t reg;
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reg = readb(UART_REG(uart, LCR));
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if (on)
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reg |= (1 << 7);
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else
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reg &= ~(1 << 7);
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writeb(reg, UART_REG(uart, LCR));
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}
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static uint8_t old_lcr;
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static void uart_set_lcr_bf(int uart, int on)
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{
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if (on) {
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old_lcr = readb(UART_REG(uart, LCR));
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writeb(0xBF, UART_REG(uart, LCR));
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} else {
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writeb(old_lcr, UART_REG(uart, LCR));
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}
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}
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/* Enable or disable the TCR_TLR latch bit in MCR[6] */
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static void uart_set_mcr6bit(int uart, int on)
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{
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uint8_t mcr;
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/* we assume EFR[4] is always set to 1 */
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mcr = readb(UART_REG(uart, MCR));
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if (on)
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mcr |= (1 << 6);
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else
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mcr &= ~(1 << 6);
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writeb(mcr, UART_REG(uart, MCR));
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}
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static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val)
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{
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if (reg & LCRBFBIT)
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uart_set_lcr_bf(uart, 1);
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else if (reg & LCR7BIT)
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uart_set_lcr7bit(uart, 1);
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else if (reg & MCR6BIT)
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uart_set_mcr6bit(uart, 1);
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writeb(val, UART_REG(uart, REG_OFFS(reg)));
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if (reg & LCRBFBIT)
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uart_set_lcr_bf(uart, 0);
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else if (reg & LCR7BIT)
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uart_set_lcr7bit(uart, 0);
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else if (reg & MCR6BIT)
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uart_set_mcr6bit(uart, 0);
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}
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/* read from a UART register, applying any required latch bits */
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static uint8_t uart_reg_read(int uart, enum uart_reg reg)
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{
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uint8_t ret;
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if (reg & LCRBFBIT)
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uart_set_lcr_bf(uart, 1);
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else if (reg & LCR7BIT)
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uart_set_lcr7bit(uart, 1);
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else if (reg & MCR6BIT)
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uart_set_mcr6bit(uart, 1);
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ret = readb(UART_REG(uart, REG_OFFS(reg)));
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if (reg & LCRBFBIT)
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uart_set_lcr_bf(uart, 0);
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else if (reg & LCR7BIT)
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uart_set_lcr7bit(uart, 0);
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else if (reg & MCR6BIT)
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uart_set_mcr6bit(uart, 0);
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return ret;
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}
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static void uart_irq_handler_cons(__unused enum irq_nr irqnr)
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{
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const uint8_t uart = cons_get_uart();
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uint8_t iir;
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//uart_putchar_nb(uart, 'U');
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iir = uart_reg_read(uart, IIR);
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if (iir & IIR_INT_PENDING)
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return;
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switch (iir & IIR_INT_TYPE) {
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case IIR_INT_TYPE_RHR:
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break;
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case IIR_INT_TYPE_THR:
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if (cons_rb_flush() == 1) {
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/* everything was flushed, disable THR IRQ */
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uint8_t ier = uart_reg_read(uart, IER);
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ier &= ~(1 << 1);
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uart_reg_write(uart, IER, ier);
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}
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break;
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case IIR_INT_TYPE_MSR:
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break;
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case IIR_INT_TYPE_RX_STATUS_ERROR:
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break;
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case IIR_INT_TYPE_RX_TIMEOUT:
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break;
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case IIR_INT_TYPE_XOFF:
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break;
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}
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}
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static void uart_irq_handler_sercomm(__unused enum irq_nr irqnr)
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{
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const uint8_t uart = sercomm_get_uart();
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uint8_t iir, ch;
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//uart_putchar_nb(uart, 'U');
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iir = uart_reg_read(uart, IIR);
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if (iir & IIR_INT_PENDING)
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return;
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switch (iir & IIR_INT_TYPE) {
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case IIR_INT_TYPE_RX_TIMEOUT:
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case IIR_INT_TYPE_RHR:
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/* as long as we have rx data available */
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while (uart_getchar_nb(uart, &ch)) {
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if (sercomm_drv_rx_char(ch) < 0) {
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/* sercomm cannot receive more data right now */
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uart_irq_enable(uart, UART_IRQ_RX_CHAR, 0);
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}
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}
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break;
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case IIR_INT_TYPE_THR:
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/* as long as we have space in the FIFO */
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while (!uart_tx_busy(uart)) {
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/* get a byte from sercomm */
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if (!sercomm_drv_pull(&ch)) {
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/* no more bytes in sercomm, stop TX interrupts */
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uart_irq_enable(uart, UART_IRQ_TX_EMPTY, 0);
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break;
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}
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/* write the byte into the TX FIFO */
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uart_putchar_nb(uart, ch);
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}
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break;
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case IIR_INT_TYPE_MSR:
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printf("UART IRQ MSR\n");
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break;
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case IIR_INT_TYPE_RX_STATUS_ERROR:
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printf("UART IRQ RX_SE\n");
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break;
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case IIR_INT_TYPE_XOFF:
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printf("UART IRQXOFF\n");
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break;
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}
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}
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static const uint8_t uart2irq[] = {
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[0] = IRQ_UART_IRDA,
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[1] = IRQ_UART_MODEM,
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};
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void uart_init(uint8_t uart, uint8_t interrupts)
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{
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uint8_t irq = uart2irq[uart];
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uart_reg_write(uart, IER, 0x00);
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if (uart == cons_get_uart()) {
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cons_init();
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if(interrupts) {
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irq_register_handler(irq, &uart_irq_handler_cons);
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irq_config(irq, 0, 0, 0xff);
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irq_enable(irq);
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}
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} else if (uart == sercomm_get_uart()) {
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sercomm_init();
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if(interrupts) {
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irq_register_handler(irq, &uart_irq_handler_sercomm);
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irq_config(irq, 0, 0, 0xff);
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irq_enable(irq);
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}
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uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
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} else {
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return;
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}
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#if 0
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if (uart == 1) {
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/* assign UART to MCU and unmask interrupts*/
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writeb(UART_REG_UIR, 0x00);
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}
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#endif
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/* if we don't initialize these, we get strange corruptions in the
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received data... :-( */
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uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
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uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
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uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
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uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
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uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
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uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
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/* select UART mode */
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uart_reg_write(uart, MDR1, 0);
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/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
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uart_reg_write(uart, EFR, (1 << 4));
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/* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */
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uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
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(3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT));
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/* THR interrupt only when TX FIFO and TX shift register are empty */
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uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));
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/* 8 bit, 1 stop bit, no parity, no break */
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uart_reg_write(uart, LCR, 0x03);
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uart_set_lcr7bit(uart, 0);
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}
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void uart_poll(uint8_t uart) {
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if(uart == cons_get_uart()) {
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uart_irq_handler_cons(0);
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} else {
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uart_irq_handler_sercomm(0);
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}
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}
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void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on)
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{
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uint8_t ier = uart_reg_read(uart, IER);
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uint8_t mask = 0;
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switch (irq) {
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case UART_IRQ_TX_EMPTY:
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mask = (1 << 1);
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break;
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case UART_IRQ_RX_CHAR:
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mask = (1 << 0);
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break;
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}
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if (on)
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ier |= mask;
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else
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ier &= ~mask;
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uart_reg_write(uart, IER, ier);
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}
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void uart_putchar_wait(uint8_t uart, int c)
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{
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/* wait while TX FIFO indicates full */
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while (readb(UART_REG(uart, SSR)) & 0x01) { }
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/* put character in TX FIFO */
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writeb(c, UART_REG(uart, THR));
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}
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int uart_putchar_nb(uint8_t uart, int c)
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{
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/* if TX FIFO indicates full, abort */
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if (readb(UART_REG(uart, SSR)) & 0x01)
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return 0;
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writeb(c, UART_REG(uart, THR));
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return 1;
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}
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int uart_getchar_nb(uint8_t uart, uint8_t *ch)
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{
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uint8_t lsr;
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lsr = readb(UART_REG(uart, LSR));
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/* something strange happened */
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if (lsr & 0x02)
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printf("LSR RX_OE\n");
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if (lsr & 0x04)
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printf("LSR RX_PE\n");
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if (lsr & 0x08)
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printf("LSR RX_FE\n");
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if (lsr & 0x10)
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printf("LSR RX_BI\n");
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if (lsr & 0x80)
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printf("LSR RX_FIFO_STS\n");
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/* is the Rx FIFO empty? */
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if (!(lsr & 0x01))
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return 0;
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*ch = readb(UART_REG(uart, RHR));
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//printf("getchar_nb(%u) = %02x\n", uart, *ch);
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return 1;
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}
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int uart_tx_busy(uint8_t uart)
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{
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if (readb(UART_REG(uart, SSR)) & 0x01)
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return 1;
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return 0;
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}
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static const uint16_t divider[] = {
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[UART_38400] = 21, /* 38,690 */
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[UART_57600] = 14, /* 58,035 */
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[UART_115200] = 7, /* 116,071 */
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[UART_230400] = 4, /* 203,125! (-3% would be 223,488) */
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[UART_460800] = 2, /* 406,250! (-3% would be 446,976) */
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[UART_921600] = 1, /* 812,500! (-3% would be 893,952) */
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};
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int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt)
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{
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uint16_t div;
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if (bdrt >= ARRAY_SIZE(divider))
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return -1;
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div = divider[bdrt];
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uart_set_lcr7bit(uart, 1);
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writeb(div & 0xff, UART_REG(uart, DLL));
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writeb(div >> 8, UART_REG(uart, DLH));
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uart_set_lcr7bit(uart, 0);
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return 0;
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}
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