95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/* Values from an actual phone firmware that uses the 3306 DSP ROM code version */
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static T_PARAM_MCU_DSP dsp_params = {
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.d_transfer_rate = 0x6666,
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/* Latencies */
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.d_lat_mcu_bridge = 15,
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.d_lat_mcu_hom2sam = 12,
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.d_lat_mcu_bef_fast_access = 5,
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.d_lat_dsp_after_sam = 4,
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/* DSP Start Address */
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.d_gprs_install_address = 0x7002, /* needs to be set by patch or manually */
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.d_misc_config = 1,
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.d_cn_sw_workaround = 0xE,
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.d_hole2_param = { 0, 0, 0, 0 },
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/* Frequency Burst */
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.d_fb_margin_beg = 24,
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.d_fb_margin_end = 22,
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.d_nsubb_idle = 296,
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.d_nsubb_dedic = 30,
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.d_fb_thr_det_iacq = 0x3333,
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.d_fb_thr_det_track = 0x28f6,
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/* Demodulation */
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.d_dc_off_thres = 0x7fff,
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.d_dummy_thres = 17408,
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.d_dem_pond_gewl = 26624,
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.d_dem_pond_red = 20152,
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/* TCH Full Speech */
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.d_maccthresh1 = 7872,
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.d_mldt = -4,
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.d_maccthresh = 7872,
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.d_gu = 5772,
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.d_go = 7872,
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.d_attmax = 53,
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.d_sm = -892,
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.d_b = 208,
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/* V.42 bis */
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.d_v42b_switch_hyst = 16,
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.d_v42b_switch_min = 64,
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.d_v42b_switch_max = 250,
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.d_v42b_reset_delay = 10,
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/* TCH Half Speech */
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.d_ldT_hr = -5,
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.d_maccthresh_hr = 6500,
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.d_maccthresh1_hr = 6500,
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.d_gu_hr = 2620,
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.d_go_hr = 3700,
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.d_b_hr = 182,
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.d_sm_hr = -1608,
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.d_attmax_hr = 53,
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/* TCH Enhanced FR Speech */
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.c_mldt_efr = -4,
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.c_maccthresh_efr = 8000,
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.c_maccthresh1_efr = 8000,
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.c_gu_efr = 4522,
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.c_go_efr = 6500,
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.c_b_efr = 174,
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.c_sm_efr = -878,
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.c_attmax_efr = 53,
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/* CHED TCH Full Speech */
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.d_sd_min_thr_tchfs = 15,
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.d_ma_min_thr_tchfs = 738,
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.d_md_max_thr_tchfs = 1700,
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.d_md1_max_thr_tchfs = 99,
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/* CHED TCH Half Speech */
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.d_sd_min_thr_tchhs = 37,
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.d_ma_min_thr_tchhs = 344,
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.d_sd_av_thr_tchhs = 1845,
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.d_md_max_thr_tchhs = 2175,
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.d_md1_max_thr_tchhs = 138,
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/* CHED TCH/F EFR Speech */
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.d_sd_min_thr_tchefs = 15,
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.d_ma_min_thr_tchefs = 738,
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.d_md_max_thr_tchefs = 0x4ce,
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.d_md1_max_thr_tchefs = 0x63,
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/* */
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.d_wed_fil_ini = 0x122a,
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.d_wed_fil_tc = 0x7c00,
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.d_x_min = 0xf,
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.d_x_max = 0x17,
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.d_slope = 0x87,
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.d_y_min = 0x2bf,
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.d_y_max = 0x99c,
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.d_wed_diff_threshold = 0x196,
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.d_mabfi_min_thr_tchhs = 0x14c8,
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/* FACCH module */
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.d_facch_thr = 0,
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/* IDS module */
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.d_max_ovsp_ul = 8,
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.d_sync_thres = 0x3f50,
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.d_idle_thres = 0x4000,
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.d_m1_thres = 5,
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.d_max_ovsp_dl = 8,
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.d_gsm_bgd_mgt = 0,
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/* we don't set the FIR coefficients !?! */
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};
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