add some header files about MTK GSM related peripherals
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#ifndef _MTK_BFE_H
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#define _MTK_BFE_H
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/* MTK Baseband Frontend */
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/* MT6235 Chapter 10 */
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enum mtk_bfe_reg {
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BFE_CON = 0x0000,
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BFE_STA = 0x0004,
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/* Rx Configuration Register */
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RX_CFG = 0x0010,
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/* Rx Control Register */
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RX_CON = 0x0014,
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/* RX Interference Detection Power Measurement Control Register */
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RX_PM_CON = 0x0018,
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/* RX FIR Coefficient Set ID Control Register */
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RX_FIR_CSID_CON = 0x001c,
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/* RX Ram0 Coefficient Set 0 Register */
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RX_RAM0_CS0 = 0x0070,
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/* RX Ram1 Coefficient Set 0 Register */
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RX_RAM1_CS0 = 0x0020,
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/* Rx Interference Detection HPF Power Register */
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RX_HPWR_STS = 0x00b0,
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/* Rx Interference Detection BPF Power Register */
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RX_BPWR_STS = 0x00b4,
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TX_CFG = 0x0060,
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TX_CON = 0x0064,
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TX_OFF = 0x0068,
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};
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#define RX_RAM0_CS(n) (RX_RAM0_CS0 + (n)*4)
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#define RX_RAM1_CS(n) (RX_RAM0_CS1 + (n)*4)
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/* SWAP I/Q before input to baesband frontend */
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#define RX_CFG_SWAP_IQ 0x0001
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/* Bypass RX FIR filter control */
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#define RX_CFG_BYPFLTR 0x0002
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/* Number of RX FIR filter taps */
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#define RX_CFG_FIRTPNO(n) (((n) & 0x3f) << 4)
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#define RX_CON_BLPEN_NORMAL (0 << 0)
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#define RX_CON_BLPEN_LOOPB (1 << 0)
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#define RX_CON_BLPEN_LOOPB_FILT (2 << 0)
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/* Phase de-rotation in wide FIR data path */
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#define RX_CON_PH_ROEN_W (1 << 2)
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/* Phase de-rotation in narrow FIR data path */
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#define RX_CON_PH_ROEN_N (1 << 3)
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/* RX I-data gain compenstation select (+/- 1.5dB */
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#define RX_CON_IGAINSEL_00dB (0 << 4)
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#define RX_CON_IGAINSEL_03dB (1 << 4)
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#define RX_CON_IGAINSEL_06dB (2 << 4)
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#define RX_CON_IGAINSEL_09dB (3 << 4)
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#define RX_CON_IGAINSEL_12dB (4 << 4)
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#define RX_CON_IGAINSEL_15dB (5 << 4)
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#define RX_CON_IGAINSEL_n03dB (9 << 4)
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#define RX_CON_IGAINSEL_n06dB (10 << 4)
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#define RX_CON_IGAINSEL_n09dB (11 << 4)
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#define RX_CON_IGAINSEL_n12dB (12 << 4)
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#define RX_CON_IGAINSEL_n15dB (13 << 4)
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/* TX_CFG */
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/* Appending Bits enable */
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#define TX_CFG_APNDEN (1 << 0)
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/* Ramp Profile Select for 8PSK */
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#define TX_CFG_RPSEL_I (0 << 1) /* 50 kHz sine tone */
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#define TX_CFG_RPSEL_II (1 << 1) /* null DC I/Q */
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#define TX_CFG_RPSEL_III (3 << 1)
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#define TX_CFG_INTEN (1 << 3) /* Interpolate between bursts */
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#define TX_CFG_MDBYP (1 << 4) /* Modulator Bypass */
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#define TX_CFG_SGEN (1 << 5) /* 540 kHz sine tone */
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#define TX_CFG_ALL_10GEN_ZERO (1 << 6)
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#define TX_CFG_ALL_10GEN_ONE (2 << 6)
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#define TX_CFG_SW_QBCNT(n) (((n) & 0x1f) << 8)
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#define TX_CFG_GMSK_DTAP_SYM_1 (0 << 13)
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#define TX_CFG_GMSK_DTAP_SYM_0 (1 << 13)
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#define TX_CFG_GMSK_DTAP_SYM_2 (2 << 13)
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#define TX_CON_IQSWP (1 << 0) /* Swap I/Q */
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/* GMSK or 8PSK modulation for 1st through 4th burst */
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#define TX_CON_MDSEL1_8PSK (1 << 2)
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#define TX_CON_MDSEL2_8PSK (1 << 3)
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#define TX_CON_MDSEL3_8PSK (1 << 4)
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#define TX_CON_MDSEL4_8PSK (1 << 5)
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/* Quadratur phase compensation select */
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#define TX_CON_PHSEL_0deg (0 << 8)
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#define TX_CON_PHSEL_1deg (1 << 8)
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#define TX_CON_PHSEL_2deg (2 << 8)
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#define TX_CON_PHSEL_3deg (3 << 8)
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#define TX_CON_PHSEL_4deg (4 << 8)
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#define TX_CON_PHSEL_5deg (5 << 8)
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#define TX_CON_PHSEL_n5deg (10 << 8)
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#define TX_CON_PHSEL_n4deg (11 << 8)
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#define TX_CON_PHSEL_n3deg (12 << 8)
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#define TX_CON_PHSEL_n2deg (13 << 8)
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#define TX_CON_PHSEL_n1deg (14 << 8)
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/* GMSK modulator output latenct */
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#define TX_CON_GMSK_DTAP_QB(n) (((n) & 3) << 12)
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#define TX_OFF_I(n) (((n) & 0x3f) << 0)
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#define TX_OFF_Q(n) (((n) & 0x3f) << 8)
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/* Double Buffering */
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#define TX_OFF_TYP_DB 0x8000
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#endif /* _MTK_BFE_H */
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#ifndef _MTK_BPI_H
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#define _MTK_BPI_H
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/* MTK Baseband Parallel Interface */
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/* Chapter 9.2 of MT6235 Data Sheet */
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#define BPI_BUF(n) (BPI_BUF0 + ((n) * 4))
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enum mtk_bpi_reg {
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BPI_CON = 0x0000,
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BPI_BUF0 = 0x0004,
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BPI_ENA0 = 0x00b0,
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BPI_ENA1 = 0x00b4,
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BPI_ENA2 = 0x00b8,
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};
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#endif /* _MTK_BPI_H */
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#ifndef _MTK_BSI_H
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#define _MTK_BSI_H
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/* MTK Baseband Serial Interface */
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enum bsi_reg {
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BSI_CON = 0x0000,
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BSI_D0_CON = 0x0004,
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BSI_D0_DAT = 0x0008,
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BSI_ENA_0 = 0x0190,
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BSI_ENA_1 = 0x0194,
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BSI_IO_CON = 0x0198,
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BSI_DOUT = 0x019c,
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BSI_DIN = 0x01a0,
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BSI_PAIR_NUM = 0x01a4,
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};
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/* Compute offset of BSI_D0_CON / BSI_D0_DAT registers */
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#define BSI_Dn_CON(x) (BSI_D0_CON + (x * 8))
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#define BSI_Dn_CON(x) (BSI_D0_DAT + (x * 8))
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/* MT6235 Section 9.1.1 */
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#define BSI_CON_CLK_POL_INV (1 << 0)
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#define BSI_CON_CLK_SPD_52_2 (0 << 1) /* 26 MHz */
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#define BSI_CON_CLK_SPD_52_4 (1 << 1) /* 13 MHz */
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#define BSI_CON_CLK_SPD_52_6 (2 << 1) /* 8.67 MHz */
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#define BSI_CON_CLK_SPD_52_8 (3 << 1) /* 6.50 MHz */
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#define BSI_CON_IMOD (1 << 3)
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#define BSI_CON_EN0_LEN_SHORT (1 << 4)
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#define BSI_CON_EN0_POL_INV (1 << 5)
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#define BSI_CON_EN0_LEN_SHORT (1 << 6)
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#define BSI_CON_EN0_POL_INV (1 << 7)
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#define BSI_CON_SETENV (1 << 8)
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/* how the length is encoded in BSI_Dx_CON */
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#define BSI_Dx_LEN(n) ((n & 0x7f) << 8)
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#define BSI_Dx_ISB 0x8000 /* select device 1 */
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#endif /* _MTK_BSI_H */
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#ifndef _MTK_TDMA_H
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#define _MTK_TDMA_H
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/* MTK TDMA Timer */
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/* MT6235 Section 11 */
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enum mtk_tdma_reg {
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/* Read current quarter bit count */
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TDMA_TQCNT = 0x0000,
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/* Latched Qbit counter reset position */
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TDMA_WRAP = 0x0004,
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/* Direct Qbit counter reset position */
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TDMA_WRAPIMD = 0x0008,
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/* Event latch position */
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TDMA_EVTVAL = 0x000c,
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/* DSP software control */
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TDMA_DTIRQ = 0x0010,
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/* MCU software control */
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TDMA_CTIRQ1 = 0x0014,
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TDMA_CTIRQ2 = 0x0018,
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/* AFC control */
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TDMA_AFC0 = 0x0020,
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TDMA_AFC1 = 0x0024,
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TDMA_AFC2 = 0x0028,
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TDMA_AFC3 = 0x002c,
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/* BSI event */
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TDMA_BSI0 = 0x00b0,
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/* BPI event */
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TDMA_BPI0 = 0x0100,
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/* Auxiliary ADC event */
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TDMA_AUXEV0 = 0x0400,
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TDMA_AUXEV1 = 0x0404,
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/* Event Control */
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TDMA_EVTENA0 = 0x0150,
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TDMA_EVTENA1 = 0x0154,
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TDMA_EVTENA2 = 0x0158,
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TDMA_EVTENA3 = 0x015c,
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TDMA_EVTENA4 = 0x0160,
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TDMA_EVTENA5 = 0x0164,
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TDMA_EVTENA6 = 0x0168,
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TDMA_EVTENA6 = 0x016c,
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TDMA_WRAPOFS = 0x0170,
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TDMA_REGBIAS = 0x0174,
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TDMA_DTXCON = 0x0180,
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TDMA_RXCON = 0x0184,
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TDMA_BDLCON = 0x0188,
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TDMA_BULCON1 = 0x018c,
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TDMA_BULCON2 = 0x0190,
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TDMA_FB_FLAG = 0x0194,
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TDMA_FB_CLRI = 0x0198,
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};
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#define TDMA_BSI(n) (TDMA_BSI0 + (n)*4)
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#define TDMA_BPI(n) (TDMA_BPI0 + (n)*4)
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#endif /* _MTK_TDMA_H */
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