diff --git a/src/host/trxcon/include/osmocom/bb/trxcon/sched_trx.h b/src/host/trxcon/include/osmocom/bb/trxcon/sched_trx.h
index ad860e9e9..9a14844df 100644
--- a/src/host/trxcon/include/osmocom/bb/trxcon/sched_trx.h
+++ b/src/host/trxcon/include/osmocom/bb/trxcon/sched_trx.h
@@ -53,48 +53,48 @@ enum trx_burst_type {
  * These types define the different channels on a multiframe.
  * Each channel has queues and can be activated individually.
  */
-enum trx_lchan_type {
-	TRXC_IDLE = 0,
-	TRXC_FCCH,
-	TRXC_SCH,
-	TRXC_BCCH,
-	TRXC_RACH,
-	TRXC_CCCH,
-	TRXC_TCHF,
-	TRXC_TCHH_0,
-	TRXC_TCHH_1,
-	TRXC_SDCCH4_0,
-	TRXC_SDCCH4_1,
-	TRXC_SDCCH4_2,
-	TRXC_SDCCH4_3,
-	TRXC_SDCCH8_0,
-	TRXC_SDCCH8_1,
-	TRXC_SDCCH8_2,
-	TRXC_SDCCH8_3,
-	TRXC_SDCCH8_4,
-	TRXC_SDCCH8_5,
-	TRXC_SDCCH8_6,
-	TRXC_SDCCH8_7,
-	TRXC_SACCHTF,
-	TRXC_SACCHTH_0,
-	TRXC_SACCHTH_1,
-	TRXC_SACCH4_0,
-	TRXC_SACCH4_1,
-	TRXC_SACCH4_2,
-	TRXC_SACCH4_3,
-	TRXC_SACCH8_0,
-	TRXC_SACCH8_1,
-	TRXC_SACCH8_2,
-	TRXC_SACCH8_3,
-	TRXC_SACCH8_4,
-	TRXC_SACCH8_5,
-	TRXC_SACCH8_6,
-	TRXC_SACCH8_7,
-	TRXC_PDTCH,
-	TRXC_PTCCH,
-	TRXC_SDCCH4_CBCH,
-	TRXC_SDCCH8_CBCH,
-	_TRX_CHAN_MAX
+enum l1sched_lchan_type {
+	L1SCHED_IDLE = 0,
+	L1SCHED_FCCH,
+	L1SCHED_SCH,
+	L1SCHED_BCCH,
+	L1SCHED_RACH,
+	L1SCHED_CCCH,
+	L1SCHED_TCHF,
+	L1SCHED_TCHH_0,
+	L1SCHED_TCHH_1,
+	L1SCHED_SDCCH4_0,
+	L1SCHED_SDCCH4_1,
+	L1SCHED_SDCCH4_2,
+	L1SCHED_SDCCH4_3,
+	L1SCHED_SDCCH8_0,
+	L1SCHED_SDCCH8_1,
+	L1SCHED_SDCCH8_2,
+	L1SCHED_SDCCH8_3,
+	L1SCHED_SDCCH8_4,
+	L1SCHED_SDCCH8_5,
+	L1SCHED_SDCCH8_6,
+	L1SCHED_SDCCH8_7,
+	L1SCHED_SACCHTF,
+	L1SCHED_SACCHTH_0,
+	L1SCHED_SACCHTH_1,
+	L1SCHED_SACCH4_0,
+	L1SCHED_SACCH4_1,
+	L1SCHED_SACCH4_2,
+	L1SCHED_SACCH4_3,
+	L1SCHED_SACCH8_0,
+	L1SCHED_SACCH8_1,
+	L1SCHED_SACCH8_2,
+	L1SCHED_SACCH8_3,
+	L1SCHED_SACCH8_4,
+	L1SCHED_SACCH8_5,
+	L1SCHED_SACCH8_6,
+	L1SCHED_SACCH8_7,
+	L1SCHED_PDTCH,
+	L1SCHED_PTCCH,
+	L1SCHED_SDCCH4_CBCH,
+	L1SCHED_SDCCH8_CBCH,
+	_L1SCHED_CHAN_MAX
 };
 
 /* Represents a burst to be transmitted */
@@ -146,12 +146,12 @@ struct trx_lchan_desc {
 };
 
 struct trx_frame {
-	/*! Downlink TRX channel type */
-	enum trx_lchan_type dl_chan;
+	/*! Downlink channel (slot) type */
+	enum l1sched_lchan_type dl_chan;
 	/*! Downlink block ID */
 	uint8_t dl_bid;
-	/*! Uplink TRX channel type */
-	enum trx_lchan_type ul_chan;
+	/*! Uplink channel (slot) type */
+	enum l1sched_lchan_type ul_chan;
 	/*! Uplink block ID */
 	uint8_t ul_bid;
 };
@@ -189,7 +189,7 @@ struct trx_lchan_meas_hist {
 /* States each channel on a multiframe */
 struct trx_lchan_state {
 	/*! Channel type */
-	enum trx_lchan_type type;
+	enum l1sched_lchan_type type;
 	/*! Channel status */
 	uint8_t active;
 	/*! Link to a list of channels */
@@ -294,14 +294,14 @@ struct trx_ts_prim {
 	/*! Link to queue of TS */
 	struct llist_head list;
 	/*! Logical channel type */
-	enum trx_lchan_type chan;
+	enum l1sched_lchan_type chan;
 	/*! Payload length */
 	size_t payload_len;
 	/*! Payload */
 	uint8_t payload[0];
 };
 
-extern const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX];
+extern const struct trx_lchan_desc trx_lchan_desc[_L1SCHED_CHAN_MAX];
 const struct trx_multiframe *sched_mframe_layout(
 	enum gsm_phys_chan_config config, int tn);
 
@@ -321,15 +321,15 @@ int sched_trx_start_ciphering(struct trx_ts *ts, uint8_t algo,
 
 /* Logical channel management functions */
 enum gsm_phys_chan_config sched_trx_chan_nr2pchan_config(uint8_t chan_nr);
-enum trx_lchan_type sched_trx_chan_nr2lchan_type(uint8_t chan_nr,
+enum l1sched_lchan_type sched_trx_chan_nr2lchan_type(uint8_t chan_nr,
 	uint8_t link_id);
 
 void sched_trx_deactivate_all_lchans(struct trx_ts *ts);
 int sched_trx_set_lchans(struct trx_ts *ts, uint8_t chan_nr, int active, uint8_t tch_mode);
-int sched_trx_activate_lchan(struct trx_ts *ts, enum trx_lchan_type chan);
-int sched_trx_deactivate_lchan(struct trx_ts *ts, enum trx_lchan_type chan);
+int sched_trx_activate_lchan(struct trx_ts *ts, enum l1sched_lchan_type chan);
+int sched_trx_deactivate_lchan(struct trx_ts *ts, enum l1sched_lchan_type chan);
 struct trx_lchan_state *sched_trx_find_lchan(struct trx_ts *ts,
-	enum trx_lchan_type chan);
+	enum l1sched_lchan_type chan);
 
 /* Primitive management functions */
 int sched_prim_init(void *ctx, struct trx_ts_prim **prim,
@@ -349,7 +349,7 @@ int sched_prim_push(struct trx_instance *trx,
 	|| mode == GSM48_CMODE_DATA_3k6)
 
 #define CHAN_IS_TCH(chan) \
-	(chan == TRXC_TCHF || chan == TRXC_TCHH_0 || chan == TRXC_TCHH_1)
+	(chan == L1SCHED_TCHF || chan == L1SCHED_TCHH_0 || chan == L1SCHED_TCHH_1)
 
 #define CHAN_IS_SACCH(chan) \
 	(trx_lchan_desc[chan].link_id & TRX_CH_LID_SACCH)
@@ -390,14 +390,14 @@ int sched_send_dt_ind(struct trx_instance *trx, struct trx_ts *ts,
 	int bit_error_count, bool dec_failed, bool traffic);
 int sched_send_dt_conf(struct trx_instance *trx, struct trx_ts *ts,
 	struct trx_lchan_state *lchan, uint32_t fn, bool traffic);
-int sched_gsmtap_send(enum trx_lchan_type lchan_type, uint32_t fn, uint8_t tn,
+int sched_gsmtap_send(enum l1sched_lchan_type lchan_type, uint32_t fn, uint8_t tn,
 		      uint16_t band_arfcn, int8_t signal_dbm, uint8_t snr,
 		      const uint8_t *data, size_t data_len);
 
 /* Interleaved TCH/H block TDMA frame mapping */
-uint32_t sched_tchh_block_dl_first_fn(enum trx_lchan_type chan,
+uint32_t sched_tchh_block_dl_first_fn(enum l1sched_lchan_type chan,
 	uint32_t last_fn, bool facch);
-bool sched_tchh_block_map_fn(enum trx_lchan_type chan,
+bool sched_tchh_block_map_fn(enum l1sched_lchan_type chan,
 	uint32_t fn, bool ul, bool facch, bool start);
 
 #define sched_tchh_traffic_start(chan, fn, ul) \
diff --git a/src/host/trxcon/src/sched_lchan_common.c b/src/host/trxcon/src/sched_lchan_common.c
index f5ee86646..e0d0091c7 100644
--- a/src/host/trxcon/src/sched_lchan_common.c
+++ b/src/host/trxcon/src/sched_lchan_common.c
@@ -99,7 +99,7 @@ const char *burst_mask2str(const uint8_t *mask, int bits)
 	return buf;
 }
 
-int sched_gsmtap_send(enum trx_lchan_type lchan_type, uint32_t fn, uint8_t tn,
+int sched_gsmtap_send(enum l1sched_lchan_type lchan_type, uint32_t fn, uint8_t tn,
 		      uint16_t band_arfcn, int8_t signal_dbm, uint8_t snr,
 		      const uint8_t *data, size_t data_len)
 {
@@ -202,7 +202,7 @@ size_t sched_bad_frame_ind(uint8_t *l2, struct trx_lchan_state *lchan)
 {
 	switch (lchan->tch_mode) {
 	case GSM48_CMODE_SPEECH_V1:
-		if (lchan->type == TRXC_TCHF) { /* Full Rate */
+		if (lchan->type == L1SCHED_TCHF) { /* Full Rate */
 			memset(l2, 0x00, GSM_FR_BYTES);
 			l2[0] = 0xd0;
 			return GSM_FR_BYTES;
diff --git a/src/host/trxcon/src/sched_lchan_desc.c b/src/host/trxcon/src/sched_lchan_desc.c
index ed7b141b9..95fd3c3e2 100644
--- a/src/host/trxcon/src/sched_lchan_desc.c
+++ b/src/host/trxcon/src/sched_lchan_desc.c
@@ -69,19 +69,19 @@ int tx_pdtch_fn(struct trx_instance *trx, struct trx_ts *ts,
 		struct trx_lchan_state *lchan,
 		struct sched_burst_req *br);
 
-const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
-	[TRXC_IDLE] = {
+const struct trx_lchan_desc trx_lchan_desc[_L1SCHED_CHAN_MAX] = {
+	[L1SCHED_IDLE] = {
 		.name = "IDLE",
 		.desc = "Idle channel",
 		/* The MS needs to perform neighbour measurements during
 		 * IDLE slots, however this is not implemented (yet). */
 	},
-	[TRXC_FCCH] = {
+	[L1SCHED_FCCH] = {
 		.name = "FCCH", /* 3GPP TS 05.02, section 3.3.2.1 */
 		.desc = "Frequency correction channel",
 		/* Handled by transceiver, nothing to do. */
 	},
-	[TRXC_SCH] = {
+	[L1SCHED_SCH] = {
 		.name = "SCH", /* 3GPP TS 05.02, section 3.3.2.2 */
 		.desc = "Synchronization channel",
 
@@ -90,7 +90,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.flags = TRX_CH_FLAG_AUTO,
 		.rx_fn = rx_sch_fn,
 	},
-	[TRXC_BCCH] = {
+	[L1SCHED_BCCH] = {
 		.name = "BCCH", /* 3GPP TS 05.02, section 3.3.2.3 */
 		.desc = "Broadcast control channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_BCCH,
@@ -103,7 +103,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.flags = TRX_CH_FLAG_AUTO,
 		.rx_fn = rx_data_fn,
 	},
-	[TRXC_RACH] = {
+	[L1SCHED_RACH] = {
 		.name = "RACH", /* 3GPP TS 05.02, section 3.3.3.1 */
 		.desc = "Random access channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_RACH,
@@ -113,7 +113,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.flags = TRX_CH_FLAG_AUTO,
 		.tx_fn = tx_rach_fn,
 	},
-	[TRXC_CCCH] = {
+	[L1SCHED_CCCH] = {
 		.name = "CCCH", /* 3GPP TS 05.02, section 3.3.3.1 */
 		.desc = "Common control channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_CCCH,
@@ -126,7 +126,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.flags = TRX_CH_FLAG_AUTO,
 		.rx_fn = rx_data_fn,
 	},
-	[TRXC_TCHF] = {
+	[L1SCHED_TCHF] = {
 		.name = "TCH/F", /* 3GPP TS 05.02, section 3.2 */
 		.desc = "Full Rate traffic channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_F,
@@ -149,7 +149,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.rx_fn = rx_tchf_fn,
 		.tx_fn = tx_tchf_fn,
 	},
-	[TRXC_TCHH_0] = {
+	[L1SCHED_TCHH_0] = {
 		.name = "TCH/H(0)", /* 3GPP TS 05.02, section 3.2 */
 		.desc = "Half Rate traffic channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_H,
@@ -178,7 +178,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.rx_fn = rx_tchh_fn,
 		.tx_fn = tx_tchh_fn,
 	},
-	[TRXC_TCHH_1] = {
+	[L1SCHED_TCHH_1] = {
 		.name = "TCH/H(1)", /* 3GPP TS 05.02, section 3.2 */
 		.desc = "Half Rate traffic channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_H,
@@ -186,13 +186,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_TCHH_0, see above. */
+		/* Same as for L1SCHED_TCHH_0, see above. */
 		.burst_buf_size = 6 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_tchh_fn,
 		.tx_fn = tx_tchh_fn,
 	},
-	[TRXC_SDCCH4_0] = {
+	[L1SCHED_SDCCH4_0] = {
 		.name = "SDCCH/4(0)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4,
@@ -200,13 +200,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 0,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH4_1] = {
+	[L1SCHED_SDCCH4_1] = {
 		.name = "SDCCH/4(1)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4,
@@ -214,13 +214,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH4_2] = {
+	[L1SCHED_SDCCH4_2] = {
 		.name = "SDCCH/4(2)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 2)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4,
@@ -228,13 +228,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH4_3] = {
+	[L1SCHED_SDCCH4_3] = {
 		.name = "SDCCH/4(3)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 3)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4,
@@ -242,13 +242,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 3,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_0] = {
+	[L1SCHED_SDCCH8_0] = {
 		.name = "SDCCH/8(0)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -256,13 +256,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 0,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_1] = {
+	[L1SCHED_SDCCH8_1] = {
 		.name = "SDCCH/8(1)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -270,13 +270,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_2] = {
+	[L1SCHED_SDCCH8_2] = {
 		.name = "SDCCH/8(2)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 2)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -284,13 +284,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_3] = {
+	[L1SCHED_SDCCH8_3] = {
 		.name = "SDCCH/8(3)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 3)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -298,13 +298,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 3,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_4] = {
+	[L1SCHED_SDCCH8_4] = {
 		.name = "SDCCH/8(4)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 4)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -312,13 +312,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 4,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_5] = {
+	[L1SCHED_SDCCH8_5] = {
 		.name = "SDCCH/8(5)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 5)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -326,13 +326,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 5,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_6] = {
+	[L1SCHED_SDCCH8_6] = {
 		.name = "SDCCH/8(6)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 6)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -340,13 +340,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 6,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SDCCH8_7] = {
+	[L1SCHED_SDCCH8_7] = {
 		.name = "SDCCH/8(7)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Stand-alone dedicated control channel (sub-channel 7)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8,
@@ -354,26 +354,26 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_DEDIC,
 		.ss_nr = 7,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCHTF] = {
+	[L1SCHED_SACCHTF] = {
 		.name = "SACCH/TF", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow TCH/F associated control channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_F | GSMTAP_CHANNEL_ACCH,
 		.chan_nr = RSL_CHAN_Bm_ACCHs,
 		.link_id = TRX_CH_LID_SACCH,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCHTH_0] = {
+	[L1SCHED_SACCHTH_0] = {
 		.name = "SACCH/TH(0)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow TCH/H associated control channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_H | GSMTAP_CHANNEL_ACCH,
@@ -381,13 +381,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 0,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCHTH_1] = {
+	[L1SCHED_SACCHTH_1] = {
 		.name = "SACCH/TH(1)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow TCH/H associated control channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_TCH_H | GSMTAP_CHANNEL_ACCH,
@@ -395,13 +395,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_BCCH (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH4_0] = {
+	[L1SCHED_SACCH4_0] = {
 		.name = "SACCH/4(0)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/4 associated control channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4 | GSMTAP_CHANNEL_ACCH,
@@ -409,13 +409,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 0,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH4_1] = {
+	[L1SCHED_SACCH4_1] = {
 		.name = "SACCH/4(1)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/4 associated control channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4 | GSMTAP_CHANNEL_ACCH,
@@ -423,13 +423,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH4_2] = {
+	[L1SCHED_SACCH4_2] = {
 		.name = "SACCH/4(2)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/4 associated control channel (sub-channel 2)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4 | GSMTAP_CHANNEL_ACCH,
@@ -437,13 +437,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH4_3] = {
+	[L1SCHED_SACCH4_3] = {
 		.name = "SACCH/4(3)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/4 associated control channel (sub-channel 3)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH4 | GSMTAP_CHANNEL_ACCH,
@@ -451,13 +451,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 3,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH4_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH4_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_0] = {
+	[L1SCHED_SACCH8_0] = {
 		.name = "SACCH/8(0)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 0)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -465,13 +465,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 0,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_1] = {
+	[L1SCHED_SACCH8_1] = {
 		.name = "SACCH/8(1)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 1)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -479,13 +479,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 1,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_2] = {
+	[L1SCHED_SACCH8_2] = {
 		.name = "SACCH/8(2)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 2)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -493,13 +493,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_3] = {
+	[L1SCHED_SACCH8_3] = {
 		.name = "SACCH/8(3)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 3)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -507,13 +507,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 3,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_4] = {
+	[L1SCHED_SACCH8_4] = {
 		.name = "SACCH/8(4)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 4)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -521,13 +521,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 4,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_5] = {
+	[L1SCHED_SACCH8_5] = {
 		.name = "SACCH/8(5)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 5)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -535,13 +535,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 5,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_6] = {
+	[L1SCHED_SACCH8_6] = {
 		.name = "SACCH/8(6)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 6)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -549,13 +549,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 6,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_SACCH8_7] = {
+	[L1SCHED_SACCH8_7] = {
 		.name = "SACCH/8(7)", /* 3GPP TS 05.02, section 3.3.4.1 */
 		.desc = "Slow SDCCH/8 associated control channel (sub-channel 7)",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_SDCCH8 | GSMTAP_CHANNEL_ACCH,
@@ -563,13 +563,13 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.link_id = TRX_CH_LID_SACCH,
 		.ss_nr = 7,
 
-		/* Same as for TRXC_BCCH and TRXC_SDCCH8_* (xCCH), see above. */
+		/* Same as for L1SCHED_BCCH and L1SCHED_SDCCH8_* (xCCH), see above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_CBTX,
 		.rx_fn = rx_data_fn,
 		.tx_fn = tx_data_fn,
 	},
-	[TRXC_PDTCH] = {
+	[L1SCHED_PDTCH] = {
 		.name = "PDTCH", /* 3GPP TS 05.02, sections 3.2.4, 3.3.2.4 */
 		.desc = "Packet data traffic & control channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_PDTCH,
@@ -584,7 +584,7 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.rx_fn = rx_pdtch_fn,
 		.tx_fn = tx_pdtch_fn,
 	},
-	[TRXC_PTCCH] = {
+	[L1SCHED_PTCCH] = {
 		.name = "PTCCH", /* 3GPP TS 05.02, section 3.3.4.2 */
 		.desc = "Packet Timing advance control channel",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_PTCCH,
@@ -601,26 +601,26 @@ const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
 		.rx_fn = rx_pdtch_fn,
 		.tx_fn = tx_rach_fn,
 	},
-	[TRXC_SDCCH4_CBCH] = {
+	[L1SCHED_SDCCH4_CBCH] = {
 		.name = "SDCCH/4(CBCH)", /* 3GPP TS 05.02, section 3.3.5 */
 		.desc = "Cell Broadcast channel on SDCCH/4",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_CBCH51,
 		.chan_nr = RSL_CHAN_OSMO_CBCH4,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH (xCCH), but Rx only. See above. */
+		/* Same as for L1SCHED_BCCH (xCCH), but Rx only. See above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.flags = TRX_CH_FLAG_AUTO,
 		.rx_fn = rx_data_fn,
 	},
-	[TRXC_SDCCH8_CBCH] = {
+	[L1SCHED_SDCCH8_CBCH] = {
 		.name = "SDCCH/8(CBCH)", /* 3GPP TS 05.02, section 3.3.5 */
 		.desc = "Cell Broadcast channel on SDCCH/8",
 		.gsmtap_chan_type = GSMTAP_CHANNEL_CBCH52,
 		.chan_nr = RSL_CHAN_OSMO_CBCH8,
 		.ss_nr = 2,
 
-		/* Same as for TRXC_BCCH (xCCH), but Rx only. See above. */
+		/* Same as for L1SCHED_BCCH (xCCH), but Rx only. See above. */
 		.burst_buf_size = 4 * GSM_BURST_PL_LEN,
 		.rx_fn = rx_data_fn,
 	},
diff --git a/src/host/trxcon/src/sched_lchan_tchh.c b/src/host/trxcon/src/sched_lchan_tchh.c
index 3be3a597a..673e5ea03 100644
--- a/src/host/trxcon/src/sched_lchan_tchh.c
+++ b/src/host/trxcon/src/sched_lchan_tchh.c
@@ -90,21 +90,21 @@ const uint8_t tch_h1_ul_facch_block_map[3][6] = {
  *
  * See GSM 05.02, clause 7, table 1
  *
- * @param  chan   channel type (TRXC_TCHH_0 or TRXC_TCHH_1)
+ * @param  chan   channel type (L1SCHED_TCHH_0 or L1SCHED_TCHH_1)
  * @param  fn     the current frame number
  * @param  ul     Uplink or Downlink?
  * @param  facch  FACCH/H or traffic?
  * @param  start  init or end of transmission?
  * @return        true (yes) or false (no)
  */
-bool sched_tchh_block_map_fn(enum trx_lchan_type chan,
+bool sched_tchh_block_map_fn(enum l1sched_lchan_type chan,
 	uint32_t fn, bool ul, bool facch, bool start)
 {
 	uint8_t fn_mf;
 	int i = 0;
 
 	/* Just to be sure */
-	OSMO_ASSERT(chan == TRXC_TCHH_0 || chan == TRXC_TCHH_1);
+	OSMO_ASSERT(chan == L1SCHED_TCHH_0 || chan == L1SCHED_TCHH_1);
 
 	/* Calculate a modulo */
 	fn_mf = facch ? (fn % 26) : (fn % 13);
@@ -121,18 +121,18 @@ bool sched_tchh_block_map_fn(enum trx_lchan_type chan,
 	/* Choose a proper block map */
 	if (facch) {
 		if (ul) {
-			if (chan == TRXC_TCHH_0)
+			if (chan == L1SCHED_TCHH_0)
 				BLOCK_MAP_FN(tch_h0_ul_facch_block_map);
 			else
 				BLOCK_MAP_FN(tch_h1_ul_facch_block_map);
 		} else {
-			if (chan == TRXC_TCHH_0)
+			if (chan == L1SCHED_TCHH_0)
 				BLOCK_MAP_FN(tch_h0_dl_facch_block_map);
 			else
 				BLOCK_MAP_FN(tch_h1_dl_facch_block_map);
 		}
 	} else {
-		if (chan == TRXC_TCHH_0)
+		if (chan == L1SCHED_TCHH_0)
 			BLOCK_MAP_FN(tch_h0_traffic_block_map);
 		else
 			BLOCK_MAP_FN(tch_h1_traffic_block_map);
@@ -147,20 +147,20 @@ bool sched_tchh_block_map_fn(enum trx_lchan_type chan,
  *
  * See GSM 05.02, clause 7, table 1
  *
- * @param  chan      channel type (TRXC_TCHH_0 or TRXC_TCHH_1)
+ * @param  chan      channel type (L1SCHED_TCHH_0 or L1SCHED_TCHH_1)
  * @param  last_fn   frame number of the last burst
  * @param  facch     FACCH/H or traffic?
  * @return           either frame number of the first burst,
  *                   or fn=last_fn if calculation failed
  */
-uint32_t sched_tchh_block_dl_first_fn(enum trx_lchan_type chan,
+uint32_t sched_tchh_block_dl_first_fn(enum l1sched_lchan_type chan,
 	uint32_t last_fn, bool facch)
 {
 	uint8_t fn_mf, fn_diff;
 	int i = 0;
 
 	/* Just to be sure */
-	OSMO_ASSERT(chan == TRXC_TCHH_0 || chan == TRXC_TCHH_1);
+	OSMO_ASSERT(chan == L1SCHED_TCHH_0 || chan == L1SCHED_TCHH_1);
 
 	/* Calculate a modulo */
 	fn_mf = facch ? (last_fn % 26) : (last_fn % 13);
@@ -175,12 +175,12 @@ uint32_t sched_tchh_block_dl_first_fn(enum trx_lchan_type chan,
 
 	/* Choose a proper block map */
 	if (facch) {
-		if (chan == TRXC_TCHH_0)
+		if (chan == L1SCHED_TCHH_0)
 			BLOCK_FIRST_FN(tch_h0_dl_facch_block_map);
 		else
 			BLOCK_FIRST_FN(tch_h1_dl_facch_block_map);
 	} else {
-		if (chan == TRXC_TCHH_0)
+		if (chan == L1SCHED_TCHH_0)
 			BLOCK_FIRST_FN(tch_h0_traffic_block_map);
 		else
 			BLOCK_FIRST_FN(tch_h1_traffic_block_map);
diff --git a/src/host/trxcon/src/sched_mframe.c b/src/host/trxcon/src/sched_mframe.c
index f5fb6c97d..e8125ea62 100644
--- a/src/host/trxcon/src/sched_mframe.c
+++ b/src/host/trxcon/src/sched_mframe.c
@@ -29,1891 +29,1891 @@
 
 /* Non-combined CCCH */
 static const struct trx_frame frame_bcch[51] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_FCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_IDLE,	0,	TRXC_RACH,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_RACH,		0 },
 };
 
 /* Combined CCCH+SDCCH4 */
 static const struct trx_frame frame_bcch_sdcch4[102] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
-	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
-	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
-	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_2,	0 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_2,	1 },
-	{ TRXC_CCCH,		2,	TRXC_SACCH4_2,	2 },
-	{ TRXC_CCCH,		3,	TRXC_SACCH4_2,	3 },
-	{ TRXC_FCCH,		0,	TRXC_SACCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SACCH4_3,	1 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_3,	2 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_3,	3 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
-	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
-	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
-	{ TRXC_SACCH4_0,	0,	TRXC_SDCCH4_1,	1 },
-	{ TRXC_SACCH4_0,	1,	TRXC_SDCCH4_1,	2 },
-	{ TRXC_SACCH4_0,	2,	TRXC_SDCCH4_1,	3 },
-	{ TRXC_SACCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_1,	1,	TRXC_SDCCH4_2,	0 },
-	{ TRXC_SACCH4_1,	2,	TRXC_SDCCH4_2,	1 },
-	{ TRXC_SACCH4_1,	3,	TRXC_SDCCH4_2,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_3,	1 },
+	{ L1SCHED_BCCH,		0,	L1SCHED_SDCCH4_3,	2 },
+	{ L1SCHED_BCCH,		1,	L1SCHED_SDCCH4_3,	3 },
+	{ L1SCHED_BCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_2,	0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_2,	1 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_SACCH4_2,	2 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_SACCH4_2,	3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SACCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SACCH4_3,	1 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_3,	2 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_3,	3 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	1,	L1SCHED_SDCCH4_0,	0 },
+	{ L1SCHED_SDCCH4_3,	2,	L1SCHED_SDCCH4_0,	1 },
+	{ L1SCHED_SDCCH4_3,	3,	L1SCHED_SDCCH4_0,	2 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_0,	3 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_1,	0 },
+	{ L1SCHED_SACCH4_0,	0,	L1SCHED_SDCCH4_1,	1 },
+	{ L1SCHED_SACCH4_0,	1,	L1SCHED_SDCCH4_1,	2 },
+	{ L1SCHED_SACCH4_0,	2,	L1SCHED_SDCCH4_1,	3 },
+	{ L1SCHED_SACCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_1,	1,	L1SCHED_SDCCH4_2,	0 },
+	{ L1SCHED_SACCH4_1,	2,	L1SCHED_SDCCH4_2,	1 },
+	{ L1SCHED_SACCH4_1,	3,	L1SCHED_SDCCH4_2,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SDCCH4_2,	3 },
 
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
-	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
-	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
-	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_0,	0 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_0,	1 },
-	{ TRXC_CCCH,		2,	TRXC_SACCH4_0,	2 },
-	{ TRXC_CCCH,		3,	TRXC_SACCH4_0,	3 },
-	{ TRXC_FCCH,		0,	TRXC_SACCH4_1,	0 },
-	{ TRXC_SCH,		0,	TRXC_SACCH4_1,	1 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_1,	2 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_1,	3 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_2,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
-	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
-	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
-	{ TRXC_SACCH4_2,	0,	TRXC_SDCCH4_1,	1 },
-	{ TRXC_SACCH4_2,	1,	TRXC_SDCCH4_1,	2 },
-	{ TRXC_SACCH4_2,	2,	TRXC_SDCCH4_1,	3 },
-	{ TRXC_SACCH4_2,	3,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_3,	1,	TRXC_SDCCH4_2,	0 },
-	{ TRXC_SACCH4_3,	2,	TRXC_SDCCH4_2,	1 },
-	{ TRXC_SACCH4_3,	3,	TRXC_SDCCH4_2,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_3,	1 },
+	{ L1SCHED_BCCH,		0,	L1SCHED_SDCCH4_3,	2 },
+	{ L1SCHED_BCCH,		1,	L1SCHED_SDCCH4_3,	3 },
+	{ L1SCHED_BCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_0,	0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_0,	1 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_SACCH4_0,	2 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_SACCH4_0,	3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SACCH4_1,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SACCH4_1,	1 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_1,	2 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_1,	3 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_2,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	1,	L1SCHED_SDCCH4_0,	0 },
+	{ L1SCHED_SDCCH4_3,	2,	L1SCHED_SDCCH4_0,	1 },
+	{ L1SCHED_SDCCH4_3,	3,	L1SCHED_SDCCH4_0,	2 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_0,	3 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_1,	0 },
+	{ L1SCHED_SACCH4_2,	0,	L1SCHED_SDCCH4_1,	1 },
+	{ L1SCHED_SACCH4_2,	1,	L1SCHED_SDCCH4_1,	2 },
+	{ L1SCHED_SACCH4_2,	2,	L1SCHED_SDCCH4_1,	3 },
+	{ L1SCHED_SACCH4_2,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_3,	1,	L1SCHED_SDCCH4_2,	0 },
+	{ L1SCHED_SACCH4_3,	2,	L1SCHED_SDCCH4_2,	1 },
+	{ L1SCHED_SACCH4_3,	3,	L1SCHED_SDCCH4_2,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SDCCH4_2,	3 },
 };
 
 static const struct trx_frame frame_bcch_sdcch4_cbch[102] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
-	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
-	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
-	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_IDLE,	0 },
-	{ TRXC_CCCH,		1,	TRXC_IDLE,	1 },
-	{ TRXC_CCCH,		2,	TRXC_IDLE,	2 },
-	{ TRXC_CCCH,		3,	TRXC_IDLE,	3 },
-	{ TRXC_FCCH,		0,	TRXC_SACCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SACCH4_3,	1 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_3,	2 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_3,	3 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
-	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
-	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
-	{ TRXC_SACCH4_0,	0,	TRXC_SDCCH4_1,	1 },
-	{ TRXC_SACCH4_0,	1,	TRXC_SDCCH4_1,	2 },
-	{ TRXC_SACCH4_0,	2,	TRXC_SDCCH4_1,	3 },
-	{ TRXC_SACCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_1,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SACCH4_1,	2,	TRXC_IDLE,	1 },
-	{ TRXC_SACCH4_1,	3,	TRXC_IDLE,	2 },
-	{ TRXC_IDLE,		0,	TRXC_IDLE,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_3,	1 },
+	{ L1SCHED_BCCH,		0,	L1SCHED_SDCCH4_3,	2 },
+	{ L1SCHED_BCCH,		1,	L1SCHED_SDCCH4_3,	3 },
+	{ L1SCHED_BCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_IDLE,		3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SACCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SACCH4_3,	1 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_3,	2 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_3,	3 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	1,	L1SCHED_SDCCH4_0,	0 },
+	{ L1SCHED_SDCCH4_3,	2,	L1SCHED_SDCCH4_0,	1 },
+	{ L1SCHED_SDCCH4_3,	3,	L1SCHED_SDCCH4_0,	2 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_0,	3 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_1,	0 },
+	{ L1SCHED_SACCH4_0,	0,	L1SCHED_SDCCH4_1,	1 },
+	{ L1SCHED_SACCH4_0,	1,	L1SCHED_SDCCH4_1,	2 },
+	{ L1SCHED_SACCH4_0,	2,	L1SCHED_SDCCH4_1,	3 },
+	{ L1SCHED_SACCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_1,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SACCH4_1,	2,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_SACCH4_1,	3,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		3 },
 
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
-	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
-	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
-	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_0,	0 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_0,	1 },
-	{ TRXC_CCCH,		2,	TRXC_SACCH4_0,	2 },
-	{ TRXC_CCCH,		3,	TRXC_SACCH4_0,	3 },
-	{ TRXC_FCCH,		0,	TRXC_SACCH4_1,	0 },
-	{ TRXC_SCH,		0,	TRXC_SACCH4_1,	1 },
-	{ TRXC_CCCH,		0,	TRXC_SACCH4_1,	2 },
-	{ TRXC_CCCH,		1,	TRXC_SACCH4_1,	3 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
-	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
-	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	1,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	2,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_CBCH,	3,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
-	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
-	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
-	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
-	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SDCCH4_1,	1 },
-	{ TRXC_IDLE,		1,	TRXC_SDCCH4_1,	2 },
-	{ TRXC_IDLE,		2,	TRXC_SDCCH4_1,	3 },
-	{ TRXC_IDLE,		3,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_3,	0,	TRXC_RACH,	0 },
-	{ TRXC_SACCH4_3,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SACCH4_3,	2,	TRXC_IDLE,	1 },
-	{ TRXC_SACCH4_3,	3,	TRXC_IDLE,	2 },
-	{ TRXC_IDLE,		0,	TRXC_IDLE,	3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_3,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_3,	1 },
+	{ L1SCHED_BCCH,		0,	L1SCHED_SDCCH4_3,	2 },
+	{ L1SCHED_BCCH,		1,	L1SCHED_SDCCH4_3,	3 },
+	{ L1SCHED_BCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_BCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_0,	0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_0,	1 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_SACCH4_0,	2 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_SACCH4_0,	3 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SACCH4_1,	0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SACCH4_1,	1 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_SACCH4_1,	2 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_SACCH4_1,	3 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_CCCH,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_0,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_1,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SCH,		0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	1,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	2,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_CBCH,	3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SDCCH4_3,	1,	L1SCHED_SDCCH4_0,	0 },
+	{ L1SCHED_SDCCH4_3,	2,	L1SCHED_SDCCH4_0,	1 },
+	{ L1SCHED_SDCCH4_3,	3,	L1SCHED_SDCCH4_0,	2 },
+	{ L1SCHED_FCCH,		0,	L1SCHED_SDCCH4_0,	3 },
+	{ L1SCHED_SCH,		0,	L1SCHED_SDCCH4_1,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SDCCH4_1,	1 },
+	{ L1SCHED_IDLE,		1,	L1SCHED_SDCCH4_1,	2 },
+	{ L1SCHED_IDLE,		2,	L1SCHED_SDCCH4_1,	3 },
+	{ L1SCHED_IDLE,		3,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_3,	0,	L1SCHED_RACH,		0 },
+	{ L1SCHED_SACCH4_3,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SACCH4_3,	2,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_SACCH4_3,	3,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		3 },
 };
 
 static const struct trx_frame frame_sdcch8[102] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
-	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_5,	1 },
-	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_5,	2 },
-	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_5,	3 },
-	{ TRXC_SDCCH8_1,	0,	TRXC_SACCH8_6,	0 },
-	{ TRXC_SDCCH8_1,	1,	TRXC_SACCH8_6,	1 },
-	{ TRXC_SDCCH8_1,	2,	TRXC_SACCH8_6,	2 },
-	{ TRXC_SDCCH8_1,	3,	TRXC_SACCH8_6,	3 },
-	{ TRXC_SDCCH8_2,	0,	TRXC_SACCH8_7,	0 },
-	{ TRXC_SDCCH8_2,	1,	TRXC_SACCH8_7,	1 },
-	{ TRXC_SDCCH8_2,	2,	TRXC_SACCH8_7,	2 },
-	{ TRXC_SDCCH8_2,	3,	TRXC_SACCH8_7,	3 },
-	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
-	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
-	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
-	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
-	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
-	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
-	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
-	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
-	{ TRXC_SDCCH8_5,	3,	TRXC_SDCCH8_2,	0 },
-	{ TRXC_SDCCH8_6,	0,	TRXC_SDCCH8_2,	1 },
-	{ TRXC_SDCCH8_6,	1,	TRXC_SDCCH8_2,	2 },
-	{ TRXC_SDCCH8_6,	2,	TRXC_SDCCH8_2,	3 },
-	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
-	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
-	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
-	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
-	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
-	{ TRXC_SACCH8_0,	0,	TRXC_SDCCH8_4,	1 },
-	{ TRXC_SACCH8_0,	1,	TRXC_SDCCH8_4,	2 },
-	{ TRXC_SACCH8_0,	2,	TRXC_SDCCH8_4,	3 },
-	{ TRXC_SACCH8_0,	3,	TRXC_SDCCH8_5,	0 },
-	{ TRXC_SACCH8_1,	0,	TRXC_SDCCH8_5,	1 },
-	{ TRXC_SACCH8_1,	1,	TRXC_SDCCH8_5,	2 },
-	{ TRXC_SACCH8_1,	2,	TRXC_SDCCH8_5,	3 },
-	{ TRXC_SACCH8_1,	3,	TRXC_SDCCH8_6,	0 },
-	{ TRXC_SACCH8_2,	0,	TRXC_SDCCH8_6,	1 },
-	{ TRXC_SACCH8_2,	1,	TRXC_SDCCH8_6,	2 },
-	{ TRXC_SACCH8_2,	2,	TRXC_SDCCH8_6,	3 },
-	{ TRXC_SACCH8_2,	3,	TRXC_SDCCH8_7,	0 },
-	{ TRXC_SACCH8_3,	0,	TRXC_SDCCH8_7,	1 },
-	{ TRXC_SACCH8_3,	1,	TRXC_SDCCH8_7,	2 },
-	{ TRXC_SACCH8_3,	2,	TRXC_SDCCH8_7,	3 },
-	{ TRXC_SACCH8_3,	3,	TRXC_SACCH8_0,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	1 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_SDCCH8_0,	0,	L1SCHED_SACCH8_5,	0 },
+	{ L1SCHED_SDCCH8_0,	1,	L1SCHED_SACCH8_5,	1 },
+	{ L1SCHED_SDCCH8_0,	2,	L1SCHED_SACCH8_5,	2 },
+	{ L1SCHED_SDCCH8_0,	3,	L1SCHED_SACCH8_5,	3 },
+	{ L1SCHED_SDCCH8_1,	0,	L1SCHED_SACCH8_6,	0 },
+	{ L1SCHED_SDCCH8_1,	1,	L1SCHED_SACCH8_6,	1 },
+	{ L1SCHED_SDCCH8_1,	2,	L1SCHED_SACCH8_6,	2 },
+	{ L1SCHED_SDCCH8_1,	3,	L1SCHED_SACCH8_6,	3 },
+	{ L1SCHED_SDCCH8_2,	0,	L1SCHED_SACCH8_7,	0 },
+	{ L1SCHED_SDCCH8_2,	1,	L1SCHED_SACCH8_7,	1 },
+	{ L1SCHED_SDCCH8_2,	2,	L1SCHED_SACCH8_7,	2 },
+	{ L1SCHED_SDCCH8_2,	3,	L1SCHED_SACCH8_7,	3 },
+	{ L1SCHED_SDCCH8_3,	0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	2,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	3,	L1SCHED_SDCCH8_0,	0 },
+	{ L1SCHED_SDCCH8_4,	0,	L1SCHED_SDCCH8_0,	1 },
+	{ L1SCHED_SDCCH8_4,	1,	L1SCHED_SDCCH8_0,	2 },
+	{ L1SCHED_SDCCH8_4,	2,	L1SCHED_SDCCH8_0,	3 },
+	{ L1SCHED_SDCCH8_4,	3,	L1SCHED_SDCCH8_1,	0 },
+	{ L1SCHED_SDCCH8_5,	0,	L1SCHED_SDCCH8_1,	1 },
+	{ L1SCHED_SDCCH8_5,	1,	L1SCHED_SDCCH8_1,	2 },
+	{ L1SCHED_SDCCH8_5,	2,	L1SCHED_SDCCH8_1,	3 },
+	{ L1SCHED_SDCCH8_5,	3,	L1SCHED_SDCCH8_2,	0 },
+	{ L1SCHED_SDCCH8_6,	0,	L1SCHED_SDCCH8_2,	1 },
+	{ L1SCHED_SDCCH8_6,	1,	L1SCHED_SDCCH8_2,	2 },
+	{ L1SCHED_SDCCH8_6,	2,	L1SCHED_SDCCH8_2,	3 },
+	{ L1SCHED_SDCCH8_6,	3,	L1SCHED_SDCCH8_3,	0 },
+	{ L1SCHED_SDCCH8_7,	0,	L1SCHED_SDCCH8_3,	1 },
+	{ L1SCHED_SDCCH8_7,	1,	L1SCHED_SDCCH8_3,	2 },
+	{ L1SCHED_SDCCH8_7,	2,	L1SCHED_SDCCH8_3,	3 },
+	{ L1SCHED_SDCCH8_7,	3,	L1SCHED_SDCCH8_4,	0 },
+	{ L1SCHED_SACCH8_0,	0,	L1SCHED_SDCCH8_4,	1 },
+	{ L1SCHED_SACCH8_0,	1,	L1SCHED_SDCCH8_4,	2 },
+	{ L1SCHED_SACCH8_0,	2,	L1SCHED_SDCCH8_4,	3 },
+	{ L1SCHED_SACCH8_0,	3,	L1SCHED_SDCCH8_5,	0 },
+	{ L1SCHED_SACCH8_1,	0,	L1SCHED_SDCCH8_5,	1 },
+	{ L1SCHED_SACCH8_1,	1,	L1SCHED_SDCCH8_5,	2 },
+	{ L1SCHED_SACCH8_1,	2,	L1SCHED_SDCCH8_5,	3 },
+	{ L1SCHED_SACCH8_1,	3,	L1SCHED_SDCCH8_6,	0 },
+	{ L1SCHED_SACCH8_2,	0,	L1SCHED_SDCCH8_6,	1 },
+	{ L1SCHED_SACCH8_2,	1,	L1SCHED_SDCCH8_6,	2 },
+	{ L1SCHED_SACCH8_2,	2,	L1SCHED_SDCCH8_6,	3 },
+	{ L1SCHED_SACCH8_2,	3,	L1SCHED_SDCCH8_7,	0 },
+	{ L1SCHED_SACCH8_3,	0,	L1SCHED_SDCCH8_7,	1 },
+	{ L1SCHED_SACCH8_3,	1,	L1SCHED_SDCCH8_7,	2 },
+	{ L1SCHED_SACCH8_3,	2,	L1SCHED_SDCCH8_7,	3 },
+	{ L1SCHED_SACCH8_3,	3,	L1SCHED_SACCH8_0,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	1 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	3 },
 
-	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_1,	0 },
-	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_1,	1 },
-	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_1,	2 },
-	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_1,	3 },
-	{ TRXC_SDCCH8_1,	0,	TRXC_SACCH8_2,	0 },
-	{ TRXC_SDCCH8_1,	1,	TRXC_SACCH8_2,	1 },
-	{ TRXC_SDCCH8_1,	2,	TRXC_SACCH8_2,	2 },
-	{ TRXC_SDCCH8_1,	3,	TRXC_SACCH8_2,	3 },
-	{ TRXC_SDCCH8_2,	0,	TRXC_SACCH8_3,	0 },
-	{ TRXC_SDCCH8_2,	1,	TRXC_SACCH8_3,	1 },
-	{ TRXC_SDCCH8_2,	2,	TRXC_SACCH8_3,	2 },
-	{ TRXC_SDCCH8_2,	3,	TRXC_SACCH8_3,	3 },
-	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
-	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
-	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
-	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
-	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
-	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
-	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
-	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
-	{ TRXC_SDCCH8_5,	3,	TRXC_SDCCH8_2,	0 },
-	{ TRXC_SDCCH8_6,	0,	TRXC_SDCCH8_2,	1 },
-	{ TRXC_SDCCH8_6,	1,	TRXC_SDCCH8_2,	2 },
-	{ TRXC_SDCCH8_6,	2,	TRXC_SDCCH8_2,	3 },
-	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
-	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
-	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
-	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
-	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
-	{ TRXC_SACCH8_4,	0,	TRXC_SDCCH8_4,	1 },
-	{ TRXC_SACCH8_4,	1,	TRXC_SDCCH8_4,	2 },
-	{ TRXC_SACCH8_4,	2,	TRXC_SDCCH8_4,	3 },
-	{ TRXC_SACCH8_4,	3,	TRXC_SDCCH8_5,	0 },
-	{ TRXC_SACCH8_5,	0,	TRXC_SDCCH8_5,	1 },
-	{ TRXC_SACCH8_5,	1,	TRXC_SDCCH8_5,	2 },
-	{ TRXC_SACCH8_5,	2,	TRXC_SDCCH8_5,	3 },
-	{ TRXC_SACCH8_5,	3,	TRXC_SDCCH8_6,	0 },
-	{ TRXC_SACCH8_6,	0,	TRXC_SDCCH8_6,	1 },
-	{ TRXC_SACCH8_6,	1,	TRXC_SDCCH8_6,	2 },
-	{ TRXC_SACCH8_6,	2,	TRXC_SDCCH8_6,	3 },
-	{ TRXC_SACCH8_6,	3,	TRXC_SDCCH8_7,	0 },
-	{ TRXC_SACCH8_7,	0,	TRXC_SDCCH8_7,	1 },
-	{ TRXC_SACCH8_7,	1,	TRXC_SDCCH8_7,	2 },
-	{ TRXC_SACCH8_7,	2,	TRXC_SDCCH8_7,	3 },
-	{ TRXC_SACCH8_7,	3,	TRXC_SACCH8_4,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	1 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
+	{ L1SCHED_SDCCH8_0,	0,	L1SCHED_SACCH8_1,	0 },
+	{ L1SCHED_SDCCH8_0,	1,	L1SCHED_SACCH8_1,	1 },
+	{ L1SCHED_SDCCH8_0,	2,	L1SCHED_SACCH8_1,	2 },
+	{ L1SCHED_SDCCH8_0,	3,	L1SCHED_SACCH8_1,	3 },
+	{ L1SCHED_SDCCH8_1,	0,	L1SCHED_SACCH8_2,	0 },
+	{ L1SCHED_SDCCH8_1,	1,	L1SCHED_SACCH8_2,	1 },
+	{ L1SCHED_SDCCH8_1,	2,	L1SCHED_SACCH8_2,	2 },
+	{ L1SCHED_SDCCH8_1,	3,	L1SCHED_SACCH8_2,	3 },
+	{ L1SCHED_SDCCH8_2,	0,	L1SCHED_SACCH8_3,	0 },
+	{ L1SCHED_SDCCH8_2,	1,	L1SCHED_SACCH8_3,	1 },
+	{ L1SCHED_SDCCH8_2,	2,	L1SCHED_SACCH8_3,	2 },
+	{ L1SCHED_SDCCH8_2,	3,	L1SCHED_SACCH8_3,	3 },
+	{ L1SCHED_SDCCH8_3,	0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	2,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	3,	L1SCHED_SDCCH8_0,	0 },
+	{ L1SCHED_SDCCH8_4,	0,	L1SCHED_SDCCH8_0,	1 },
+	{ L1SCHED_SDCCH8_4,	1,	L1SCHED_SDCCH8_0,	2 },
+	{ L1SCHED_SDCCH8_4,	2,	L1SCHED_SDCCH8_0,	3 },
+	{ L1SCHED_SDCCH8_4,	3,	L1SCHED_SDCCH8_1,	0 },
+	{ L1SCHED_SDCCH8_5,	0,	L1SCHED_SDCCH8_1,	1 },
+	{ L1SCHED_SDCCH8_5,	1,	L1SCHED_SDCCH8_1,	2 },
+	{ L1SCHED_SDCCH8_5,	2,	L1SCHED_SDCCH8_1,	3 },
+	{ L1SCHED_SDCCH8_5,	3,	L1SCHED_SDCCH8_2,	0 },
+	{ L1SCHED_SDCCH8_6,	0,	L1SCHED_SDCCH8_2,	1 },
+	{ L1SCHED_SDCCH8_6,	1,	L1SCHED_SDCCH8_2,	2 },
+	{ L1SCHED_SDCCH8_6,	2,	L1SCHED_SDCCH8_2,	3 },
+	{ L1SCHED_SDCCH8_6,	3,	L1SCHED_SDCCH8_3,	0 },
+	{ L1SCHED_SDCCH8_7,	0,	L1SCHED_SDCCH8_3,	1 },
+	{ L1SCHED_SDCCH8_7,	1,	L1SCHED_SDCCH8_3,	2 },
+	{ L1SCHED_SDCCH8_7,	2,	L1SCHED_SDCCH8_3,	3 },
+	{ L1SCHED_SDCCH8_7,	3,	L1SCHED_SDCCH8_4,	0 },
+	{ L1SCHED_SACCH8_4,	0,	L1SCHED_SDCCH8_4,	1 },
+	{ L1SCHED_SACCH8_4,	1,	L1SCHED_SDCCH8_4,	2 },
+	{ L1SCHED_SACCH8_4,	2,	L1SCHED_SDCCH8_4,	3 },
+	{ L1SCHED_SACCH8_4,	3,	L1SCHED_SDCCH8_5,	0 },
+	{ L1SCHED_SACCH8_5,	0,	L1SCHED_SDCCH8_5,	1 },
+	{ L1SCHED_SACCH8_5,	1,	L1SCHED_SDCCH8_5,	2 },
+	{ L1SCHED_SACCH8_5,	2,	L1SCHED_SDCCH8_5,	3 },
+	{ L1SCHED_SACCH8_5,	3,	L1SCHED_SDCCH8_6,	0 },
+	{ L1SCHED_SACCH8_6,	0,	L1SCHED_SDCCH8_6,	1 },
+	{ L1SCHED_SACCH8_6,	1,	L1SCHED_SDCCH8_6,	2 },
+	{ L1SCHED_SACCH8_6,	2,	L1SCHED_SDCCH8_6,	3 },
+	{ L1SCHED_SACCH8_6,	3,	L1SCHED_SDCCH8_7,	0 },
+	{ L1SCHED_SACCH8_7,	0,	L1SCHED_SDCCH8_7,	1 },
+	{ L1SCHED_SACCH8_7,	1,	L1SCHED_SDCCH8_7,	2 },
+	{ L1SCHED_SACCH8_7,	2,	L1SCHED_SDCCH8_7,	3 },
+	{ L1SCHED_SACCH8_7,	3,	L1SCHED_SACCH8_4,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	1 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	3 },
 };
 
 static const struct trx_frame frame_sdcch8_cbch[102] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
-	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_5,	1 },
-	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_5,	2 },
-	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_5,	3 },
-	{ TRXC_SDCCH8_1,	0,	TRXC_SACCH8_6,	0 },
-	{ TRXC_SDCCH8_1,	1,	TRXC_SACCH8_6,	1 },
-	{ TRXC_SDCCH8_1,	2,	TRXC_SACCH8_6,	2 },
-	{ TRXC_SDCCH8_1,	3,	TRXC_SACCH8_6,	3 },
-	{ TRXC_SDCCH8_CBCH,	0,	TRXC_SACCH8_7,	0 },
-	{ TRXC_SDCCH8_CBCH,	1,	TRXC_SACCH8_7,	1 },
-	{ TRXC_SDCCH8_CBCH,	2,	TRXC_SACCH8_7,	2 },
-	{ TRXC_SDCCH8_CBCH,	3,	TRXC_SACCH8_7,	3 },
-	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
-	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
-	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
-	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
-	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
-	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
-	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
-	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
-	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
-	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
-	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
-	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
-	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
-	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
-	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
-	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
-	{ TRXC_SACCH8_0,	0,	TRXC_SDCCH8_4,	1 },
-	{ TRXC_SACCH8_0,	1,	TRXC_SDCCH8_4,	2 },
-	{ TRXC_SACCH8_0,	2,	TRXC_SDCCH8_4,	3 },
-	{ TRXC_SACCH8_0,	3,	TRXC_SDCCH8_5,	0 },
-	{ TRXC_SACCH8_1,	0,	TRXC_SDCCH8_5,	1 },
-	{ TRXC_SACCH8_1,	1,	TRXC_SDCCH8_5,	2 },
-	{ TRXC_SACCH8_1,	2,	TRXC_SDCCH8_5,	3 },
-	{ TRXC_SACCH8_1,	3,	TRXC_SDCCH8_6,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SDCCH8_6,	1 },
-	{ TRXC_IDLE,		1,	TRXC_SDCCH8_6,	2 },
-	{ TRXC_IDLE,		2,	TRXC_SDCCH8_6,	3 },
-	{ TRXC_IDLE,		3,	TRXC_SDCCH8_7,	0 },
-	{ TRXC_SACCH8_3,	0,	TRXC_SDCCH8_7,	1 },
-	{ TRXC_SACCH8_3,	1,	TRXC_SDCCH8_7,	2 },
-	{ TRXC_SACCH8_3,	2,	TRXC_SDCCH8_7,	3 },
-	{ TRXC_SACCH8_3,	3,	TRXC_SACCH8_0,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	1 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_SDCCH8_0,	0,	L1SCHED_SACCH8_5,	0 },
+	{ L1SCHED_SDCCH8_0,	1,	L1SCHED_SACCH8_5,	1 },
+	{ L1SCHED_SDCCH8_0,	2,	L1SCHED_SACCH8_5,	2 },
+	{ L1SCHED_SDCCH8_0,	3,	L1SCHED_SACCH8_5,	3 },
+	{ L1SCHED_SDCCH8_1,	0,	L1SCHED_SACCH8_6,	0 },
+	{ L1SCHED_SDCCH8_1,	1,	L1SCHED_SACCH8_6,	1 },
+	{ L1SCHED_SDCCH8_1,	2,	L1SCHED_SACCH8_6,	2 },
+	{ L1SCHED_SDCCH8_1,	3,	L1SCHED_SACCH8_6,	3 },
+	{ L1SCHED_SDCCH8_CBCH,	0,	L1SCHED_SACCH8_7,	0 },
+	{ L1SCHED_SDCCH8_CBCH,	1,	L1SCHED_SACCH8_7,	1 },
+	{ L1SCHED_SDCCH8_CBCH,	2,	L1SCHED_SACCH8_7,	2 },
+	{ L1SCHED_SDCCH8_CBCH,	3,	L1SCHED_SACCH8_7,	3 },
+	{ L1SCHED_SDCCH8_3,	0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	2,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	3,	L1SCHED_SDCCH8_0,	0 },
+	{ L1SCHED_SDCCH8_4,	0,	L1SCHED_SDCCH8_0,	1 },
+	{ L1SCHED_SDCCH8_4,	1,	L1SCHED_SDCCH8_0,	2 },
+	{ L1SCHED_SDCCH8_4,	2,	L1SCHED_SDCCH8_0,	3 },
+	{ L1SCHED_SDCCH8_4,	3,	L1SCHED_SDCCH8_1,	0 },
+	{ L1SCHED_SDCCH8_5,	0,	L1SCHED_SDCCH8_1,	1 },
+	{ L1SCHED_SDCCH8_5,	1,	L1SCHED_SDCCH8_1,	2 },
+	{ L1SCHED_SDCCH8_5,	2,	L1SCHED_SDCCH8_1,	3 },
+	{ L1SCHED_SDCCH8_5,	3,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_6,	0,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_SDCCH8_6,	1,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_SDCCH8_6,	2,	L1SCHED_IDLE,		3 },
+	{ L1SCHED_SDCCH8_6,	3,	L1SCHED_SDCCH8_3,	0 },
+	{ L1SCHED_SDCCH8_7,	0,	L1SCHED_SDCCH8_3,	1 },
+	{ L1SCHED_SDCCH8_7,	1,	L1SCHED_SDCCH8_3,	2 },
+	{ L1SCHED_SDCCH8_7,	2,	L1SCHED_SDCCH8_3,	3 },
+	{ L1SCHED_SDCCH8_7,	3,	L1SCHED_SDCCH8_4,	0 },
+	{ L1SCHED_SACCH8_0,	0,	L1SCHED_SDCCH8_4,	1 },
+	{ L1SCHED_SACCH8_0,	1,	L1SCHED_SDCCH8_4,	2 },
+	{ L1SCHED_SACCH8_0,	2,	L1SCHED_SDCCH8_4,	3 },
+	{ L1SCHED_SACCH8_0,	3,	L1SCHED_SDCCH8_5,	0 },
+	{ L1SCHED_SACCH8_1,	0,	L1SCHED_SDCCH8_5,	1 },
+	{ L1SCHED_SACCH8_1,	1,	L1SCHED_SDCCH8_5,	2 },
+	{ L1SCHED_SACCH8_1,	2,	L1SCHED_SDCCH8_5,	3 },
+	{ L1SCHED_SACCH8_1,	3,	L1SCHED_SDCCH8_6,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SDCCH8_6,	1 },
+	{ L1SCHED_IDLE,		1,	L1SCHED_SDCCH8_6,	2 },
+	{ L1SCHED_IDLE,		2,	L1SCHED_SDCCH8_6,	3 },
+	{ L1SCHED_IDLE,		3,	L1SCHED_SDCCH8_7,	0 },
+	{ L1SCHED_SACCH8_3,	0,	L1SCHED_SDCCH8_7,	1 },
+	{ L1SCHED_SACCH8_3,	1,	L1SCHED_SDCCH8_7,	2 },
+	{ L1SCHED_SACCH8_3,	2,	L1SCHED_SDCCH8_7,	3 },
+	{ L1SCHED_SACCH8_3,	3,	L1SCHED_SACCH8_0,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	1 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_0,	3 },
 
-	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_1,	0 },
-	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_1,	1 },
-	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_1,	2 },
-	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_1,	3 },
-	{ TRXC_SDCCH8_1,	0,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_1,	1,	TRXC_IDLE,	1 },
-	{ TRXC_SDCCH8_1,	2,	TRXC_IDLE,	2 },
-	{ TRXC_SDCCH8_1,	3,	TRXC_IDLE,	3 },
-	{ TRXC_SDCCH8_CBCH,	0,	TRXC_SACCH8_3,	0 },
-	{ TRXC_SDCCH8_CBCH,	1,	TRXC_SACCH8_3,	1 },
-	{ TRXC_SDCCH8_CBCH,	2,	TRXC_SACCH8_3,	2 },
-	{ TRXC_SDCCH8_CBCH,	3,	TRXC_SACCH8_3,	3 },
-	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
-	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
-	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
-	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
-	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
-	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
-	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
-	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
-	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
-	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
-	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
-	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
-	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
-	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
-	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
-	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
-	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
-	{ TRXC_SACCH8_4,	0,	TRXC_SDCCH8_4,	1 },
-	{ TRXC_SACCH8_4,	1,	TRXC_SDCCH8_4,	2 },
-	{ TRXC_SACCH8_4,	2,	TRXC_SDCCH8_4,	3 },
-	{ TRXC_SACCH8_4,	3,	TRXC_SDCCH8_5,	0 },
-	{ TRXC_SACCH8_5,	0,	TRXC_SDCCH8_5,	1 },
-	{ TRXC_SACCH8_5,	1,	TRXC_SDCCH8_5,	2 },
-	{ TRXC_SACCH8_5,	2,	TRXC_SDCCH8_5,	3 },
-	{ TRXC_SACCH8_5,	3,	TRXC_SDCCH8_6,	0 },
-	{ TRXC_SACCH8_6,	0,	TRXC_SDCCH8_6,	1 },
-	{ TRXC_SACCH8_6,	1,	TRXC_SDCCH8_6,	2 },
-	{ TRXC_SACCH8_6,	2,	TRXC_SDCCH8_6,	3 },
-	{ TRXC_SACCH8_6,	3,	TRXC_SDCCH8_7,	0 },
-	{ TRXC_SACCH8_7,	0,	TRXC_SDCCH8_7,	1 },
-	{ TRXC_SACCH8_7,	1,	TRXC_SDCCH8_7,	2 },
-	{ TRXC_SACCH8_7,	2,	TRXC_SDCCH8_7,	3 },
-	{ TRXC_SACCH8_7,	3,	TRXC_SACCH8_4,	0 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	1 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	2 },
-	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
+	{ L1SCHED_SDCCH8_0,	0,	L1SCHED_SACCH8_1,	0 },
+	{ L1SCHED_SDCCH8_0,	1,	L1SCHED_SACCH8_1,	1 },
+	{ L1SCHED_SDCCH8_0,	2,	L1SCHED_SACCH8_1,	2 },
+	{ L1SCHED_SDCCH8_0,	3,	L1SCHED_SACCH8_1,	3 },
+	{ L1SCHED_SDCCH8_1,	0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_1,	1,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_SDCCH8_1,	2,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_SDCCH8_1,	3,	L1SCHED_IDLE,		3 },
+	{ L1SCHED_SDCCH8_CBCH,	0,	L1SCHED_SACCH8_3,	0 },
+	{ L1SCHED_SDCCH8_CBCH,	1,	L1SCHED_SACCH8_3,	1 },
+	{ L1SCHED_SDCCH8_CBCH,	2,	L1SCHED_SACCH8_3,	2 },
+	{ L1SCHED_SDCCH8_CBCH,	3,	L1SCHED_SACCH8_3,	3 },
+	{ L1SCHED_SDCCH8_3,	0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	1,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	2,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_3,	3,	L1SCHED_SDCCH8_0,	0 },
+	{ L1SCHED_SDCCH8_4,	0,	L1SCHED_SDCCH8_0,	1 },
+	{ L1SCHED_SDCCH8_4,	1,	L1SCHED_SDCCH8_0,	2 },
+	{ L1SCHED_SDCCH8_4,	2,	L1SCHED_SDCCH8_0,	3 },
+	{ L1SCHED_SDCCH8_4,	3,	L1SCHED_SDCCH8_1,	0 },
+	{ L1SCHED_SDCCH8_5,	0,	L1SCHED_SDCCH8_1,	1 },
+	{ L1SCHED_SDCCH8_5,	1,	L1SCHED_SDCCH8_1,	2 },
+	{ L1SCHED_SDCCH8_5,	2,	L1SCHED_SDCCH8_1,	3 },
+	{ L1SCHED_SDCCH8_5,	3,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_SDCCH8_6,	0,	L1SCHED_IDLE,		1 },
+	{ L1SCHED_SDCCH8_6,	1,	L1SCHED_IDLE,		2 },
+	{ L1SCHED_SDCCH8_6,	2,	L1SCHED_IDLE,		3 },
+	{ L1SCHED_SDCCH8_6,	3,	L1SCHED_SDCCH8_3,	0 },
+	{ L1SCHED_SDCCH8_7,	0,	L1SCHED_SDCCH8_3,	1 },
+	{ L1SCHED_SDCCH8_7,	1,	L1SCHED_SDCCH8_3,	2 },
+	{ L1SCHED_SDCCH8_7,	2,	L1SCHED_SDCCH8_3,	3 },
+	{ L1SCHED_SDCCH8_7,	3,	L1SCHED_SDCCH8_4,	0 },
+	{ L1SCHED_SACCH8_4,	0,	L1SCHED_SDCCH8_4,	1 },
+	{ L1SCHED_SACCH8_4,	1,	L1SCHED_SDCCH8_4,	2 },
+	{ L1SCHED_SACCH8_4,	2,	L1SCHED_SDCCH8_4,	3 },
+	{ L1SCHED_SACCH8_4,	3,	L1SCHED_SDCCH8_5,	0 },
+	{ L1SCHED_SACCH8_5,	0,	L1SCHED_SDCCH8_5,	1 },
+	{ L1SCHED_SACCH8_5,	1,	L1SCHED_SDCCH8_5,	2 },
+	{ L1SCHED_SACCH8_5,	2,	L1SCHED_SDCCH8_5,	3 },
+	{ L1SCHED_SACCH8_5,	3,	L1SCHED_SDCCH8_6,	0 },
+	{ L1SCHED_SACCH8_6,	0,	L1SCHED_SDCCH8_6,	1 },
+	{ L1SCHED_SACCH8_6,	1,	L1SCHED_SDCCH8_6,	2 },
+	{ L1SCHED_SACCH8_6,	2,	L1SCHED_SDCCH8_6,	3 },
+	{ L1SCHED_SACCH8_6,	3,	L1SCHED_SDCCH8_7,	0 },
+	{ L1SCHED_SACCH8_7,	0,	L1SCHED_SDCCH8_7,	1 },
+	{ L1SCHED_SACCH8_7,	1,	L1SCHED_SDCCH8_7,	2 },
+	{ L1SCHED_SACCH8_7,	2,	L1SCHED_SDCCH8_7,	3 },
+	{ L1SCHED_SACCH8_7,	3,	L1SCHED_SACCH8_4,	0 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	1 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	2 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_SACCH8_4,	3 },
 };
 
 static const struct trx_frame frame_tchf_ts0[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
 };
 
 static const struct trx_frame frame_tchf_ts1[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
 };
 
 static const struct trx_frame frame_tchf_ts2[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
 };
 
 static const struct trx_frame frame_tchf_ts3[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
 };
 
 static const struct trx_frame frame_tchf_ts4[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
 };
 
 static const struct trx_frame frame_tchf_ts5[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
 };
 
 static const struct trx_frame frame_tchf_ts6[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
 };
 
 static const struct trx_frame frame_tchf_ts7[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	1,	TRXC_SACCHTF,	1 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	2,	TRXC_SACCHTF,	2 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	3,	TRXC_SACCHTF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
-	{ TRXC_TCHF,	1,	TRXC_TCHF,	1 },
-	{ TRXC_TCHF,	2,	TRXC_TCHF,	2 },
-	{ TRXC_TCHF,	3,	TRXC_TCHF,	3 },
-	{ TRXC_SACCHTF,	0,	TRXC_SACCHTF,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	1,	L1SCHED_SACCHTF,	1 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	2,	L1SCHED_SACCHTF,	2 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	3,	L1SCHED_SACCHTF,	3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_TCHF,		0,	L1SCHED_TCHF,		0 },
+	{ L1SCHED_TCHF,		1,	L1SCHED_TCHF,		1 },
+	{ L1SCHED_TCHF,		2,	L1SCHED_TCHF,		2 },
+	{ L1SCHED_TCHF,		3,	L1SCHED_TCHF,		3 },
+	{ L1SCHED_SACCHTF,	0,	L1SCHED_SACCHTF,	0 },
 };
 
 static const struct trx_frame frame_tchh_ts01[104] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	0,	TRXC_SACCHTH_0,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	0,	TRXC_SACCHTH_1,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	1,	TRXC_SACCHTH_0,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	1,	TRXC_SACCHTH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	2,	TRXC_SACCHTH_0,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	2,	TRXC_SACCHTH_1,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	3,	TRXC_SACCHTH_0,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	3,	TRXC_SACCHTH_1,	3 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	0,	L1SCHED_SACCHTH_0,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	0,	L1SCHED_SACCHTH_1,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	1,	L1SCHED_SACCHTH_0,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	1,	L1SCHED_SACCHTH_1,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	2,	L1SCHED_SACCHTH_0,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	2,	L1SCHED_SACCHTH_1,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	3,	L1SCHED_SACCHTH_0,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	3,	L1SCHED_SACCHTH_1,	3 },
 };
 
 static const struct trx_frame frame_tchh_ts23[104] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	3,	TRXC_SACCHTH_0,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	3,	TRXC_SACCHTH_1,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	0,	TRXC_SACCHTH_0,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	0,	TRXC_SACCHTH_1,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	1,	TRXC_SACCHTH_0,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	1,	TRXC_SACCHTH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	2,	TRXC_SACCHTH_0,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	2,	TRXC_SACCHTH_1,	2 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	3,	L1SCHED_SACCHTH_0,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	3,	L1SCHED_SACCHTH_1,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	0,	L1SCHED_SACCHTH_0,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	0,	L1SCHED_SACCHTH_1,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	1,	L1SCHED_SACCHTH_0,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	1,	L1SCHED_SACCHTH_1,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	2,	L1SCHED_SACCHTH_0,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	2,	L1SCHED_SACCHTH_1,	2 },
 };
 
 static const struct trx_frame frame_tchh_ts45[104] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	2,	TRXC_SACCHTH_0,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	2,	TRXC_SACCHTH_1,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	3,	TRXC_SACCHTH_0,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	3,	TRXC_SACCHTH_1,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	0,	TRXC_SACCHTH_0,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	0,	TRXC_SACCHTH_1,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	1,	TRXC_SACCHTH_0,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	1,	TRXC_SACCHTH_1,	1 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	2,	L1SCHED_SACCHTH_0,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	2,	L1SCHED_SACCHTH_1,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	3,	L1SCHED_SACCHTH_0,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	3,	L1SCHED_SACCHTH_1,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	0,	L1SCHED_SACCHTH_0,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	0,	L1SCHED_SACCHTH_1,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	1,	L1SCHED_SACCHTH_0,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	1,	L1SCHED_SACCHTH_1,	1 },
 };
 
 static const struct trx_frame frame_tchh_ts67[104] = {
-	/* dl_chan		dl_bid	ul_chan		ul_bid */
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	1,	TRXC_SACCHTH_0,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	1,	TRXC_SACCHTH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	2,	TRXC_SACCHTH_0,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	2,	TRXC_SACCHTH_1,	2 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	3,	TRXC_SACCHTH_0,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	3,	TRXC_SACCHTH_1,	3 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_0,	0,	TRXC_SACCHTH_0,	0 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_TCHH_0,		0,	TRXC_TCHH_0,	0 },
-	{ TRXC_TCHH_1,		0,	TRXC_TCHH_1,	0 },
-	{ TRXC_TCHH_0,		1,	TRXC_TCHH_0,	1 },
-	{ TRXC_TCHH_1,		1,	TRXC_TCHH_1,	1 },
-	{ TRXC_SACCHTH_1,	0,	TRXC_SACCHTH_1,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	1,	L1SCHED_SACCHTH_0,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	1,	L1SCHED_SACCHTH_1,	1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	2,	L1SCHED_SACCHTH_0,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	2,	L1SCHED_SACCHTH_1,	2 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	3,	L1SCHED_SACCHTH_0,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	3,	L1SCHED_SACCHTH_1,	3 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_0,	0,	L1SCHED_SACCHTH_0,	0 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_TCHH_0,	0,	L1SCHED_TCHH_0,		0 },
+	{ L1SCHED_TCHH_1,	0,	L1SCHED_TCHH_1,		0 },
+	{ L1SCHED_TCHH_0,	1,	L1SCHED_TCHH_0,		1 },
+	{ L1SCHED_TCHH_1,	1,	L1SCHED_TCHH_1,		1 },
+	{ L1SCHED_SACCHTH_1,	0,	L1SCHED_SACCHTH_1,	0 },
 };
 
 static const struct trx_frame frame_pdch[104] = {
-	/* dl_chan	dl_bid	ul_chan		ul_bid */
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PTCCH,	0,	TRXC_PTCCH,	0 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PTCCH,	1,	TRXC_PTCCH,	1 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PTCCH,	2,	TRXC_PTCCH,	2 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PTCCH,	3,	TRXC_PTCCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_PDTCH,	0,	TRXC_PDTCH,	0 },
-	{ TRXC_PDTCH,	1,	TRXC_PDTCH,	1 },
-	{ TRXC_PDTCH,	2,	TRXC_PDTCH,	2 },
-	{ TRXC_PDTCH,	3,	TRXC_PDTCH,	3 },
-	{ TRXC_IDLE,	0,	TRXC_IDLE,	0 },
+	/* dl_chan		dl_bid	ul_chan			ul_bid */
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PTCCH,	0,	L1SCHED_PTCCH,		0 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PTCCH,	1,	L1SCHED_PTCCH,		1 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PTCCH,	2,	L1SCHED_PTCCH,		2 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PTCCH,	3,	L1SCHED_PTCCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_PDTCH,	0,	L1SCHED_PDTCH,		0 },
+	{ L1SCHED_PDTCH,	1,	L1SCHED_PDTCH,		1 },
+	{ L1SCHED_PDTCH,	2,	L1SCHED_PDTCH,		2 },
+	{ L1SCHED_PDTCH,	3,	L1SCHED_PDTCH,		3 },
+	{ L1SCHED_IDLE,		0,	L1SCHED_IDLE,		0 },
 };
 
 /* Logical channel mask for a single channel */
@@ -1923,42 +1923,42 @@ static const struct trx_frame frame_pdch[104] = {
 /* Logical channel mask for BCCH+CCCH */
 #define M64_BCCH_CCCH \
 	(uint64_t) 0x00 \
-		| M64(TRXC_FCCH) \
-		| M64(TRXC_SCH)  \
-		| M64(TRXC_BCCH) \
-		| M64(TRXC_RACH) \
-		| M64(TRXC_CCCH)
+		| M64(L1SCHED_FCCH) \
+		| M64(L1SCHED_SCH)  \
+		| M64(L1SCHED_BCCH) \
+		| M64(L1SCHED_RACH) \
+		| M64(L1SCHED_CCCH)
 
 /* Logical channel mask for SDCCH4 (with SACCH, all sub-channels) */
 #define M64_SDCCH4 \
 	(uint64_t) 0x00 \
-		| M64(TRXC_SDCCH4_0) | M64(TRXC_SACCH4_0) \
-		| M64(TRXC_SDCCH4_1) | M64(TRXC_SACCH4_1) \
-		| M64(TRXC_SDCCH4_2) | M64(TRXC_SACCH4_2) \
-		| M64(TRXC_SDCCH4_3) | M64(TRXC_SACCH4_3)
+		| M64(L1SCHED_SDCCH4_0) | M64(L1SCHED_SACCH4_0) \
+		| M64(L1SCHED_SDCCH4_1) | M64(L1SCHED_SACCH4_1) \
+		| M64(L1SCHED_SDCCH4_2) | M64(L1SCHED_SACCH4_2) \
+		| M64(L1SCHED_SDCCH4_3) | M64(L1SCHED_SACCH4_3)
 
 /* Logical channel mask for SDCCH8 (with SACCH, all sub-channels) */
 #define M64_SDCCH8 \
 	(uint64_t) 0x00 \
-		| M64(TRXC_SDCCH8_0) | M64(TRXC_SACCH8_0) \
-		| M64(TRXC_SDCCH8_1) | M64(TRXC_SACCH8_1) \
-		| M64(TRXC_SDCCH8_2) | M64(TRXC_SACCH8_2) \
-		| M64(TRXC_SDCCH8_3) | M64(TRXC_SACCH8_3) \
-		| M64(TRXC_SDCCH8_4) | M64(TRXC_SACCH8_4) \
-		| M64(TRXC_SDCCH8_5) | M64(TRXC_SACCH8_5) \
-		| M64(TRXC_SDCCH8_6) | M64(TRXC_SACCH8_6) \
-		| M64(TRXC_SDCCH8_7) | M64(TRXC_SACCH8_7)
+		| M64(L1SCHED_SDCCH8_0) | M64(L1SCHED_SACCH8_0) \
+		| M64(L1SCHED_SDCCH8_1) | M64(L1SCHED_SACCH8_1) \
+		| M64(L1SCHED_SDCCH8_2) | M64(L1SCHED_SACCH8_2) \
+		| M64(L1SCHED_SDCCH8_3) | M64(L1SCHED_SACCH8_3) \
+		| M64(L1SCHED_SDCCH8_4) | M64(L1SCHED_SACCH8_4) \
+		| M64(L1SCHED_SDCCH8_5) | M64(L1SCHED_SACCH8_5) \
+		| M64(L1SCHED_SDCCH8_6) | M64(L1SCHED_SACCH8_6) \
+		| M64(L1SCHED_SDCCH8_7) | M64(L1SCHED_SACCH8_7)
 
 /* Logical channel mask for TCH/F (with SACCH) */
 #define M64_TCHF \
 	(uint64_t) 0x00 \
-		| M64(TRXC_TCHF) | M64(TRXC_SACCHTF)
+		| M64(L1SCHED_TCHF) | M64(L1SCHED_SACCHTF)
 
 /* Logical channel mask for TCH/H (with SACCH, all sub-channels) */
 #define M64_TCHH \
 	(uint64_t) 0x00 \
-		| M64(TRXC_TCHH_0) | M64(TRXC_SACCHTH_0) \
-		| M64(TRXC_TCHH_1) | M64(TRXC_SACCHTH_1)
+		| M64(L1SCHED_TCHH_0) | M64(L1SCHED_SACCHTH_0) \
+		| M64(L1SCHED_TCHH_1) | M64(L1SCHED_SACCHTH_1)
 
 /**
  * A few notes about frame count:
@@ -1991,7 +1991,7 @@ static const struct trx_multiframe layouts[] = {
 	{
 		GSM_PCHAN_CCCH_SDCCH4_CBCH, "BCCH+CCCH+SDCCH/4+SACCH/4+CBCH",
 		102,	0xff,
-		M64_BCCH_CCCH | M64_SDCCH4 | M64(TRXC_SDCCH4_CBCH),
+		M64_BCCH_CCCH | M64_SDCCH4 | M64(L1SCHED_SDCCH4_CBCH),
 		frame_bcch_sdcch4_cbch
 	},
 	{
@@ -2003,7 +2003,7 @@ static const struct trx_multiframe layouts[] = {
 	{
 		GSM_PCHAN_SDCCH8_SACCH8C_CBCH, "SDCCH/8+SACCH/8+CBCH",
 		102,	0xff,
-		M64_SDCCH8 | M64(TRXC_SDCCH8_CBCH),
+		M64_SDCCH8 | M64(L1SCHED_SDCCH8_CBCH),
 		frame_sdcch8_cbch
 	},
 	{
@@ -2081,7 +2081,7 @@ static const struct trx_multiframe layouts[] = {
 	{
 		GSM_PCHAN_PDCH, "PDCH",
 		104,	0xff,
-		M64(TRXC_PDTCH) | M64(TRXC_PTCCH),
+		M64(L1SCHED_PDTCH) | M64(L1SCHED_PTCCH),
 		frame_pdch
 	},
 };
diff --git a/src/host/trxcon/src/sched_prim.c b/src/host/trxcon/src/sched_prim.c
index 847ebd384..9d0101c76 100644
--- a/src/host/trxcon/src/sched_prim.c
+++ b/src/host/trxcon/src/sched_prim.c
@@ -48,7 +48,7 @@
 int sched_prim_init(void *ctx, struct trx_ts_prim **prim,
 	size_t pl_len, uint8_t chan_nr, uint8_t link_id)
 {
-	enum trx_lchan_type lchan_type;
+	enum l1sched_lchan_type lchan_type;
 	struct trx_ts_prim *new_prim;
 	uint8_t len;
 
@@ -314,7 +314,7 @@ static struct trx_ts_prim *prim_dequeue_sacch(struct llist_head *queue,
 
 /* Dequeues a primitive of a given channel type */
 static struct trx_ts_prim *prim_dequeue_one(struct llist_head *queue,
-	enum trx_lchan_type lchan_type)
+	enum l1sched_lchan_type lchan_type)
 {
 	struct trx_ts_prim *prim;
 
@@ -344,13 +344,13 @@ static struct trx_ts_prim *prim_dequeue_one(struct llist_head *queue,
  *
  * @param  queue      transmit queue to take a prim from
  * @param  lchan_type required channel type of a primitive,
- *                    e.g. TRXC_TCHF, TRXC_TCHH_0, or TRXC_TCHH_1
+ *                    e.g. L1SCHED_TCHF, L1SCHED_TCHH_0, or L1SCHED_TCHH_1
  * @param  facch      FACCH (true) or speech (false) prim?
  * @return            either a FACCH, or a TCH primitive if found,
  *                    otherwise NULL
  */
 static struct trx_ts_prim *prim_dequeue_tch(struct llist_head *queue,
-	enum trx_lchan_type lchan_type, bool facch)
+	enum l1sched_lchan_type lchan_type, bool facch)
 {
 	struct trx_ts_prim *prim;
 
@@ -388,8 +388,8 @@ static struct trx_ts_prim *prim_dequeue_tch_f(struct llist_head *queue)
 	struct trx_ts_prim *tch;
 
 	/* Attempt to find a pair of both FACCH/F and TCH/F frames */
-	facch = prim_dequeue_tch(queue, TRXC_TCHF, true);
-	tch = prim_dequeue_tch(queue, TRXC_TCHF, false);
+	facch = prim_dequeue_tch(queue, L1SCHED_TCHF, true);
+	tch = prim_dequeue_tch(queue, L1SCHED_TCHF, false);
 
 	/* Prioritize FACCH/F, if found */
 	if (facch) {
@@ -429,7 +429,7 @@ static struct trx_ts_prim *prim_dequeue_tch_f(struct llist_head *queue)
  *                    otherwise NULL
  */
 static struct trx_ts_prim *prim_dequeue_tch_h(struct llist_head *queue,
-	uint32_t fn, enum trx_lchan_type lchan_type)
+	uint32_t fn, enum l1sched_lchan_type lchan_type)
 {
 	struct trx_ts_prim *facch;
 	struct trx_ts_prim *tch;
@@ -485,12 +485,12 @@ struct trx_ts_prim *sched_prim_dequeue(struct llist_head *queue,
 
 	switch (lchan->type) {
 	/* TCH/F requires FACCH/F prioritization */
-	case TRXC_TCHF:
+	case L1SCHED_TCHF:
 		return prim_dequeue_tch_f(queue);
 
 	/* FACCH/H prioritization is a bit more complex */
-	case TRXC_TCHH_0:
-	case TRXC_TCHH_1:
+	case L1SCHED_TCHH_0:
+	case L1SCHED_TCHH_1:
 		return prim_dequeue_tch_h(queue, fn, lchan->type);
 
 	/* Other kinds of logical channels */
@@ -521,7 +521,7 @@ void sched_prim_drop(struct trx_lchan_state *lchan)
  */
 int sched_prim_dummy(struct trx_lchan_state *lchan)
 {
-	enum trx_lchan_type chan = lchan->type;
+	enum l1sched_lchan_type chan = lchan->type;
 	uint8_t tch_mode = lchan->tch_mode;
 	struct trx_ts_prim *prim;
 	uint8_t prim_buffer[40];
diff --git a/src/host/trxcon/src/sched_trx.c b/src/host/trxcon/src/sched_trx.c
index 618ce8bd6..fe9f78363 100644
--- a/src/host/trxcon/src/sched_trx.c
+++ b/src/host/trxcon/src/sched_trx.c
@@ -47,7 +47,7 @@ static void sched_frame_clck_cb(struct trx_sched *sched)
 	const struct trx_frame *frame;
 	struct trx_lchan_state *lchan;
 	trx_lchan_tx_func *handler;
-	enum trx_lchan_type chan;
+	enum l1sched_lchan_type chan;
 	uint8_t offset;
 	struct trx_ts *ts;
 	int i;
@@ -124,8 +124,8 @@ static void sched_frame_clck_cb(struct trx_sched *sched)
 
 		/* Handover RACH needs to be handled regardless of the
 		 * current channel type and the associated handler. */
-		if (PRIM_IS_RACH(lchan->prim) && lchan->prim->chan != TRXC_RACH)
-			handler = trx_lchan_desc[TRXC_RACH].tx_fn;
+		if (PRIM_IS_RACH(lchan->prim) && lchan->prim->chan != L1SCHED_RACH)
+			handler = trx_lchan_desc[L1SCHED_RACH].tx_fn;
 
 		/* Poke lchan handler */
 		handler(trx, ts, lchan, &br[i]);
@@ -263,7 +263,7 @@ int sched_trx_configure_ts(struct trx_instance *trx, int tn,
 	enum gsm_phys_chan_config config)
 {
 	struct trx_lchan_state *lchan;
-	enum trx_lchan_type type;
+	enum l1sched_lchan_type type;
 	struct trx_ts *ts;
 
 	/* Try to find specified ts */
@@ -294,7 +294,7 @@ int sched_trx_configure_ts(struct trx_instance *trx, int tn,
 	INIT_LLIST_HEAD(&ts->lchans);
 
 	/* Allocate channel states */
-	for (type = 0; type < _TRX_CHAN_MAX; type++) {
+	for (type = 0; type < _L1SCHED_CHAN_MAX; type++) {
 		if (!LAYOUT_HAS_LCHAN(ts->mf_layout, type))
 			continue;
 
@@ -387,7 +387,7 @@ int sched_trx_start_ciphering(struct trx_ts *ts, uint8_t algo,
 }
 
 struct trx_lchan_state *sched_trx_find_lchan(struct trx_ts *ts,
-	enum trx_lchan_type chan)
+	enum l1sched_lchan_type chan)
 {
 	struct trx_lchan_state *lchan;
 
@@ -426,7 +426,7 @@ int sched_trx_set_lchans(struct trx_ts *ts, uint8_t chan_nr, int active, uint8_t
 	return rc;
 }
 
-int sched_trx_activate_lchan(struct trx_ts *ts, enum trx_lchan_type chan)
+int sched_trx_activate_lchan(struct trx_ts *ts, enum l1sched_lchan_type chan)
 {
 	const struct trx_lchan_desc *lchan_desc = &trx_lchan_desc[chan];
 	struct trx_lchan_state *lchan;
@@ -516,7 +516,7 @@ static void sched_trx_reset_lchan(struct trx_lchan_state *lchan)
 	memset(&lchan->tdma, 0x00, sizeof(lchan->tdma));
 }
 
-int sched_trx_deactivate_lchan(struct trx_ts *ts, enum trx_lchan_type chan)
+int sched_trx_deactivate_lchan(struct trx_ts *ts, enum l1sched_lchan_type chan)
 {
 	struct trx_lchan_state *lchan;
 
@@ -585,18 +585,18 @@ enum gsm_phys_chan_config sched_trx_chan_nr2pchan_config(uint8_t chan_nr)
 	return GSM_PCHAN_NONE;
 }
 
-enum trx_lchan_type sched_trx_chan_nr2lchan_type(uint8_t chan_nr,
+enum l1sched_lchan_type sched_trx_chan_nr2lchan_type(uint8_t chan_nr,
 	uint8_t link_id)
 {
 	int i;
 
 	/* Iterate over all known lchan types */
-	for (i = 0; i < _TRX_CHAN_MAX; i++)
+	for (i = 0; i < _L1SCHED_CHAN_MAX; i++)
 		if (trx_lchan_desc[i].chan_nr == (chan_nr & 0xf8))
 			if (trx_lchan_desc[i].link_id == link_id)
 				return i;
 
-	return TRXC_IDLE;
+	return L1SCHED_IDLE;
 }
 
 static void sched_trx_a5_burst_dec(struct trx_lchan_state *lchan,
@@ -717,7 +717,7 @@ int sched_trx_handle_rx_burst(struct trx_instance *trx, uint8_t tn,
 	struct trx_ts *ts;
 
 	trx_lchan_rx_func *handler;
-	enum trx_lchan_type chan;
+	enum l1sched_lchan_type chan;
 	uint8_t offset, bid;
 	int rc;