fixed typos in comments
Signed-off-by: Steve Markgraf <steve@steve-m.de>
This commit is contained in:
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579edab27a
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be9ea273b3
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@ -85,7 +85,7 @@ int main(void)
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keypad_set_handler(&key_handler);
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/* Dump clock config aftee PLL set */
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/* Dump clock config after PLL set */
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calypso_clk_dump();
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puts(hr);
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@ -120,7 +120,7 @@ static void l1test_state_change(enum l1test_state new_state)
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}
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}
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/* completion call-back for the L1 Sync Pwer Measurement */
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/* completion call-back for the L1 Sync Power Measurement */
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static void l1s_signal_cb(struct l1_signal *sig)
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{
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uint16_t i, next_arfcn;
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@ -176,7 +176,7 @@ int main(void)
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keypad_set_handler(&key_handler);
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/* Dump clock config aftee PLL set */
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/* Dump clock config after PLL set */
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calypso_clk_dump();
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puts(hr);
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@ -65,7 +65,7 @@ int main(void)
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keypad_set_handler(&key_handler);
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/* Dump clock config aftee PLL set */
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/* Dump clock config after PLL set */
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calypso_clk_dump();
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puts(hr);
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@ -71,7 +71,7 @@ static void myHexdump(uint8_t *data, int len)
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#define SIM_UPDATE_RECORD 0xDC /* Write record of a record based file */
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#define SIM_SEEK 0xA2 /* Seek in a record based file */
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#define SIM_INCREASE 0x32 /* Increase a record in a record based file */
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#define SIM_VERIFY_CHV 0x20 /* Authenicate with card (enter pin) */
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#define SIM_VERIFY_CHV 0x20 /* Authenticate with card (enter pin) */
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#define SIM_CHANGE_CHV 0x24 /* Change pin */
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#define SIM_DISABLE_CHV 0x26 /* Disable pin so that no authentication is needed anymore */
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#define SIM_ENABLE_CHV 0x28 /* Enable pin, authentication is now needed again */
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@ -83,7 +83,7 @@ static void myHexdump(uint8_t *data, int len)
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#define SIM_GET_RESPONSE 0xC0 /* Get the response of a command from the card */
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/* File identifiers (filenames)
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The file identifiers are the standartized file identfiers mentiond in the
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The file identifiers are the standardized file identifiers mentioned in the
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GSM-11-11 specification. */
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#define SIM_MF 0x3F00
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#define SIM_EF_ICCID 0x2FE2
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@ -159,7 +159,7 @@ uint16_t sim_readbinary(uint8_t offset_high, uint8_t offset_low, uint8_t length,
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/* FIXME: We need proper calibrated delay loops at some point! */
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/* FIXME: We need properly calibrated delay loops at some point! */
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void delay_us(unsigned int us)
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{
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volatile unsigned int i;
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@ -201,8 +201,8 @@ void do_sim_test(void)
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puts("----------------SIMTEST----8<-----------------\n");
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/* Initalize Sim-Controller driver */
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puts("Initalizing driver:\n");
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/* Initialize Sim-Controller driver */
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puts("Initializing driver:\n");
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calypso_sim_init();
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/* Power up sim and display ATR */
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@ -288,7 +288,7 @@ int main(void)
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keypad_set_handler(&key_handler);
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/* Dump clock config aftee PLL set */
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/* Dump clock config after PLL set */
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calypso_clk_dump();
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puts(hr);
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@ -1,6 +1,6 @@
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#include <delay.h>
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/* FIXME: We need proper calibrated delay loops at some point! */
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/* FIXME: We need properly calibrated delay loops at some point! */
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void delay_us(unsigned int us)
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{
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volatile unsigned int i;
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@ -48,10 +48,10 @@
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#define API_SIZE 0x2000U /* in words */
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#define BASE_API_RAM 0xffd00000 /* Base address of API RAM form ARM point of view */
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#define BASE_API_RAM 0xffd00000 /* Base address of API RAM from ARM point of view */
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#define DSP_BASE_API 0x0800 /* Base address of API RAM for DSP */
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#define DSP_BASE_API_MIRROR 0xe000 /* Base address of API RAM for DSP (API boot mirrot */
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#define DSP_BASE_API_MIRROR 0xe000 /* Base address of API RAM for DSP (API boot mirror) */
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#define DSP_START 0x7000 /* DSP Start address */
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/* Boot loader */
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@ -446,7 +446,7 @@ static void dsp_db_init(void)
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void dsp_power_on(void)
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{
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/* proabaly a good idea to initialize the whole API area to a know value */
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/* probably a good idea to initialize the whole API area to a known value */
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dsp_api_memset((uint16_t *)BASE_API_RAM, API_SIZE * 2); // size is in words
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dsp_set_params((int16_t *)&dsp_params, sizeof(dsp_params)/2);
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@ -559,8 +559,8 @@ void dsp_load_tch_param(struct gsm_time *next_time,
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a5fn1 = (uint16_t)next_time->t1;
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dsp_api.db_w->d_fn = fn; /* Fn_sid & Fn_report */
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dsp_api.db_w->a_a5fn[0] = a5fn0; /* cyphering FN part 1 */
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dsp_api.db_w->a_a5fn[1] = a5fn1; /* cyphering FN part 2 */
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dsp_api.db_w->a_a5fn[0] = a5fn0; /* ciphering FN part 1 */
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dsp_api.db_w->a_a5fn[1] = a5fn1; /* ciphering FN part 2 */
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dsp_api.db_w->d_ctrl_tch = d_ctrl_tch; /* Channel config. */
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}
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@ -671,7 +671,7 @@ void dsp_dump(void)
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dsp_upload_sections_api(dsp_dumpcode, DSP_BASE_API);
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dsp_bl_start_at(DSP_DUMPCODE_START);
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/* our dump code actually simulates the boot loaded
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/* our dump code actually simulates the boot loader
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* but with added read commands */
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dsp_bl_wait_ready();
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@ -72,7 +72,7 @@ int i2c_write(uint8_t chip, uint32_t addr, int alen, const uint8_t *buffer, int
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writeb(chip & 0x3f, I2C_REG(DEVICE_REG));
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writeb(addr & 0xff, I2C_REG(ADDRESS_REG));
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/* we have to tell the controler how many bits we'll put into the fifo ?!? */
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/* we have to tell the controller how many bits we'll put into the fifo ?!? */
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writeb(len-1, I2C_REG(CONF_FIFO_REG));
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/* fill the FIFO */
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@ -34,8 +34,8 @@ static int sim_tx_character_count = 0; /* How many bytes have been transmitted b
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static int sim_tx_character_length = 0; /* How many bytes have to be transmitted by calypso_sim_transmit() */
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static uint8_t *rx_buffer = 0; /* RX-Buffer that is issued by calypso_sim_receive() */
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static uint8_t *tx_buffer = 0; /* TX-Buffer that is issued by calypso_sim_transmit() */
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volatile static int rxDoneFlag = 0; /* Used for rx syncronization instead of a semaphore in calypso_sim_receive() */
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volatile static int txDoneFlag = 0; /* Used for rx syncronization instead of a semaphore in calypso_sim_transmit() */
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volatile static int rxDoneFlag = 0; /* Used for rx synchronization instead of a semaphore in calypso_sim_receive() */
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volatile static int txDoneFlag = 0; /* Used for rx synchronization instead of a semaphore in calypso_sim_transmit() */
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/* Display Register dump */
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void calypso_sim_regdump(void)
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@ -194,7 +194,7 @@ void tpu_enable(int active)
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#endif
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}
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/* Enable or Disable the clock of teh TPU Module */
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/* Enable or Disable the clock of the TPU Module */
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void tpu_clk_enable(int active)
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{
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uint16_t reg = readw(TPU_REG(TPU_CTRL));
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@ -90,7 +90,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
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if (cs < 0 || cs > 4)
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return -1;
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/* FIXME uwire_init always select CS0 for now */
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/* FIXME uwire_init always selects CS0 for now */
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printd("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
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@ -159,7 +159,7 @@ int sercomm_drv_pull(uint8_t *ch)
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if (sercomm.tx.state == RX_ST_ESCAPE) {
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/* we've already transmitted the ESCAPE octet,
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* we now need to trnsmit the escaped data */
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* we now need to transmit the escaped data */
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*ch = *sercomm.tx.next_char++;
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sercomm.tx.state = RX_ST_DATA;
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} else if (sercomm.tx.next_char >= sercomm.tx.msg->tail) {
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@ -199,7 +199,7 @@ int sercomm_register_rx_cb(uint8_t dlci, dlci_cb_t cb)
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return 0;
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}
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/* dispatch an incomnig message once it is completely received */
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/* dispatch an incoming message once it is completely received */
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static void dispatch_rx_msg(uint8_t dlci, struct msgb *msg)
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{
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if (dlci >= ARRAY_SIZE(sercomm.rx.dlci_handler) ||
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@ -268,7 +268,7 @@ int sercomm_drv_rx_char(uint8_t ch)
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ch ^= (1 << 5);
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ptr = msgb_put(sercomm.rx.msg, 1);
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*ptr = ch;
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/* transition back to nromal DATA state */
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/* transition back to normal DATA state */
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sercomm.rx.state = RX_ST_DATA;
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break;
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}
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@ -10,7 +10,7 @@
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void tpu_reset(int active);
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/* Enable or Disable a new scenario loaded into the TPU */
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void tpu_enable(int active);
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/* Enable or Disable the clock of teh TPU Module */
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/* Enable or Disable the clock of the TPU Module */
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void tpu_clk_enable(int active);
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/* Enable Frame Interrupt generation on next frame. DSP will reset it */
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void tpu_dsp_frameirq_enable(void);
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@ -60,7 +60,7 @@ static struct afc_state afc_state = {
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* DAC = 1MHz / 947MHz * FreqErr(Hz) / AFCslop(ppm/LSB)
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* where:
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* 947 MHz is the center of EGSM
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* AFCslope is coded F1.15, thus a normalization factor of 2^15 aplpies
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* AFCslope is coded F1.15, thus a normalization factor of 2^15 applies
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*/
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#define AFC_NORM_FACTOR_GSM ((1<<15) / 947)
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@ -76,7 +76,7 @@ static int l1s_nb_resp(__unused uint8_t p1, uint8_t burst_id, uint16_t p3)
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return 0;
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}
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/* DSP burst ID needs to corespond with what we expect */
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/* DSP burst ID needs to correspond with what we expect */
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if (dsp_api.db_r->d_burst_d != burst_id) {
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printf("BURST ID %u!=%u\n", dsp_api.db_r->d_burst_d, burst_id);
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return 0;
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@ -54,7 +54,7 @@
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static uint32_t last_txnb_fn;
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/* p1: type of operation (0: one NB, 1: one RACH burst, 2: four NB */
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/* p1: type of operation (0: one NB, 1: one RACH burst, 2: four NB) */
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static int l1s_tx_resp(__unused uint8_t p1, __unused uint8_t burst_id,
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__unused uint16_t p3)
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{
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@ -70,7 +70,7 @@ static int l1s_tx_resp(__unused uint8_t p1, __unused uint8_t burst_id,
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return 0;
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}
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/* p1: type of operation (0: one NB, 1: one RACH burst, 2: four NB */
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/* p1: type of operation (0: one NB, 1: one RACH burst, 2: four NB) */
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static int l1s_tx_cmd(uint8_t p1, uint8_t burst_id, uint16_t p3)
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{
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uint16_t arfcn;
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@ -144,7 +144,7 @@ void l1s_tx_test(uint8_t base_fn, uint8_t type)
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if (type == 0) {// one normal burst
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tdma_schedule(base_fn, &l1s_tx_cmd, 0, 0, 0, 3);
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tdma_schedule(base_fn + 2, &l1s_tx_resp, 0, 0, 0, 3);
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} else if (type == 2) { // four normal burst
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} else if (type == 2) { // four normal bursts
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tdma_schedule(base_fn, &l1s_tx_cmd, 2, 0, 0, 3);
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tdma_schedule(base_fn + 1, &l1s_tx_cmd, 2, 1, 0, 3);
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tdma_schedule(base_fn + 2, &l1s_tx_resp, 2, 0, 0, 3);
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@ -33,7 +33,7 @@ static struct sched_gsmtime_event sched_gsmtime_events[16];
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static LLIST_HEAD(active_evts);
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static LLIST_HEAD(inactive_evts);
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/* Scheduling of a tdma_sched_item list one-shot at a givnen GSM time */
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/* Scheduling of a tdma_sched_item list one-shot at a given GSM time */
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int sched_gsmtime(const struct tdma_sched_item *si, uint32_t fn, uint16_t p3)
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{
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struct llist_head *lh;
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@ -38,7 +38,7 @@
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enum trf6151_reg {
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REG_RX = 0, /* RF general settings */
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REG_PLL = 1, /* PLL settings */
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REG_PWR = 2, /* Power on/off funcitonal blocks */
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REG_PWR = 2, /* Power on/off functional blocks */
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REG_CFG = 3, /* Transceiver and PA controller settings */
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REG_TEST1 = 4,
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REG_TEST2 = 5,
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@ -87,7 +87,7 @@ enum trf6151_reg {
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#define PLL_VAL(a, b) ((a << 3) | (((b)-64) << 9))
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/* All values in qbits unless otherwise speciifed */
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/* All values in qbits unless otherwise specified */
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#define TRF6151_LDO_DELAY_TS 6 /* six TDMA frames (at least 25ms) */
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#define TRF6151_RX_PLL_DELAY 184 /* 170 us */
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#define TRF6151_TX_PLL_DELAY 260 /* 240 us */
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