fw: Add display driver for K200i/K220i
Change-Id: I90fbe583983de34f39ec402d5a35712dfe57222b
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@ -35,6 +35,7 @@ FB_e99_OBJS=$(FB_OBJS) fb/fb_rgb332.o fb/fb_ssd1783.o
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FB_e86_OBJS=$(FB_OBJS) fb/fb_rgb332.o fb/fb_td014.o
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FB_j100_OBJS=$(FB_OBJS) fb/fb_rgb332.o fb/fb_ssd1963.o
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FB_dpl10_OBJS=$(FB_OBJS) fb/fb_rgb332.o fb/fb_s6b33b1x.o
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FB_k2x0_OBJS=$(FB_OBJS) fb/fb_rgb332.o fb/fb_k2x0.o
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FB_dummy_OBJS=$(FB_OBJS) fb/fb_dummy.o
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# TI Calypso
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@ -104,7 +105,7 @@ BOARD_se_j100_ENVIRONMENTS=$(compal_COMMON_ENVIRONMENTS)
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BOARD_se_k2x0_OBJS=$(calypso_COMMON_OBJS) board/se_k2x0/init.o \
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board/se_k2x0/rffe_k2x0.o \
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board/gta0x/rf_tables.o board/gta0x/afcparams.o \
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board/common/readcal_tiffs.o battery/dummy.o $(FB_dummy_OBJS)
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board/common/readcal_tiffs.o battery/dummy.o $(FB_k2x0_OBJS)
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BOARD_se_k2x0_ENVIRONMENTS=highram
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#
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@ -47,29 +47,36 @@
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#include "keymap.h"
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#define ASIC_CONF_REG 0xfffef008
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#define ARMIO_LATCH_OUT 0xfffe4802
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#define IO_CNTL_REG 0xfffe4804
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#define IO_CONF_REG 0xfffef00a
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static void board_io_init(void)
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{
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uint16_t reg;
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reg = readw(ASIC_CONF_REG);
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/* Set LPG and PWL pin mux */
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reg |= (1 << 6) | (1 << 4);
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/* TWL3025: Set SPI+RIF RX clock to rising edge */
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reg |= (1 << 13) | (1 << 14);
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writew(reg, ASIC_CONF_REG);
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writew(0xc060, IO_CNTL_REG);
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writew(0x03fd, IO_CONF_REG);
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/* set default IO state */
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writew(0x1f83, ARMIO_LATCH_OUT);
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}
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void board_init(int with_irq)
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{
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/* Disable watchdog (compal loader leaves it enabled) */
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wdog_enable(0);
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/* Configure the memory interface - TODO: adapt for K2x0i, right now just
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* copied from Pirelli DP-L10 */
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/* Configure the memory interface */
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calypso_mem_cfg(CALYPSO_nCS0, 4, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS1, 4, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS3, 4, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_CS4, 7, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS1, 5, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS2, 4, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
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calypso_mem_cfg(CALYPSO_CS4, 5, CALYPSO_MEM_8bit, 1); /* TODO: add one dummy cycle */
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calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
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calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
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@ -0,0 +1,190 @@
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/* Framebuffer implementation for SE K200i/K220i -
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* combined driver for Core Logic CL761ST and S6B33B1X derivative */
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/* (C) 2022 by Steve Markgraf <steve@steve-m.de>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <fb/framebuffer.h>
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#include <fb/fb_rgb332.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <delay.h>
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#include <memory.h>
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#define K2X0_WIDTH 128
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#define K2X0_HEIGHT 128
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#define ARMIO_LATCH_OUT 0xfffe4802
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#define CS3_ADDR 0x02000000
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#define DISPLAY_CMD_ADDR (CS3_ADDR + 0)
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#define DISPLAY_DATA_ADDR (CS3_ADDR + 2)
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#define CL761_INDEX_ADDR (CS3_ADDR + 4)
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#define CL761_DATA_ADDR (CS3_ADDR + 6)
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#define CL761_CLK (1 << 4)
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#define CL761_RESET (1 << 9)
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#define K2X0_ENABLE_BACKLIGHT (1 << 3)
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static uint8_t fb_k2x0_mem[K2X0_WIDTH * K2X0_HEIGHT];
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static const uint8_t k2x0_initdata[] = {
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0x2c, /* CMD: Standby Mode off */
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0x02, /* CMD: Oscillation Mode Set */
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0x01, /* DATA: oscillator on */
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0x26, /* CMD: DCDC and AMP ON/OFF set */
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0x01, /* DATA: Booster 1 on */
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0x26, /* CMD: DCDC and AMP ON/OFF set */
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0x09, /* DATA: Booster 1 on, OP-AMP on */
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0x26, /* CMD: DCDC and AMP ON/OFF set */
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0x0b, /* DATA: Booster 1 + 2 on, OP-AMP on */
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0x26, /* CMD: DCDC and AMP ON/OFF set */
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0x0f, /* DATA: Booster 1 + 2 + 3 on, OP-AMP on */
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0x10, /* CMD: Driver output mode set */
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0x00, /* DATA: Display duty: 1/66 */
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0x20, /* CMD: DC-DC Select */
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0x01, /* DATA: step up x1.5 */
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0x24, /* CMD: DCDC Clock Division Set */
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0x08, /* DATA: fPCK = fOSC/32 */
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0x28, /* CMD: Temperature Compensation set */
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0x02, /* DATA: slope -0.10%/degC */
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0x2a, /* CMD: Contrast Control */
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0x1d, /* DATA: Constrast Level 29 */
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0x30, /* CMD: Addressing mode set */
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0x53, /* DATA: 256 color mode (orignal FW uses 0x13, 65k colors) */
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0x32, /* CMD: ROW vector mode set */
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0x0e, /* DATA: every subframe */
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0x34, /* CMD: N-block inversion set */
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0x8d, /* DATA: inversion on, every 1 block and every 2 frames */
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0x36, /* CMD: unknown */
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0x00, /* DATA: unknown */
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0x40, /* CMD: Entry mode set */
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0x80, /* DATA: Y address counter mode */
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0x45, /* CMD: RAM Skip Area Set */
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0x00, /* DATA: No Skip */
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0x53, /* CMD: Specified Display Pattern Set */
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0x00, /* DATA: Normal display */
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0x55, /* CMD: Partial Display Mode Set */
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0x00, /* DATA: Partial display OFF */
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0x51, /* CMD: Display on */
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};
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uint16_t cl761_read_reg(uint16_t reg)
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{
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writew(reg, CL761_INDEX_ADDR);
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return readw(CL761_INDEX_ADDR);
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}
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void cl761_write_reg(uint8_t reg, uint16_t data)
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{
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writew(reg, CL761_INDEX_ADDR);
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writew(data, CL761_DATA_ADDR);
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}
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static void fb_k2x0_init(void)
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{
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unsigned int i;
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uint16_t reg;
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printf("%s: initializing LCD.\n", __FUNCTION__);
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reg = readw(ARMIO_LATCH_OUT);
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reg &= ~(CL761_RESET | (1 << 1));
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reg |= CL761_CLK;
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writew(reg, ARMIO_LATCH_OUT);
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delay_ms(10);
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reg |= CL761_RESET;
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writew(reg, ARMIO_LATCH_OUT);
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/* we need to perform a dummy register read for the
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* CL761 to pass through the chip select to the display */
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cl761_read_reg(0x2e);
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delay_ms(1);
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reg &= ~CL761_CLK;
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reg |= (1 << 1) | K2X0_ENABLE_BACKLIGHT;
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writew(reg, ARMIO_LATCH_OUT);
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for (i = 0; i < sizeof(k2x0_initdata); i++)
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writew(k2x0_initdata[i], DISPLAY_CMD_ADDR);
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}
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static void fb_k2x0_flush(void)
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{
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unsigned int i;
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int x, y;
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uint8_t *p;
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uint8_t prepare_disp_write_cmds[] = {
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0x43, /* set column address */
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fb_rgb332->damage_x1,
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fb_rgb332->damage_x2 - 1,
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0x42, /* set page address (Y) */
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fb_rgb332->damage_y1,
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fb_rgb332->damage_y2 - 1,
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};
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/* If everything's clean, just return */
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if (fb_rgb332->damage_x1 == fb_rgb332->damage_x2 ||
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fb_rgb332->damage_y1 == fb_rgb332->damage_y2) {
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printf("%s: no damage\n", __FUNCTION__);
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return;
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}
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for (i = 0; i < sizeof(prepare_disp_write_cmds); i++)
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writew(prepare_disp_write_cmds[i], DISPLAY_CMD_ADDR);
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for (y = fb_rgb332->damage_y1; y < fb_rgb332->damage_y2; y++) {
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p = & fb_rgb332->mem[y * framebuffer->width]; // start of line
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p += fb_rgb332->damage_x1; // start of damage area
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for (x = fb_rgb332->damage_x1; x < fb_rgb332->damage_x2; x++) {
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/* For whatever reason, the 256 color mode of this
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* display uses 'RBG323' */
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uint8_t d = *p++;
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d = (d & 0xe0) | ((d & 0x1c) >> 2) | ((d & 0x03) << 3);
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/* We need to transfer the data twice in the 256 color mode.
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* Interestingly, the red and green information is taken
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* from the first byte written, and the blue information
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* from the second byte written. */
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writew(d, DISPLAY_DATA_ADDR);
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writew(d, DISPLAY_DATA_ADDR);
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}
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}
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fb_rgb332->damage_x1 = fb_rgb332->damage_x2 = 0;
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fb_rgb332->damage_y1 = fb_rgb332->damage_y2 = 0;
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}
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static struct framebuffer fb_k2x0_framebuffer = {
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.name = "k2x0",
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.init = fb_k2x0_init,
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.clear = fb_rgb332_clear,
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.boxto = fb_rgb332_boxto,
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.lineto = fb_rgb332_lineto,
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.putstr = fb_rgb332_putstr,
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.flush = fb_k2x0_flush,
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.width = K2X0_WIDTH,
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.height = K2X0_HEIGHT
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};
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static struct fb_rgb332 fb_k2x0_rgb332 = {
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.mem = fb_k2x0_mem
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};
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struct framebuffer *framebuffer = &fb_k2x0_framebuffer;
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struct fb_rgb332 *fb_rgb332 = &fb_k2x0_rgb332;
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