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UART initialisation, serial port errors 

Additional initialisations for the UART to make the data corruption
from the PC to the Phone go away.

I've seen a lot of systematic character swaps on the serial port,
especially in the vincinity of 0-bytes. As the XON/XOFF registers
are the only thing in the UART that look like they would consider
the actual data sent, I've added this initialisation to uart.c
This makes the problem go away completely on my C123.

To check for it I've added CRCs to the HDLC protocol and checked
for bad frames, and also compared them in a (patched) osmocon
that just sends random garbate in a special DLCI. The bad
frames I observed always looked like this (number in
parenthesis define number of omitted bytes, for brevity):

<------ good bytes ---------->  <-recvd|sent->  <----- identical again
------>

d0 e0 00 00..(107)..f7 ce 17 c4 < 0c 00|00 0c > db 70 ba cb..(67)..d8 6d 3a 1f
31 e1 00 00..(47)..38 ca 2f e5 < 0c 00|00 0c > f8 a3 77 5f..(127)..5b 72 ff 4a

<-- good -> <--- bad -----> <---- good again ------------->
dc e1 00 00 < 0c 00|00 0c > 87 cb 24 83..(178)..2f 69 b3 51

ae e2 00 00..(167)..bd 18 6f a1 < 0c 00|00 0c > 2f 53 d2 b2..(7)..da c7 1b 63
dc e3 00 00..(131)..8e 2c b0 a8 < 0c 00|00 0c > 40 62 56 5f..(43)..f0 3a 47 f7

Formerly I was observing about 10 packets for every 2000 sent (with 192
bytes of payload each). Now, with the added initialisation, I see
(as the time of writing this email) 12000 packets with 192 bytes each
sent, with 0 bytes missing, corrupted, flipped).
This commit is contained in:
Christian Vogel 2010-04-12 12:29:00 +02:00 committed by Harald Welte
parent 93b04a5d32
commit 9b7dbede26
1 changed files with 10 additions and 0 deletions
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10
src/target/firmware/calypso/uart.c
View File

@ -303,6 +303,16 @@ void uart_init(uint8_t uart, uint8_t interrupts)
writeb(UART_REG_UIR, 0x00);
}
#endif
/* if we don't initialize these, we get strange corruptions in the
received data... :-( */
uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */