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target_dsp/calypso: Dump I/Q samples and demodulated burst via MCSI 

Extend the DSP sniff task patch with MCSI (Multi-Channel
Serial Interface) support and dump the I/Q samples and the
demodulated burst over this interface.

Signed-off-by: Steve Markgraf <steve@steve-m.de>
This commit is contained in:
Steve Markgraf 2011-09-08 17:34:58 +02:00
parent 44649961dd
commit 711eec8b4f
2 changed files with 170 additions and 5 deletions
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30
src/target/firmware/calypso/dsp_sniffcode.c
View File

@ -5,7 +5,7 @@
static const struct dsp_section dsp_sniffcode[] = {
{
.addr = 0x015c,
.size = 0x0051,
.size = 0x00a1,
.data = _SA_DECL {
0x76f8, 0x3f6b, 0x0160, 0xfc00,
0x76f8, 0x439e, 0x0164, 0xfc00,
@ -17,15 +17,35 @@ static const struct dsp_section dsp_sniffcode[] = {
0x7211, 0x2114, 0xf495, 0xf495,
0x1281, 0xf845, 0x018a, 0xf010,
0x0001, 0x8081, 0xf074, 0xb74c,
0xf020, 0x018b, 0xf074, 0xaa9f,
0xf073, 0x0178, 0xfc00, 0xe834,
0xf020, 0x01c3, 0xf074, 0xaa9f,
0xf073, 0x0178, 0xfc00, 0x7681,
0x0010, 0x7581, 0x0806, 0xfc00,
0x7711, 0x2116, 0x7681, 0x0002,
0x7581, 0x0805, 0x7681, 0x004f,
0x7581, 0x0801, 0x7681, 0x0001,
0x7581, 0x0800, 0xf074, 0x018b,
0xfc00, 0x7711, 0x2116, 0xf074,
0x018b, 0x7594, 0x0820, 0x7481,
0x0806, 0x6181, 0x0010, 0xf820,
0x01a7, 0xfc00, 0x1282, 0xf074,
0x01a1, 0xf010, 0x0001, 0xf844,
0x01af, 0xfc00, 0x7711, 0x2116,
0x7481, 0x0806, 0x6181, 0x0020,
0xf820, 0x01b8, 0x7681, 0x0002,
0x7581, 0x0800, 0xfc00, 0x7714,
0x0cce, 0xf074, 0x0190, 0x7712,
0x2117, 0x7782, 0x017c, 0xf074,
0x01ae, 0xf074, 0x01b6, 0xe834,
0xf074, 0xa9ea, 0x7213, 0x2115,
0xf495, 0xf495, 0x7093, 0x3fa4,
0x7093, 0x3fa5, 0x7093, 0x3fa7,
0x7093, 0x3fa6, 0x7093, 0x0cce,
0x7712, 0x0ccf, 0x7711, 0x001c,
0x47f8, 0x0011, 0xe589, 0x7313,
0x2115, 0x7211, 0x2114, 0xf495,
0x47f8, 0x0011, 0xe589, 0x7214,
0x2115, 0x7313, 0x2115, 0xf074,
0x0190, 0x7712, 0x2117, 0x7782,
0x0022, 0xf074, 0x01ae, 0xf074,
0x01b6, 0x7211, 0x2114, 0xf495,
0xf495, 0x6be1, 0x0001, 0x0001,
0xfc00,
},

145
src/target_dsp/calypso/dsp_sniff.S
View File

@ -2,6 +2,7 @@
;
; (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
; (C) 2011 by Steve Markgraf <steve@steve-m.de>
;
; All Rights Reserved
;
@ -39,6 +40,20 @@ fq_4320_push .equ 0xAA9F
fq_4330_push .equ 0xAA6C
fq_4340_push .equ 0xAAC3
; ----------------------------------------------------------------------------
; MCSI (Multi-Channel Serial Interface)
; ----------------------------------------------------------------------------
; MCSI registers
MCSI_CONTROL_REG .equ 0x800
MCSI_MAIN_PARAM_REG .equ 0x801
MCSI_CLOCK_REG .equ 0x805
MCSI_STATUS_REG .equ 0x806
MCSI_TX0_REG .equ 0x820
; MCSI STATUS_REG bits
MCSI_TX_READY .equ 0x10
MCSI_TX_UNFLOW .equ 0x20
; ----------------------------------------------------------------------------
; Our double buffer API
@ -51,6 +66,9 @@ sniff_db1 .ds 138
sniff_db_ptr .ds 1
sniff_burst_ptr .ds 1
; Variables for MCSI
mcsi_tmp .ds 1
mcsi_cnt .ds 1
; ----------------------------------------------------------------------------
; The code itself
@ -132,6 +150,105 @@ sniff_task:
; Done
ret
;
; MCSI clear status
;
; Clears the MCSI status register, needs AR1 to be set to point to a temp word
;
mcsi_clear_status:
; The MCSI_TX_READY bit is cleared with a 1
st #MCSI_TX_READY, *AR1
portw *AR1, MCSI_STATUS_REG
ret
;
; MCSI initialisation
;
; Initializes and enables the MCSI
;
mcsi_init:
stm #mcsi_tmp, AR1
; Use a clock divider of 2 -> 13MHz/2 = 6.5MHz
st #2, *AR1
portw *AR1, MCSI_CLOCK_REG
; Set MCSI parameters: 16 bit framesize, master mode
st #0x4F, *AR1
portw *AR1, MCSI_MAIN_PARAM_REG
; Enable MCSI clock
st #1, *AR1
portw *AR1, MCSI_CONTROL_REG
call mcsi_clear_status
; Done
ret
;
; MCSI send word
;
; Sends a word of 16 bits over the MCSI and increases the source address
; Parameter: the address of the word has to be stored in AR4
;
mcsi_send_word:
stm #mcsi_tmp, AR1
call mcsi_clear_status
; Write TX word and increase address
portw *AR4+, MCSI_TX0_REG
; Loop until TX_READY bit of MCSI_STATUS_REG
; has been set (happens around the 4th transmitted bit)
1:
portr MCSI_STATUS_REG, *AR1
bitf *AR1, #MCSI_TX_READY
bc 1b, ntc
; Done
ret
;
; MCSI send burst
;
; Sends a burst of *AR2 words, beginning at the address of AR4
; Parameters: the number of words to send at *AR2, start-address in AR4
;
mcsi_send_burst:
; Load word-count in A
ldu *AR2, A
; Loop over all words
1:
call mcsi_send_word
sub #1, A
bc 1b, aneq
; Done
ret
;
; MCSI disable
;
; waits until the last word has been sent and disables the MCSI
;
mcsi_disable:
stm #mcsi_tmp, AR1
1: ; Loop until TX_UNFLOW bit of MCSI_STATUS_REG
; has been set (can only be reset with SW_RESET)
portr MCSI_STATUS_REG, *AR1
bitf *AR1, #MCSI_TX_UNFLOW
bc 1b, ntc
; disable MCSI clock and set SW_RESET
st #2, *AR1
portw *AR1, MCSI_CONTROL_REG
; Done
ret
;
; Burst data handler
;
@ -140,6 +257,20 @@ sniff_task:
; done for us. Only real work goes here.
;
burst_handler:
; Store address of I/Q data
stm #0x0CCE, AR4
; Initialize MCSI
call mcsi_init
; Send the I/Q data over MCSI
stm #mcsi_cnt, AR2
stm #380, *AR2 ; 190 samples, 380 words
call mcsi_send_burst
; Disable MCSI
call mcsi_disable
; NB demodulation
ld #0x34, A
call jt4387_exec
@ -162,9 +293,23 @@ burst_handler:
rpt *(AR1)
mvdd *AR2+, *AR3+
; Backup the old burst begin address
mvdm @sniff_burst_ptr, AR4
; Store the new pointer
mvmd AR3, @sniff_burst_ptr
; Initialize MCSI
call mcsi_init
; Send the demodulated burst data over MCSI
stm #mcsi_cnt, AR2
stm #34, *AR2 ; 5 + 29 words
call mcsi_send_burst
; Disable MCSI
call mcsi_disable
; Increment received bursts count
mvdm @sniff_db_ptr, AR1
nop ; (pipeline conflict)