fw: use proper delay routines, adapt all delays
Because the Pirelli DP-L10 display initialization has very strict timing requirements, implement compiler version agnostic delay functions using inline assembly. As it turned out, our delay routines always were way off: delay_ms(1000) with GCC 4.8.2 was actually 400ms, and with GCC 11.2.0 480ms were measured, the latter resulting in the DP-L10 display not working anymore. As the new routines now actually wait the time they should, scale all existing delay times by 0.4 to get the same behavior as previously with the old GCC version.steve-m/trx_rebased
parent
c731c86b9b
commit
6c6c880a66
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@ -178,7 +178,7 @@ uint16_t twl3025_reg_read(uint8_t reg)
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/* A read cycle contains two SPI transfers */
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spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx);
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delay_ms(1);
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delay_us(400);
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spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx);
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rx >>= 6;
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@ -192,7 +192,7 @@ uint16_t twl3025_reg_read(uint8_t reg)
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static void twl3025_wait_ibic_access(void)
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{
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/* Wait 6 * 32kHz clock cycles for first IBIC access (187us + 10% = 210us) */
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delay_ms(1);
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delay_us(400);
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}
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int twl3025_get_pwon(void)
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@ -69,7 +69,7 @@ static void flush_uart(void)
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unsigned i;
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for (i = 0; i < 500; i++) {
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uart_poll(sercomm_uart);
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delay_ms(1);
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delay_us(400);
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}
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}
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@ -63,7 +63,7 @@ static void flush_uart(void)
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unsigned i;
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for (i = 0; i < 500; i++) {
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uart_poll(sercomm_uart);
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delay_ms(1);
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delay_us(400);
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}
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}
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@ -83,7 +83,7 @@ static void device_reset(void)
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static void device_enter_loader(__unused unsigned char bootrom)
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{
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flush_uart();
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delay_ms(2000);
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delay_ms(800);
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void (*entry)( void ) = (void (*)(void))0;
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entry();
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}
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@ -108,7 +108,7 @@ static void wait_key_release(void)
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{
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/* wait for key release */
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while (key_state == PRESSED) {
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delay_ms(10);
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delay_ms(4);
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keypad_poll();
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}
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}
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@ -323,7 +323,7 @@ int main(void)
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while (1) {
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for (i = 0; i < 50; i++) {
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keypad_poll();
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delay_ms(10);
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delay_ms(4);
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osmo_timers_update();
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handle_key_code();
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}
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@ -285,7 +285,7 @@ void do_sim_test(void)
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printf(" Result: ");
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myHexdump(buffer,12);
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delay_ms(5000);
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delay_ms(2000);
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calypso_sim_powerdown();
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@ -409,8 +409,8 @@ int main(void)
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osmo_timers_update();
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intro();
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delay_ms(5000);
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fb_clear_fancy(20);
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delay_ms(2000);
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fb_clear_fancy(8);
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fb_setfg(FB_COLOR_BLACK);
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fb_setbg(FB_COLOR_WHITE);
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@ -49,7 +49,7 @@ void pll_init(void)
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writew(PLL_RST, MTK_PLL_PLL);
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writew(0, MTK_PLL_PLL);
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delay_ms(1);
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delay_us(400);
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/* Turn on PLL for MCU, DSP and USB */
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writew(PLL_MPLLSEL_PLL | PLL_DPLLSEL | PLL_UPLLSEL, MTK_PLL_PLL);
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@ -87,9 +87,9 @@ void memory_init(void)
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for (i = 0; i < 5; ++i) {
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/* Setup five single bits, one by one for DRAM init */
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writel((1 << (24 + i)) | (0x400013), MTK_EMI_CONN);
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delay_ms(1);
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delay_us(400);
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writel(0x400013, MTK_EMI_CONN);
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delay_ms(1);
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delay_us(400);
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}
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#if 0
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@ -109,9 +109,9 @@ void memory_init(void)
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for (i = 0; i < 5; ++i) {
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/* Setup five single bits, one by one for DRAM init */
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writel((1 << (24 + i)) | (0x500013), MTK_EMI_CONN);
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delay_ms(1);
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delay_us(400);
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writel(0x500013, MTK_EMI_CONN);
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delay_ms(1);
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delay_us(400);
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}
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#endif
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@ -186,13 +186,13 @@ static void dsp_pre_boot(const struct dsp_section *bootcode)
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writew(BL_STATUS_NA, BL_CMD_STATUS);
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} else
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delay_ms(10);
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delay_ms(4);
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dputs("Releasing DSP from Reset\n");
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calypso_reset_set(RESET_DSP, 0);
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/* Wait 10 us */
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delay_ms(100);
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delay_ms(40);
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dsp_bl_wait_ready();
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}
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@ -650,7 +650,7 @@ static void _dsp_dump_range(uint32_t addr, uint32_t size, int mode)
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while (bs--) {
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/* FIXME workaround: small delay to prevent overflowing
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* the sercomm buffer */
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delay_ms(2);
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delay_us(800);
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if ((addr&15)==0)
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printf("%05lx : ", addr);
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printf("%04hx%c", *api++, ((addr&15)==15)?'\n':' ');
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@ -86,7 +86,7 @@ void calypso_sim_regdump(void)
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#ifdef DEBUG
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unsigned int regVal;
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#define SIM_DEBUG_OUTPUTDELAY 200
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#define SIM_DEBUG_OUTPUTDELAY 80
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puts("\n\n\n");
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puts("====================== CALYPSO SIM REGISTER DUMP =====================\n");
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@ -121,7 +121,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
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break;
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}
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/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
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delay_ms(1);
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delay_us(400);
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if (din) {
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tmp = readw(SPI_REG(REG_RX_MSB)) << 16;
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@ -291,7 +291,7 @@ void tpu_wait_idle(void)
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{
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dputs("Waiting for TPU Idle ");
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/* Wait until TPU is doing something */
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delay_us(3);
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delay_us(1);
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/* Wait until TPU is idle */
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while (readw(TPU_REG(TPU_CTRL)) & TPU_CTRL_IDLE)
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dputchar('.');
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@ -99,7 +99,7 @@ static void fb_s6b33b1x_send_cmdlist(const struct s6b33b1x_cmdlist *p)
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static void fb_spca_write(uint16_t addr, uint16_t val)
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{
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writew(addr, nCS4_ADDR);
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delay_ms(1);
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delay_us(100);
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writew(val , nCS4_ADDR | 2);
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}
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@ -109,15 +109,15 @@ static void fb_spca_init(void)
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/* Initialize Sunplus SPCA552E Media Controller for bypass mode */
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fb_spca_write(0x7e, 0x00); /* internal register access */
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delay_ms(10);
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delay_ms(4);
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fb_spca_write(0x7a, 0x00); /* keep CPU in reset state */
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delay_ms(10);
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delay_ms(4);
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fb_spca_write(0x7f, 0x00); /* select main page */
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delay_ms(5);
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delay_ms(2);
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fb_spca_write(0x72, 0x07); /* don't reshape timing, 16 bit mode */
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fb_spca_write(0x14, 0x03);
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fb_spca_write(0x7f, 0x00); /* select main page */
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delay_ms(5);
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delay_ms(2);
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fb_spca_write(0x06, 0xff);
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fb_spca_write(0x7f, 0x09);
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fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */
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@ -128,9 +128,9 @@ static void
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fb_ssd1783_init(void){
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printf("%s: initializing LCD.\n",__FUNCTION__);
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calypso_reset_set(RESET_EXT, 0);
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delay_ms(5);
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delay_ms(2);
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uwire_init();
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delay_ms(5);
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delay_ms(2);
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fb_ssd1783_send_cmdlist(ssd1783_initdata);
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}
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@ -126,9 +126,9 @@ static void
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fb_ssd1963_init(void){
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printf("%s: initializing LCD.\n",__FUNCTION__);
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calypso_reset_set(RESET_EXT, 0);
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delay_ms(5);
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delay_ms(2);
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uwire_init();
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delay_ms(5);
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delay_ms(2);
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fb_ssd1963_send_cmdlist(ssd1963_initdata);
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}
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@ -73,9 +73,9 @@ static void
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fb_td014_init(void) {
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printf("%s: initializing LCD.\n",__FUNCTION__);
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calypso_reset_set(RESET_EXT, 0);
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delay_ms(5);
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delay_ms(2);
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uwire_init();
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delay_ms(5);
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delay_ms(2);
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fb_td014_send_cmdlist(td014_initdata);
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}
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@ -147,7 +147,7 @@
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/* 1 = SIM card insertion/extraction */
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#define SIM_OPERATION_DELAY 100 /* Time between operations like reset, vcc apply ect... */
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#define SIM_OPERATION_DELAY 40 /* Time between operations like reset, vcc apply etc... */
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void calypso_sim_regdump(void); /* Display Register dump */
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@ -1,16 +1,41 @@
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#include <delay.h>
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/* FIXME: We need properly calibrated delay loops at some point! */
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#define CALYPSO_CLK 52000000
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#define CYCLES_PER_LOOP 4
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#define COUNTS_PER_MS (CALYPSO_CLK / CYCLES_PER_LOOP) / 1000
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#define COUNTS_PER_US COUNTS_PER_MS/1000
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void delay_us(unsigned int us)
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{
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volatile unsigned int i;
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unsigned int counts = COUNTS_PER_US * us;
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for (i= 0; i < us*4; i++) { i; }
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asm volatile
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(
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"mov r3, %[counts]\n\t"
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"usloop:\n\t"
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"subs r3, #1\n\t"
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"bne usloop\n\t"
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: /* we have no output, list empty */
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: [counts] "r" (counts)
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/* r3 and flags are clobbered */
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: "r3", "cc"
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);
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}
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void delay_ms(unsigned int ms)
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{
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volatile unsigned int i;
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for (i= 0; i < ms*1300; i++) { i; }
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unsigned int counts = COUNTS_PER_MS;
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while (ms--) {
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asm volatile
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(
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"mov r3, %[counts]\n\t"
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"msloop:\n\t"
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"subs r3, #1\n\t"
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"bne msloop\n\t"
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: /* we have no output, list empty */
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: [counts] "r" (counts)
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/* r3 and flags are clobbered */
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: "r3", "cc"
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);
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}
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}
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