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target/fw/l1: Fix TCH/H by properly scheduling the TCHD task during 'off' slots 

Apparently the DSP needs to be run even during the slots without
actual bursts exchange.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2010-10-30 21:13:41 +02:00
parent 2ac17ed9fa
commit 375f41a9dd
3 changed files with 63 additions and 0 deletions
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1
src/target/firmware/include/layer1/prim.h
View File

@ -28,5 +28,6 @@ extern const struct tdma_sched_item nb_sched_set_ul[];
extern const struct tdma_sched_item tch_sched_set[];
extern const struct tdma_sched_item tch_a_sched_set[];
extern const struct tdma_sched_item tch_d_sched_set[];
#endif /* _L1_PRIM_H */

13
src/target/firmware/layer1/mframe_sched.c
View File

@ -200,6 +200,7 @@ static const struct mframe_sched_item mf_sdcch8_7[] = {
/* TCH */
#define TCH tch_sched_set
#define TCH_A tch_a_sched_set
#define TCH_D tch_d_sched_set
static const struct mframe_sched_item mf_tch_f_even[] = {
{ .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
@ -237,21 +238,33 @@ static const struct mframe_sched_item mf_tch_f_odd[] = {
static const struct mframe_sched_item mf_tch_h_0[] = {
{ .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 1 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 2 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 3 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 4 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 5 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 6 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 7 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 8 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 9 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 10 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 11 },
{ .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
{ .sched_set = NULL }
};
static const struct mframe_sched_item mf_tch_h_1[] = {
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 0 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 1 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 2 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 3 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 4 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 5 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 6 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 7 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 8 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 9 },
{ .sched_set = TCH_D, .modulo = 13, .frame_nr = 10 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 11 },
{ .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
{ .sched_set = NULL }

49
src/target/firmware/layer1/prim_tch.c
View File

@ -393,6 +393,55 @@ const struct tdma_sched_item tch_sched_set[] = {
};
/* -------------------------------------------------------------------------
* TCH/H: Dummy
* ------------------------------------------------------------------------- */
/* This task is needed to perform some operation in the DSP when there is
* no data to be exchanged */
static int l1s_tch_d_resp(__unused uint8_t p1, __unused uint8_t p2, uint16_t p3)
{
/* mark READ page as being used */
dsp_api.r_page_used = 1;
return 0;
}
static int l1s_tch_d_cmd(__unused uint8_t p1, __unused uint8_t p2, uint16_t p3)
{
uint8_t mf_task_id = p3 & 0xff;
uint8_t chan_nr;
uint8_t tsc, tn;
uint8_t tch_f_hn, tch_sub, tch_mode;
uint32_t fn_report;
/* Get/compute various parameters */
rfch_get_params(&l1s.next_time, NULL, &tsc, &tn);
chan_nr = mframe_task2chan_nr(mf_task_id, tn);
tch_get_params(&l1s.next_time, chan_nr, &fn_report, &tch_f_hn, &tch_sub, &tch_mode);
/* Configure DSP */
dsp_load_tch_param(
&l1s.next_time,
tch_mode, tch_f_hn ? TCH_F : TCH_H, tch_sub,
0, 0, tn
);
dsp_load_rx_task(TCHD_DSP_TASK, 0, tsc); /* burst_id unused for TCH */
dsp_load_tx_task(TCHD_DSP_TASK, 0, tsc); /* burst_id unused for TCH */
return 0;
}
const struct tdma_sched_item tch_d_sched_set[] = {
SCHED_ITEM_DT(l1s_tch_d_cmd, 0, 0, 0), SCHED_END_FRAME(),
SCHED_END_FRAME(),
SCHED_ITEM(l1s_tch_d_resp, 0, 0, -4), SCHED_END_FRAME(),
SCHED_END_SET()
};
/* -------------------------------------------------------------------------
* TCH: SACCH
* ------------------------------------------------------------------------- */