186 lines
6.4 KiB
C
186 lines
6.4 KiB
C
/****************************************************************************
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* configs/vsn/src/sysclock.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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*
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/** \file
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*/
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#include <arch/board/board.h>
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#include "stm32_rcc.h"
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#include "stm32_gpio.h"
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#include "stm32_flash.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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/*--- Private ---*/
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/** Selects internal HSI Clock, SYSCLK = 36 MHz, HCLK = 36 MHz
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* - HSI at 8 MHz, :2 enters DPLL * 9, to get 36 MHz
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* - AHB prescaler is set to 1 for maximum performance of all peripherals and FRAM (18 Mbps)
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* - Suitable for start-up and lower power operation
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* - Flash Wait State = 1, since it is 64-bit prefetch, it satisfies two 32-bit instructions
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* (and branch losses a single cycle only, I found this as the best performance vs. frequency)
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* - Sleep with peripherals disabled is about 2.5 mA @ 36 MHz, HSI
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*
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* \todo:
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* - dynamic clock scalling according to cross-peripheral requirements, AHB prescaler could
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* change if all other prescalers increase, to maintain the ratio and to have min. HCLK
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* possible; This is of interest when peripherals consume 50% of all power, as for instance
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* in sleep mode @ 36 MHz, HSI with all peripherals enabled, i = 7 mA, on 24 Mhz 4.8 mA and
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* on 16 MHz 3.2 mA only.
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*
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* \return Nothing, operation is always successful.
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*/
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void stm32_board_select_hsi(void)
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{
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uint32_t regval;
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// Are we running on HSE?
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regval = getreg32(STM32_RCC_CR);
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if (regval & RCC_CR_HSEON) {
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// \todo: check is if we are running on HSE, we need the step down sequenuce from HSE -> HSI
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return; // do nothing at this time
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}
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// Set FLASH prefetch buffer and 1 wait state
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~ACR_LATENCY_MASK;
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regval |= (ACR_LATENCY_1|ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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// Set the HCLK source/divider
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE_HSI;
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putreg32(regval, STM32_RCC_CFGR);
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// Set the PCLK2 divider
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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// Set the PCLK1 divider
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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// Set the PLL source = HSI, divider (/2) and multipler (*9)
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
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regval |= (STM32_CFGR_PLLSRC_HSI|STM32_CFGR_PLLMUL_HSI);
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putreg32(regval, STM32_RCC_CFGR);
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// Enable the PLL
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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// Wait until the PLL is ready
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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// Select the system clock source (probably the PLL)
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= STM32_SYSCLK_SW;
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putreg32(regval, STM32_RCC_CFGR);
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// Wait until the selected source is used as the system clock source
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
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// map port PD0 and PD1 on OSC pins
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regval = getreg32(STM32_AFIO_MAPR);
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regval |= AFIO_MAPR_PD01_REMAP;
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putreg32(regval, STM32_AFIO_MAPR);
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}
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/** Selects external HSE Clock, SYSCLK = 72 MHz, HCLK = 36/72 MHz
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* - HSE at 9 MHz, DPLL * 8, to get 72 MHz
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* - Suitable for maximum performance and USB
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* - Sleep power consumption at HSE and at 72 MHz is 5.5 mA (3.1 @ 36 MHz)
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* - Option AHB prescaler is set to :2 to be compatible with HSI to remain on HCLK = 36 MHz
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* - Flash memory running on 72 MHz needs two wait states
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*
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* \return Clock selection status
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* \retval 0 Successful
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* \retval -1 External clock is not provided
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* \retval -2 Could not lock to external clock
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*/
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int stm32_board_select_hse(void)
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{
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uint32_t regval;
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// be sure to release PD0 and PD1 pins from the OSC pins
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regval = getreg32(STM32_AFIO_MAPR);
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regval &= ~AFIO_MAPR_PD01_REMAP;
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putreg32(regval, STM32_AFIO_MAPR);
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// if (is cc1101 9 MHz clock output enabled), otherwise return with -1
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// I think that clock register provides HSE valid signal to detect that as well.
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return 0;
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}
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/*--- Interrupts ---*/
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/** TODO: Interrupt on lost HSE clock, change it to HSI, ... restarting is
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* more complex as the step requires restart of CC1101 device driver;
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* so spawn a task for that... once cc1101 is restarted signal an event
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* to restart clock.
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*/
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void stm32_board_hse_lost(void)
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{
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}
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/*--- Public API ---*/
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/** Setup system clock, enabled when:
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* - CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
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* option is set in .config
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*/
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void stm32_board_clockconfig(void)
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{
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stm32_board_select_hsi();
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}
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