259 lines
15 KiB
C
259 lines
15 KiB
C
/************************************************************************************
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* arch/arm/src/imx/imx_memorymap.h
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_IMX_MEMORYMAP_H
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#define __ARCH_ARM_IMX_MEMORYMAP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "arm.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Physical Memory Map **************************************************************/
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/* -0x000fffff Double Map Image 1Mb */
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/* -0x001fffff Bootstrap ROM 1Mb */
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#define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */
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#define IMX_ESRAM_PSECTION 0x00300000 /* -0x003fffff Embedded SRAM 128Kb */
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#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x0bffffff SDRAM0 (CSD0) 64Mb */
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#define IMX_SDRAM1_PSECTION 0x0c000000 /* -0x0fffffff SDRAM1 (CSD1) 64Mb */
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#define IMX_FLASH_PSECTION 0x10000000 /* -0x11ffffff FLASH (CS0) 32Mb */
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#define IMX_CS1_PSECTION 0x12000000 /* -0x12ffffff CS1 16Mb */
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#define IMX_CS2_PSECTION 0x13000000 /* -0x13ffffff CS2 16Mb */
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#define IMX_CS3_PSECTION 0x14000000 /* -0x14ffffff CS3 16Mb */
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#define IMX_CS4_PSECTION 0x15000000 /* -0x15ffffff CS4 16Mb */
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#define IMX_CS5_PSECTION 0x16000000 /* -0x16ffffff CS5 16Mb */
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/* Sizes of Address Sections ********************************************************/
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/* Mapped sections */
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#define IMX_PERIPHERALS_NSECTIONS 1 /* 1Mb 1 section */
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#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_DRAM_SIZE */
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#define IMX_SDRAM1_NSECTIONS 0 /* 64Mb (Not mapped) */
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#define IMX_FLASH_NSECTIONS 32 /* 64Mb Based on CONFIG_FLASH_SIZE */
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#define IMX_CS1_NSECTIONS 16 /* 16Mb */
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#define IMX_CS2_NSECTIONS 16 /* 16Mb */
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#define IMX_CS3_NSECTIONS 16 /* 16Mb */
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#define IMX_CS4_NSECTIONS 16 /* 16Mb */
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#define IMX_CS5_NSECTIONS 16 /* 16Mb */
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/* Virtual Memory Map ***************************************************************/
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/* There are three operational memory configurations:
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*
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* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case:
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*
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* - Our vectors must be located at the beginning of FLASH and will
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* also be mapped to address zero (because of the i.MX's "double map image."
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* - All vector addresses are FLASH absolute addresses,
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* - DRAM cannot reside at address zero,
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* - Vectors at address zero (CR_V is not set),
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* - The boot logic must configure SDRAM and,
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* - The .data section in RAM must be initialized.
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*
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* 2. We boot in FLASH but copy ourselves to DRAM from better performance.
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* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case:
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*
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* - Our code image is in FLASH and we boot to FLASH initially, then copy
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* ourself to DRAM,
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* - DRAM will be mapped to address zero,
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* - The RESET vector is a FLASH absolute address,
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* - All other vectors are absulte and reference functions in the final mapped SDRAM address
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* - Vectors at address zero (CR_V is not set), and
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* - The boot logic must configure SDRAM.
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*
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* 3. There is bootloader that copies us to DRAM, but probably not to the beginning
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* of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
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* In this case:
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*
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* - DRAM will be mapped to address zero,
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* - Interrupt vectors will be copied to address zero,
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* - Memory between the end of the vector area (say 0x0800:0400) and the beginning
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* of the page table (0x0900:0000) will be given to the memory manager as a second
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* memory region,
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* - All vectors are absulte and reference functions in the final mapped SDRAM address
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* - Vectors at address zero (CR_V is not set), and
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* - We must assume that the bootloader has configured SDRAM.
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*/
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* Use the identity mapping */
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# define IMX_SDRAM_VSECTION 0x08000000 /* -(+CONFIG_DRAM_SIZE) */
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#else
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/* Map SDRAM to address zero */
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# define IMX_SDRAM_VSECTION 0x00000000 /* -(+CONFIG_DRAM_SIZE) */
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#endif
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/* We use a identity mapping for other regions */
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#define IMX_PERIPHERALS_VSECTION 0x00200000 /* -0x002fffff 1Mb */
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#define IMX_FLASH_VSECTION 0x10000000 /* -(+CONFIG_FLASH_SIZE) */
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#define IMX_CS1_VSECTION 0x12000000 /* -0x12ffffff CS1 32Mb */
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#define IMX_CS2_VSECTION 0x13000000 /* -0x13ffffff CS2 32Mb */
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#define IMX_CS3_VSECTION 0x14000000 /* -0x14ffffff CS3 32Mb */
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#define IMX_CS4_VSECTION 0x15000000 /* -0x15ffffff CS4 32Mb */
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#define IMX_CS5_VSECTION 0x16000000 /* -0x16ffffff CS5 32Mb */
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/* In any event, the vector base address is 0x0000:0000 */
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#define VECTOR_BASE 0x00000000
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/* Peripheral Register Offsets ******************************************************/
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#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */
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#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */
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#define IMX_TIMER1_OFFSET 0x00002000 /* -0x00002fff Timer1 4Kb */
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#define IMX_TIMER2_OFFSET 0x00003000 /* -0x00003fff Timer2 4Kb */
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#define IMX_RTC_OFFSET 0x00004000 /* -0x00004fff RTC 4Kb */
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#define IMX_LCDC_OFFSET 0x00005000 /* -0x00005fff LCD 4Kb */
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#define IMX_LCDC_COLORMAP 0x00005800
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#define IMX_UART1_OFFSET 0x00006000 /* -0x00006fff UART1 4Kb */
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#define IMX_UART2_OFFSET 0x00007000 /* -0x00007fff UART2 4Kb */
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#define IMX_PWM1_OFFSET 0x00008000 /* -0x00008fff PWM 4Kb */
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#define IMX_DMA_OFFSET 0x00009000 /* -0x00009fff DMA 4Kb */
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#define IMX_UART3_OFFSET 0x0000a000 /* -0x0000afff UART3 4Kb */
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/* -0x0000ffff Reserved 20Kb */
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#define IMX_AIPI2_OFFSET 0x00010000 /* -0x00010fff AIPI2 4Kb */
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#define IMX_SIM_OFFSET 0x00011000 /* -0x00011fff SIM 4Kb */
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#define IMX_USBD_OFFSET 0x00012000 /* -0x00012fff USBD 4Kb */
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#define IMX_CSPI1_OFFSET 0x00013000 /* -0x00013fff CSPI1 4Kb */
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#define IMX_MMC_OFFSET 0x00014000 /* -0x00014fff MMC 4Kb */
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#define IMX_ASP_OFFSET 0x00015000 /* -0x00015fff ASP 4Kb */
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#define IMX_BTA_OFFSET 0x00016000 /* -0x00016fff BTA 4Kb */
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#define IMX_I2C_OFFSET 0x00017000 /* -0x00017fff I2C 4Kb */
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#define IMX_SSI_OFFSET 0x00018000 /* -0x00018fff SSI 4Kb */
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#define IMX_CSPI2_OFFSET 0x00019000 /* -0x00019fff CSPI2 4Kb */
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#define IMX_MSHC_OFFSET 0x0001a000 /* -0x0001afff Memory Stick 4Kb */
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#define IMX_CRM_OFFSET 0x0001b000 /* -0x0001bfff CRM 4Kb */
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#define IMX_PLL_OFFSET 0x0001b000
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#define IMX_SC_OFFSET 0x0001b800
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#define IMX_GPIO_OFFSET 0x0001c000 /* -0x0001cfff GPIO 4Kb */
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/* -0x0001ffff Reserved 12Kb */
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#define IMX_EIM_OFFSET 0x00020000 /* -0x00020fff EIM 4Kb */
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#define IMX_SDRAMC_OFFSET 0x00021000 /* -0x00021fff SDRAMC 4Kb */
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#define IMX_DSPA_OFFSET 0x00022000 /* -0x00022fff DSPA 4Kb */
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#define IMX_AITC_OFFSET 0x00023000 /* -0x00023fff AITC 4Kb */
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#define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */
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/* -0x000fffff Reserved 876Kb */
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/* Peripheral Register Offsets ******************************************************/
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#define IMX_AIPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI1_OFFSET)
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#define IMX_WDOG_VBASE (IMX_PERIPHERALS_VSECTION + IMX_WDOG_OFFSET)
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#define IMX_TIMER1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_TIMER1_OFFSET)
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#define IMX_TIMER2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_TIMER2_OFFSET)
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#define IMX_RTC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_RTC_OFFSET)
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#define IMX_LCDC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_LCDC_OFFSET)
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#define IMX_LCDC_COLORMAP_VBASE (IMX_PERIPHERALS_VSECTION + IMX_LCDC_COLORMAP)
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#define IMX_UART1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART1_OFFSET)
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#define IMX_UART2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART2_OFFSET)
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#define IMX_PWM1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PWM1_OFFSET)
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#define IMX_DMA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_DMA_OFFSET)
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#define IMX_UART3_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART3_OFFSET)
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#define IMX_AIP2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI2_OFFSET)
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#define IMX_SIM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SIM_OFFSET)
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#define IMX_USBD_VBASE (IMX_PERIPHERALS_VSECTION + IMX_USBD_OFFSET)
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#define IMX_CSPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSPI1_OFFSET)
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#define IMX_MMC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_MMC_OFFSET)
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#define IMX_ASP_VBASE (IMX_PERIPHERALS_VSECTION + IMX_ASP_OFFSET)
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#define IMX_BTA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_BTA_OFFSET)
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#define IMX_I2C_VBASE (IMX_PERIPHERALS_VSECTION + IMX_I2C_OFFSET)
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#define IMX_SSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SSI_OFFSET)
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#define IMX_CSPI2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSPI2_OFFSET)
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#define IMX_MSHC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_MSHC_OFFSET)
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#define IMX_CRM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CRM_OFFSET)
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#define IMX_PLL_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PLL_OFFSET)
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#define IMX_SC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SC_OFFSET)
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#define IMX_GPIO_VBASE (IMX_PERIPHERALS_VSECTION + IMX_GPIO_OFFSET)
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#define IMX_EIM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_EIM_OFFSET)
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#define IMX_SDRAMC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SDRAMC_OFFSET)
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#define IMX_DSPA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_DSPA_OFFSET)
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#define IMX_AITC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AITC_OFFSET)
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#define IMX_CSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSI_OFFSET)
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/* Memory Mapping Info **************************************************************/
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/* The NuttX entry point starts at an offset from the virtual beginning of DRAM.
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* This offset reserves space for the MMU page cache.
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*/
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#define NUTTX_START_VADDR ((CONFIG_DRAM_NUTTXENTRY & 0xfff00000) | PGTABLE_SIZE)
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#if NUTTX_START_VADDR != CONFIG_DRAM_NUTTXENTRY
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# error "CONFIG_DRAM_NUTTXENTRY does not have correct offset for page table"
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#endif
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/* Section MMU Flags */
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#define IMX_FLASH_MMUFLAGS MMU_IOFLAGS
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#define IMX_PERIPHERALS_MMUFLAGS MMU_IOFLAGS
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/* 16Kb of memory is reserved at the beginning of SDRAM to hold the
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* page table for the virtual mappings. A portion of this table is
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* not accessible in the virtual address space (for normal operation).
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* We will reuse this memory for coarse page tables as follows:
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*/
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#define PGTABLE_BASE_PADDR IMX_SDRAM0_PSECTION
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#define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR
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#define PGTABLE_COARSE_PBASE (PGTABLE_BASE_PADDR+0x00000800)
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#define PGTABLE_COARSE_PEND (PGTABLE_BASE_PADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_BASE_PADDR+0x00003000)
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#define PGTABLE_PEND (PGTABLE_BASE_PADDR+0x00004000)
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#define PGTABLE_BASE_VADDR IMX_SDRAM_VSECTION
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#define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR
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#define PGTABLE_COARSE_VBASE (PGTABLE_BASE_VADDR+0x00000800)
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#define PGTABLE_COARSE_VEND (PGTABLE_BASE_VADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_BASE_VADDR+0x00003000)
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#define PGTABLE_VEND (PGTABLE_BASE_VADDR+0x00004000)
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#define PGTABLE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)
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#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_IMX_MEMORYMAP_H */
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