172 lines
9.0 KiB
C
172 lines
9.0 KiB
C
/************************************************************************************
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* arch/arm/src/lpc43xx/lpc43_ssp.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 8 frame FIFOs for both transmit and receive */
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#define LPC43_SSP_FIFOSZ 8
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/* Register offsets *****************************************************************/
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#define LPC43_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
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#define LPC43_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
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#define LPC43_SSP_DR_OFFSET 0x0008 /* Data Register */
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#define LPC43_SSP_SR_OFFSET 0x000c /* Status Register */
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#define LPC43_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
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#define LPC43_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */
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#define LPC43_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
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#define LPC43_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
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#define LPC43_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
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#define LPC43_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */
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/* Register addresses ***************************************************************/
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#define LPC43_SSP0_CR0 (LPC43_SSP0_BASE+LPC43_SSP_CR0_OFFSET)
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#define LPC43_SSP0_CR1 (LPC43_SSP0_BASE+LPC43_SSP_CR1_OFFSET)
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#define LPC43_SSP0_DR (LPC43_SSP0_BASE+LPC43_SSP_DR_OFFSET)
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#define LPC43_SSP0_SR (LPC43_SSP0_BASE+LPC43_SSP_SR_OFFSET)
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#define LPC43_SSP0_CPSR (LPC43_SSP0_BASE+LPC43_SSP_CPSR_OFFSET)
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#define LPC43_SSP0_IMSC (LPC43_SSP0_BASE+LPC43_SSP_IMSC_OFFSET)
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#define LPC43_SSP0_RIS (LPC43_SSP0_BASE+LPC43_SSP_RIS_OFFSET)
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#define LPC43_SSP0_MIS (LPC43_SSP0_BASE+LPC43_SSP_MIS_OFFSET)
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#define LPC43_SSP0_ICR (LPC43_SSP0_BASE+LPC43_SSP_ICR_OFFSET)
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#define LPC43_SSP0_DMACR (LPC43_SSP0_BASE+LPC43_SSP_DMACR_OFFSET)
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#define LPC43_SSP1_CR0 (LPC43_SSP1_BASE+LPC43_SSP_CR0_OFFSET)
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#define LPC43_SSP1_CR1 (LPC43_SSP1_BASE+LPC43_SSP_CR1_OFFSET)
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#define LPC43_SSP1_DR (LPC43_SSP1_BASE+LPC43_SSP_DR_OFFSET)
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#define LPC43_SSP1_SR (LPC43_SSP1_BASE+LPC43_SSP_SR_OFFSET)
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#define LPC43_SSP1_CPSR (LPC43_SSP1_BASE+LPC43_SSP_CPSR_OFFSET)
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#define LPC43_SSP1_IMSC (LPC43_SSP1_BASE+LPC43_SSP_IMSC_OFFSET)
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#define LPC43_SSP1_RIS (LPC43_SSP1_BASE+LPC43_SSP_RIS_OFFSET)
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#define LPC43_SSP1_MIS (LPC43_SSP1_BASE+LPC43_SSP_MIS_OFFSET)
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#define LPC43_SSP1_ICR (LPC43_SSP1_BASE+LPC43_SSP_ICR_OFFSET)
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#define LPC43_SSP1_DMACR (LPC43_SSP1_BASE+LPC43_SSP_DMACR_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Control Register 0 */
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#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */
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#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT)
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# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT)
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#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */
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#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
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# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT)
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# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT)
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# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT)
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#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */
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#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */
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#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */
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#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT)
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/* Bits 8-31: Reserved */
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/* Control Register 1 */
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#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
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#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */
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#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
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#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
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/* Bits 4-31: Reserved */
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/* Data Register */
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#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
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/* Bits 16-31: Reserved */
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/* Status Register */
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#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
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#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
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#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
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#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
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#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
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/* Bits 5-31: Reserved */
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/* Clock Prescale Register */
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#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */
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/* Bits 8-31: Reserved */
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/* Common format for interrupt control registers:
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*
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* Interrupt Mask Set and Clear Register (IMSC)
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* Raw Interrupt Status Register (RIS)
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* Masked Interrupt Status Register (MIS)
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* Interrupt Clear Register (ICR)
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*/
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#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */
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#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */
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#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */
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#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */
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/* Bits 4-31: Reserved */
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/* DMA Control Register */
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#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */
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#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
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/* Bits 2-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H */
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