517 lines
22 KiB
C
Executable File
517 lines
22 KiB
C
Executable File
/****************************************************************************
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* drivers/wireless/chipcon_cc1101.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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*
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* Authors: Uros Platise <uros.platise@isotel.eu>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/** \file
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* \author Uros Platise
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* \brief Chipcon CC1101 Device Driver
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*
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*
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**/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <stdio.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/wireless/chipcon_cc1101.h>
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#include <nuttx/ptimer.h>
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/************************************************************************************
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* Chipcon CC1101 Internal Registers
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************************************************************************************/
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/* Configuration Registers */
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#define CC1101_IOCFG2 0x00 /* GDO2 output pin configuration */
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#define CC1101_IOCFG1 0x01 /* GDO1 output pin configuration */
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#define CC1101_IOCFG0 0x02 /* GDO0 output pin configuration */
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#define CC1101_FIFOTHR 0x03 /* RX FIFO and TX FIFO thresholds */
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#define CC1101_SYNC1 0x04 /* Sync word, high byte */
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#define CC1101_SYNC0 0x05 /* Sync word, low byte */
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#define CC1101_PKTLEN 0x06 /* Packet length */
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#define CC1101_PKTCTRL1 0x07 /* Packet automation control */
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#define CC1101_PKTCTRL0 0x08 /* Packet automation control */
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#define CC1101_ADDR 0x09 /* Device address */
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#define CC1101_CHANNR 0x0A /* Channel number */
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#define CC1101_FSCTRL1 0x0B /* Frequency synthesizer control */
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#define CC1101_FSCTRL0 0x0C /* Frequency synthesizer control */
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#define CC1101_FREQ2 0x0D /* Frequency control word, high byte */
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#define CC1101_FREQ1 0x0E /* Frequency control word, middle byte */
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#define CC1101_FREQ0 0x0F /* Frequency control word, low byte */
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#define CC1101_MDMCFG4 0x10 /* Modem configuration */
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#define CC1101_MDMCFG3 0x11 /* Modem configuration */
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#define CC1101_MDMCFG2 0x12 /* Modem configuration */
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#define CC1101_MDMCFG1 0x13 /* Modem configuration */
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#define CC1101_MDMCFG0 0x14 /* Modem configuration */
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#define CC1101_DEVIATN 0x15 /* Modem deviation setting */
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#define CC1101_MCSM2 0x16 /* Main Radio Cntrl State Machine config */
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#define CC1101_MCSM1 0x17 /* Main Radio Cntrl State Machine config */
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#define CC1101_MCSM0 0x18 /* Main Radio Cntrl State Machine config */
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#define CC1101_FOCCFG 0x19 /* Frequency Offset Compensation config */
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#define CC1101_BSCFG 0x1A /* Bit Synchronization configuration */
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#define CC1101_AGCCTRL2 0x1B /* AGC control */
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#define CC1101_AGCCTRL1 0x1C /* AGC control */
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#define CC1101_AGCCTRL0 0x1D /* AGC control */
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#define CC1101_WOREVT1 0x1E /* High byte Event 0 timeout */
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#define CC1101_WOREVT0 0x1F /* Low byte Event 0 timeout */
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#define CC1101_WORCTRL 0x20 /* Wake On Radio control */
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#define CC1101_FREND1 0x21 /* Front end RX configuration */
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#define CC1101_FREND0 0x22 /* Front end TX configuration */
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#define CC1101_FSCAL3 0x23 /* Frequency synthesizer calibration */
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#define CC1101_FSCAL2 0x24 /* Frequency synthesizer calibration */
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#define CC1101_FSCAL1 0x25 /* Frequency synthesizer calibration */
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#define CC1101_FSCAL0 0x26 /* Frequency synthesizer calibration */
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#define CC1101_RCCTRL1 0x27 /* RC oscillator configuration */
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#define CC1101_RCCTRL0 0x28 /* RC oscillator configuration */
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#define CC1101_FSTEST 0x29 /* Frequency synthesizer cal control */
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#define CC1101_PTEST 0x2A /* Production test */
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#define CC1101_AGCTEST 0x2B /* AGC test */
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#define CC1101_TEST2 0x2C /* Various test settings */
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#define CC1101_TEST1 0x2D /* Various test settings */
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#define CC1101_TEST0 0x2E /* Various test settings */
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/* Status registers */
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#define CC1101_PARTNUM (0x30 | 0xc0) /* Part number */
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#define CC1101_VERSION (0x31 | 0xc0) /* Current version number */
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#define CC1101_FREQEST (0x32 | 0xc0) /* Frequency offset estimate */
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#define CC1101_LQI (0x33 | 0xc0) /* Demodulator estimate for link quality */
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#define CC1101_RSSI (0x34 | 0xc0) /* Received signal strength indication */
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#define CC1101_MARCSTATE (0x35 | 0xc0) /* Control state machine state */
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#define CC1101_WORTIME1 (0x36 | 0xc0) /* High byte of WOR timer */
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#define CC1101_WORTIME0 (0x37 | 0xc0) /* Low byte of WOR timer */
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#define CC1101_PKTSTATUS (0x38 | 0xc0) /* Current GDOx status and packet status */
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#define CC1101_VCO_VC_DAC (0x39 | 0xc0) /* Current setting from PLL cal module */
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#define CC1101_TXBYTES (0x3A | 0xc0) /* Underflow and # of bytes in TXFIFO */
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#define CC1101_RXBYTES (0x3B | 0xc0) /* Overflow and # of bytes in RXFIFO */
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#define CC1101_RCCTRL1_STATUS (0x3E | 0xc0) /* Last RC oscilator calibration results */
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#define CC1101_RCCTRL0_STATUS (0x3F | 0xc0) /* Last RC oscilator calibration results */
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/* Multi byte memory locations */
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#define CC1101_PATABLE 0x3E
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#define CC1101_TXFIFO 0x3F
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#define CC1101_RXFIFO 0x3F
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/* Definitions for burst/single access to registers */
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#define CC1101_WRITE_BURST 0x40
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#define CC1101_READ_SINGLE 0x80
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#define CC1101_READ_BURST 0xC0
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/* Strobe commands */
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#define CC1101_SRES 0x30 /* Reset chip. */
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#define CC1101_SFSTXON 0x31 /* Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). */
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#define CC1101_SXOFF 0x32 /* Turn off crystal oscillator. */
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#define CC1101_SCAL 0x33 /* Calibrate frequency synthesizer and turn it off */
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#define CC1101_SRX 0x34 /* Enable RX. Perform calibration first if switching from IDLE and MCSM0.FS_AUTOCAL=1. */
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#define CC1101_STX 0x35 /* Enable TX. Perform calibration first if IDLE and MCSM0.FS_AUTOCAL=1. */
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/* If switching from RX state and CCA is enabled then go directly to TX if channel is clear. */
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#define CC1101_SIDLE 0x36 /* Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable. */
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#define CC1101_SAFC 0x37 /* Perform AFC adjustment of the frequency synthesizer */
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#define CC1101_SWOR 0x38 /* Start automatic RX polling sequence (Wake-on-Radio) */
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#define CC1101_SPWD 0x39 /* Enter power down mode when CSn goes high. */
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#define CC1101_SFRX 0x3A /* Flush the RX FIFO buffer. */
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#define CC1101_SFTX 0x3B /* Flush the TX FIFO buffer. */
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#define CC1101_SWORRST 0x3C /* Reset real time clock. */
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#define CC1101_SNOP 0x3D /* No operation. */
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/*
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* Chip Status Byte
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*/
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/* Bit fields in the chip status byte */
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#define CC1101_STATUS_CHIP_RDYn_BM 0x80
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#define CC1101_STATUS_STATE_BM 0x70
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#define CC1101_STATUS_FIFO_BYTES_AVAILABLE_BM 0x0F
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/* Chip states */
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#define CC1101_STATE_IDLE 0x00
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#define CC1101_STATE_RX 0x10
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#define CC1101_STATE_TX 0x20
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#define CC1101_STATE_FSTXON 0x30
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#define CC1101_STATE_CALIBRATE 0x40
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#define CC1101_STATE_SETTLING 0x50
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#define CC1101_STATE_RX_OVERFLOW 0x60
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#define CC1101_STATE_TX_UNDERFLOW 0x70
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/* Values of the MACRSTATE register */
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#define CC1101_MARCSTATE_SLEEP 0x00
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#define CC1101_MARCSTATE_IDLE 0x01
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#define CC1101_MARCSTATE_XOFF 0x02
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#define CC1101_MARCSTATE_VCOON_MC 0x03
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#define CC1101_MARCSTATE_REGON_MC 0x04
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#define CC1101_MARCSTATE_MANCAL 0x05
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#define CC1101_MARCSTATE_VCOON 0x06
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#define CC1101_MARCSTATE_REGON 0x07
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#define CC1101_MARCSTATE_STARTCAL 0x08
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#define CC1101_MARCSTATE_BWBOOST 0x09
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#define CC1101_MARCSTATE_FS_LOCK 0x0A
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#define CC1101_MARCSTATE_IFADCON 0x0B
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#define CC1101_MARCSTATE_ENDCAL 0x0C
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#define CC1101_MARCSTATE_RX 0x0D
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#define CC1101_MARCSTATE_RX_END 0x0E
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#define CC1101_MARCSTATE_RX_RST 0x0F
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#define CC1101_MARCSTATE_TXRX_SWITCH 0x10
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#define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11
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#define CC1101_MARCSTATE_FSTXON 0x12
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#define CC1101_MARCSTATE_TX 0x13
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#define CC1101_MARCSTATE_TX_END 0x14
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#define CC1101_MARCSTATE_RXTX_SWITCH 0x15
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#define CC1101_MARCSTATE_TXFIFO_UNDERFLOW 0x16
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/*
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* General Purpose, Test Output Pin Options
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*/
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/* Associated to the RX FIFO: Asserts when RX FIFO is filled at or above
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* the RX FIFO threshold. De-asserts when RX FIFO is drained below the
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* same threshold. */
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#define CC1101_GDO_RXFIFO_THR 0x00
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/* Associated to the RX FIFO: Asserts when RX FIFO is filled at or above
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* the RX FIFO threshold or the end of packet is reached. De-asserts when
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* the RX FIFO is empty. */
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#define CC1101_GDO_RXFIFO_THREND 0x01
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/* Associated to the TX FIFO: Asserts when the TX FIFO is filled at or
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* above the TX FIFO threshold. De-asserts when the TX FIFO is below the
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* same threshold. */
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#define CC1101_GDO_TXFIFO_THR 0x02
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/* Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts
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* when the TX FIFO is drained below theTX FIFO threshold. */
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#define CC1101_GDO_TXFIFO_FULL 0x03
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/* Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has
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* been flushed. */
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#define CC1101_GDO_RXFIFO_OVR 0x04
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/* Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is
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* flushed. */
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#define CC1101_GDO_TXFIFO_UNR 0x05
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/* Asserts when sync word has been sent / received, and de-asserts at the
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* end of the packet. In RX, the pin will de-assert when the optional
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* address check fails or the RX FIFO overflows. In TX the pin will
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* de-assert if the TX FIFO underflows. */
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#define CC1101_GDO_SYNC 0x06
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/* Asserts when a packet has been received with CRC OK. De-asserts when
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* the first byte is read from the RX FIFO. */
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#define CC1101_GDO_CRCOK 0x07
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/* Preamble Quality Reached. Asserts when the PQI is above the programmed
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* PQT value. */
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#define CC1101_GDO_PREAMBLE 0x08
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/* Clear channel assessment. High when RSSI level is below threshold
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* (dependent on the current CCA_MODE setting). */
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#define CC1101_GDO_CHCLEAR 0x09
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/* Lock detector output. The PLL is in lock if the lock detector output
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* has a positive transition or is constantly logic high. To check for
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* PLL lock the lock detector output should be used as an interrupt for
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* the MCU. */
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#define CC1101_GDO_LOCK 0x0A
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/* Serial Clock. Synchronous to the data in synchronous serial mode.
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* In RX mode, data is set up on the falling edge by CC1101 when GDOx_INV=0.
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* In TX mode, data is sampled by CC1101 on the rising edge of the serial
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* clock when GDOx_INV=0. */
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#define CC1101_GDO_SSCLK 0x0B
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/* Serial Synchronous Data Output. Used for synchronous serial mode. */
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#define CC1101_GDO_SSDO 0x0C
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/* Serial Data Output. Used for asynchronous serial mode. */
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#define CC1101_GDO_ASDO 0x0D
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/* Carrier sense. High if RSSI level is above threshold. */
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#define CC1101_GDO_CARRIER 0x0E
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/* CRC_OK. The last CRC comparison matched. Cleared when entering or
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* restarting RX mode. */
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#define CC1101_GDO_CRCOK2 0x0F
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/* RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for
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* alternative serial RX output. */
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#define CC1101_GDO_RXOUT1 0x16
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/* RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for
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* alternative serial RX output. */
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#define CC1101_GDO_RXOUT0 0x17
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/* PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX
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* states. To control an external PA or RX/TX switch in applications
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* where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F
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* instead. */
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#define CC1101_GDO_PA_PD 0x1B
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/* LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX
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* states. To control an external LNA or RX/TX switch in applications
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* where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F
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* instead. */
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#define CC1101_GDO_LNA_PD 0x1C
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/* RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative
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* serial RX output. */
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#define CC1101_GDO_RXSYMTICK 0x1D
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#define CC1101_GDO_WOR_EVNT0 0x24
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#define CC1101_GDO_WOR_EVNT1 0x25
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#define CC1101_GDO_CLK32K 0x27
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#define CC1101_GDO_CHIP_RDYn 0x29
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#define CC1101_GDO_XOSC_STABLE 0x2B
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/* GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input
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* (for serial TX data). */
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#define CC1101_GDO_GDO0_Z_EN_N 0x2D
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/* High impedance (3-state). */
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#define CC1101_GDO_HIZ 0x2E
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/* HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control
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* an external LNA/PA or RX/TX switch. */
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#define CC1101_GDO_HW 0x2F
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/* There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an
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* output at any time. If CLK_XOSC/n is to be monitored on one of the
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* GDO pins, the other two GDO pins must be configured to values less
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* than 0x30. The GDO0 default value is CLK_XOSC/192. To optimize RF
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* performance, these signals should not be used while the radio is
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* in RX or TX mode. */
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#define CC1101_GDO_CLK_XOSC1 0x30
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#define CC1101_GDO_CLK_XOSC1_5 0x31
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#define CC1101_GDO_CLK_XOSC2 0x32
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#define CC1101_GDO_CLK_XOSC3 0x33
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#define CC1101_GDO_CLK_XOSC4 0x34
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#define CC1101_GDO_CLK_XOSC6 0x35
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#define CC1101_GDO_CLK_XOSC8 0x36
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#define CC1101_GDO_CLK_XOSC12 0x37
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#define CC1101_GDO_CLK_XOSC16 0x38
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#define CC1101_GDO_CLK_XOSC24 0x39
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#define CC1101_GDO_CLK_XOSC32 0x3A
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#define CC1101_GDO_CLK_XOSC48 0x3B
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#define CC1101_GDO_CLK_XOSC64 0x3C
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#define CC1101_GDO_CLK_XOSC96 0x3D
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#define CC1101_GDO_CLK_XOSC128 0x3E
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#define CC1101_GDO_CLK_XOSC192 0x3F
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/*
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* Others ...
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*/
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#define CC1101_LQI_CRC_OK_BM 0x80
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#define CC1101_LQI_EST_BM 0x7F
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/************************************************************************************
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* Private Data Types
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************************************************************************************/
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struct chipcon_c1101_rfsettings_s {
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uint8_t FSCTRL1; /* Frequency synthesizer control. */
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uint8_t IOCFG0; /* GDO0 output pin configuration */
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uint8_t FSCTRL0; /* Frequency synthesizer control. */
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uint8_t FREQ2; /* Frequency control word, high byte. */
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uint8_t FREQ1; /* Frequency control word, middle byte. */
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uint8_t FREQ0; /* Frequency control word, low byte. */
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uint8_t MDMCFG4; /* Modem configuration. */
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uint8_t MDMCFG3; /* Modem configuration. */
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uint8_t MDMCFG2; /* Modem configuration. */
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uint8_t MDMCFG1; /* Modem configuration. */
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uint8_t MDMCFG0; /* Modem configuration. */
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uint8_t CHANNR; /* Channel number. */
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uint8_t DEVIATN; /* Modem deviation setting (when FSK modulation is enabled). */
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uint8_t FREND1; /* Front end RX configuration. */
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uint8_t FREND0; /* Front end RX configuration. */
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uint8_t MCSM0; /* Main Radio Control State Machine configuration. */
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uint8_t FOCCFG; /* Frequency Offset Compensation Configuration. */
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uint8_t BSCFG; /* Bit synchronization Configuration. */
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uint8_t AGCCTRL2; /* AGC control. */
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uint8_t AGCCTRL1; /* AGC control. */
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uint8_t AGCCTRL0; /* AGC control. */
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uint8_t FSCAL3; /* Frequency synthesizer calibration. */
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uint8_t FSCAL2; /* Frequency synthesizer calibration. */
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uint8_t FSCAL1; /* Frequency synthesizer calibration. */
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uint8_t FSCAL0; /* Frequency synthesizer calibration. */
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uint8_t FSTEST; /* Frequency synthesizer calibration control */
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uint8_t TEST2; /* Various test settings. */
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uint8_t TEST1; /* Various test settings. */
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uint8_t TEST0; /* Various test settings. */
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uint8_t FIFOTHR; /* RXFIFO and TXFIFO thresholds. */
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uint8_t IOCFG2; /* GDO2 output pin configuration */
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uint8_t PKTCTRL1; /* Packet automation control. */
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uint8_t PKTCTRL0; /* Packet automation control. */
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uint8_t ADDR; /* Device address. */
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uint8_t PKTLEN; /* Packet length. */
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};
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struct chipcon_cc1101_dev_s {
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struct spi_dev_s * spi;
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struct chipcon_c1101_rfsettings_s * settings;
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/** LIS331DL Access with range check
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*
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* \param dev LIS331 DL Private Structure
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* \param subaddr LIS331 Sub Address
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* \param buf Pointer to buffer, either for read or write access
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* \param length when >0 it denotes read access, when <0 it denotes write access of -length
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* \return OK on success or errno is set.
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**/
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int chipcon_cc1101_access(struct chipcon_cc1101_dev_s * dev, uint8_t subaddr, uint8_t *buf, int length)
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{
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return 0;
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}
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/****************************************************************************
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* Callbacks
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****************************************************************************/
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/** External line triggers this callback
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*
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* The concept todo is:
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* - GPIO provides EXTI Interrupt
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* - It should handle EXTI Interrupts in ISR, to which chipcon can
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* register a callback (and others). The ISR then foreach() calls a
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* its callback, and it is up to peripheral to find, whether the cause
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* of EXTI ISR was itself.
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**/
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void chipcon_cc1101_eventcb(void)
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{
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}
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|
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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struct chipcon_cc1101_dev_s * chipcon_cc1101_init(struct spi_dev_s * spi)
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{
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/* Powerup or wake-up, if it was previously set into some power-down state */
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|
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/* Inquiry part number and version */
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|
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/* Reset chip, check status bytes */
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|
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/* Load it with default configuration */
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|
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/* Bind to external interrupt line */
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return NULL;
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}
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int chipcon_cc1101_deinit(struct chipcon_cc1101_dev_s * dev)
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{
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/* Power down chip, possibly in some inactive state */
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|
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return 0;
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}
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|
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int chipcon_cc1101_setgdo(struct chipcon_cc1101_dev_s * dev, uint8_t pin, uint8_t function)
|
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{
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return 0;
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}
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|
|
|
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int chipcon_cc1101_setrf(struct chipcon_cc1101_dev_s * dev, uint32_t frequency, int modulation)
|
|
{
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|
return 0;
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}
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|
|
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int chipcon_cc1101_read(struct chipcon_cc1101_dev_s * dev, uint8_t * data, size_t size)
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{
|
|
return 0;
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}
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|
|
|
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int chipcon_cc1101_write(struct chipcon_cc1101_dev_s * dev, const uint8_t * data, size_t size)
|
|
{
|
|
return 0;
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}
|
|
|
|
|
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int chipcon_cc1101_listen(struct chipcon_cc1101_dev_s * dev)
|
|
{
|
|
return 0;
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|
}
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|
|
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int chipcon_cc1101_send(struct chipcon_cc1101_dev_s * dev)
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|
{
|
|
return 0;
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|
}
|
|
|
|
|
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int chipcon_cc1101_idle(struct chipcon_cc1101_dev_s * dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
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int chipcon_cc1101_powerup(struct chipcon_cc1101_dev_s * dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
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int chipcon_cc1101_powerdown(struct chipcon_cc1101_dev_s * dev)
|
|
{
|
|
return 0;
|
|
}
|