399 lines
11 KiB
ArmAsm
399 lines
11 KiB
ArmAsm
/************************************************************
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* up_vectors.S
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************/
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/************************************************************
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* Included Files
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************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include "c5471.h"
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/************************************************************
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* Definitions
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************************************************************/
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/************************************************************
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* Global Data
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************************************************************/
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.data
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up_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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up_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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up_aborttmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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/************************************************************
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* Macros
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************************************************************/
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/************************************************************
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* Private Functions
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************************************************************/
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.text
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/************************************************************
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* Public Functions
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************************************************************/
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.text
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/************************************************************
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* Name: up_vectorirq
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*
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* Description:
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* Interrupt excetpion. Entered in IRQ mode with spsr = SVC
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* CPSR, lr = SVC PC
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************************************************************/
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.global up_vectorirq
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.type up_vectorirq, %function
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up_vectorirq:
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/* On entry, we are in IRQ mode. We are free to use
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* the IRQ mode r13 and r14.
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*
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*/
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ldr r13, .Lirqtmp
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sub lr, lr, #4
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str lr, [r13] @ save lr_IRQ
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mrs lr, spsr
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str lr, [r13, #4] @ save spsr_IRQ
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/* Then switch back to SVC mode */
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bic lr, lr, #MODE_MASK /* Keep F and T bits */
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orr lr, lr, #I_BIT | SVC_MODE
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msr spsr_c, lr /* Swith to SVC mode */
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/* Create a context structure */
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r14} /* Save the SVC mode regs */
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r1, r2} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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add r0, sp, #(4*REG_PC) /* Offset to pc, cpsr storage */
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stmia r0, {r1, r2}
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/* Now decode the interrupt */
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#if 0
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ldr lr, =SRC_IRQ_BIN_REG /* Fetch encoded IRQ */
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ldr r0, [lr]
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and r0, r0, #0x0f /* Valid range is 0..15 */
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/* Problems here... cannot read SRC_IRQ_BIN_REQ (and/or
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* SRC_IRQ_REQ because this will clear edge triggered
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* interrupts. Plus, no way to validate spurious
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* interrupt.
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*/
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#else
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ldr r6, =SRC_IRQ_REG
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ldr r6, [r6] /* Get source IRQ reg */
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mov r0, #0 /* Assume IRQ0_IRQ set */
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.Lmorebits:
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tst r6, #1 /* Is IRQ set? */
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bne .Lhaveirq /* Yes... we have the IRQ */
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add r0, r0, #1 /* Setup next IRQ */
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mov r6, r6, lsr #1 /* Shift right one */
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cmp r0, #16 /* Only 16 valid bits */
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bcc .Lmorebits /* Keep until we have looked
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* at all bits */
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b .Lnoirqset /* If we get here, there is
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* no pending interrupt */
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.Lhaveirq:
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#endif
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/* Then call the data abort handler with interrupt disabled.
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* rq_dispatch(int irq, struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r1, sp /* Get r1=xcp */
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bl up_prefetchabort /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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.Lnoirqset:
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.Lirqtmp:
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.word up_irqtmp
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.align 5
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/************************************************************
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* Function: up_vectorswi
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*
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* Description:
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* SWI interrupt. We enter the SWI in SVC mode
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************************************************************/
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.global up_vectorswi
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.type up_vectorswi, %function
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up_vectorswi:
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/* The c547x rrload bootloader intemediates all
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* interrupts. For the* case of the SWI, it mucked
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* with the stack to create some temporary registers.
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* We'll have to recover from this mucking here.
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*/
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ldr r14, [sp,#-0x4] /* rrload workaround */
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/* Create a context structure */
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r14} /* Save the SVC mode regs */
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mrs r2, spsr /* Get the saved CPSR */
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mov r1, r14 /* Save r14 as the PC */
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add r0, sp, #(4*REG_PC) /* Offset to pc, cpsr storage */
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stmia r0, {r1, r2}
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/* Then call the SWI handler with interrupt disabled.
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* void up_syscall(struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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bl up_syscall /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.align 5
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/************************************************************
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* Name: up_vectordata
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*
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* Description:
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* Data abort Exception dispatcher. Give control to data
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* abort handler. This function is entered in ABORT mode
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* with spsr = SVC CPSR, lr = SVC PC
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*
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************************************************************/
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.global up_vectordata
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.type up_vectordata, %function
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up_vectordata:
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/* On entry we are free to use the ABORT mode registers
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* r13 and r14
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*/
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ldr r13, .Ldaborttmp /* Points to temp storage */
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sub lr, lr, #8 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #MODE_MASK /* Keep F and T bits */
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orr lr, lr, #I_BIT | SVC_MODE
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msr spsr_c, lr /* Swith to SVC mode */
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/* Create a context structure */
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r14} /* Save the SVC mode regs */
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ldr r0, .Ldaborttmp /* Points to temp storage */
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ldmia r0, {r1, r2} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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add r0, sp, #(4*REG_PC) /* Offset to pc, cpsr storage */
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stmia r0, {r1, r2}
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/* Then call the data abort handler with interrupt disabled.
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* void up_dataabort(struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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bl up_dataabort /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.Ldaborttmp:
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.word up_aborttmp
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.align 5
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/************************************************************
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* Name: up_vectorprefetch
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*
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* Description:
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* Prefetch abort exception. Entered in ABT mode with
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* spsr = SVC CPSR, lr = SVC PC
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************************************************************/
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.global up_vectorprefetch
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.type up_vectorprefetch, %function
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up_vectorprefetch:
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/* On entry we are free to use the ABORT mode registers
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* r13 and r14
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*/
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ldr r13, .Lpaborttmp /* Points to temp storage */
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sub lr, lr, #4 /* Fixup return */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #MODE_MASK /* Keep F and T bits */
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orr lr, lr, #I_BIT | SVC_MODE
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msr spsr_c, lr /* Swith to SVC mode */
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/* Create a context structure */
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r14} /* Save the SVC mode regs */
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ldr r0, .Lpaborttmp /* Points to temp storage */
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ldmia r0, {r1, r2} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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add r0, sp, #(4*REG_PC) /* Offset to pc, cpsr storage */
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stmia r0, {r1, r2}
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/* Then call the data abort handler with interrupt disabled.
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* void up_prefetchabort(struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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bl up_prefetchabort /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.Lpaborttmp:
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.word up_aborttmp
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.align 5
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/************************************************************
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* Name: up_vectorundefinsn
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*
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* Description:
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* Undefined instruction entry exception. Entered in
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* UND mode, spsr = SVC CPSR, lr = SVC PC
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*
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************************************************************/
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.global up_vectorundefinsn
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.type up_vectorundefinsn, %function
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up_vectorundefinsn:
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/* On entry we are free to use the UND mode registers
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* r13 and r14
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*/
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ldr r13, .Lundeftmp /* Points to temp storage */
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str lr, [r13] /* Save in temp storage */
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mrs lr, spsr /* Get SPSR */
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str lr, [r13, #4] /* Save in temp storage */
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/* Then switch back to SVC mode */
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bic lr, lr, #MODE_MASK /* Keep F and T bits */
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orr lr, lr, #I_BIT | SVC_MODE
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msr spsr_c, lr /* Swith to SVC mode */
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/* Create a context structure */
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r14} /* Save the SVC mode regs */
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ldr r0, .Lundeftmp /* Points to temp storage */
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ldmia r0, {r1, r2} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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add r0, sp, #(4*REG_PC) /* Offset to pc, cpsr storage */
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stmia r0, {r1, r2}
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/* Then call the data abort handler with interrupt disabled.
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* void up_undefinedinsn(struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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bl up_undefinedinsn /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.Lundeftmp:
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.word up_undeftmp
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.align 5
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/************************************************************
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* Name: up_vectorfiq
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*
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* Description:
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* Shouldn't happen
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************************************************************/
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.global up_vectorfiq
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.type up_vectorfiq, %function
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up_vectorfiq:
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subs pc, lr, #4
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/************************************************************
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* Name: up_vectoraddrexcption
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*
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* Description:
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* Shouldn't happen
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*
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************************************************************/
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.global up_vectoraddrexcptn
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.type up_vectoraddrexcptn, %function
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up_vectoraddrexcptn:
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b up_vectoraddrexcptn
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.end
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