445 lines
14 KiB
C
445 lines
14 KiB
C
/****************************************************************************
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* configs/ea3152/src/up_clkinit.c
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* arch/arm/src/board/up_clkinit.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - NXP lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "lpc31_cgu.h"
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#include "lpc31_cgudrvr.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Sub-domain Clock Bitsets *************************************************/
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/* The following bitsets group clocks into bitsets associated with each
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* domain and fractional divider subdomain.
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*
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* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6. Clocks not
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* defined in the clock sets will be sourced with SYS_BASE_CLK.
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*/
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/* Domain 0, Fractional divider 0: */
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#define CGU_CLKSET_DOMAIN0_DIV0 \
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(_D0B(CLKID_APB0CLK)|_D0B(CLKID_APB1CLK)|_D0B(CLKID_APB2CLK)|\
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_D0B(CLKID_APB3CLK)|_D0B(CLKID_APB4CLK)|_D0B(CLKID_AHB2INTCCLK)|\
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_D0B(CLKID_AHB0CLK)|_D0B(CLKID_DMAPCLK)|_D0B(CLKID_DMACLKGATED)|\
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_D0B(CLKID_NANDFLASHS0CLK)|_D0B(CLKID_NANDFLASHPCLK)|\
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_D0B(CLKID_ARM926BUSIFCLK)|_D0B(CLKID_SDMMCHCLK)|_D0B(CLKID_USBOTGAHBCLK)|\
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_D0B(CLKID_ISRAM0CLK)|_D0B(CLKID_ISRAM1CLK)|_D0B(CLKID_ISROMCLK)|\
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_D0B(CLKID_MPMCCFGCLK)|_D0B(CLKID_MPMCCFGCLK2)|_D0B(CLKID_INTCCLK))
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/* Domain 0, Fractional divider 1: */
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#define CGU_CLKSET_DOMAIN0_DIV1 \
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(_D0B(CLKID_ARM926CORECLK))
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/* Domain 0, Fractional divider 2: */
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#define CGU_CLKSET_DOMAIN0_DIV2 \
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(_D0B(CLKID_NANDFLASHAESCLK)|_D0B(CLKID_NANDFLASHNANDCLK))
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/* Domain 0, Fractional divider 3: */
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#define CGU_CLKSET_DOMAIN0_DIV3 \
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(_D0B(CLKID_NANDFLASHECCCLK))
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/* Domain 0, Fractional divider 4: */
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#define CGU_CLKSET_DOMAIN0_DIV4 \
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(_D0B(CLKID_SDMMCCCLKIN))
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/* Domain 0, Fractional divider 5: */
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#define CGU_CLKSET_DOMAIN0_DIV5 \
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(_D0B(CLKID_CLOCKOUT))
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/* Domain 0, Fractional divider 6: */
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#define CGU_CLKSET_DOMAIN0_DIV6 \
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(_D0B(CLKID_EBICLK))
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/* Domain 1 (DOMAINID_AHB0APB0), Clocks 30-39, Fraction dividers 7-8. Clocks
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* not defined in the clock sets will be sourced with AHB_APB0_BASE_CLK.
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*/
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/* Domain 1, Fractional divider 7: */
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#define CGU_CLKSET_DOMAIN1_DIV7 \
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(_D1B(CLKID_ADCCLK))
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/* Domain 1, Fractional divider 8: */
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#define CGU_CLKSET_DOMAIN1_DIV8 \
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(_D1B(CLKID_AHB2APB0PCLK)|_D1B(CLKID_EVENTROUTERPCLK)|\
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_D1B(CLKID_ADCPCLK)|_D1B(CLKID_WDOGPCLK)|_D1B(CLKID_IOCONFPCLK)|\
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_D1B(CLKID_CGUPCLK)|_D1B(CLKID_SYSCREGPCLK)|_D1B(CLKID_OTPPCLK)|\
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_D1B(CLKID_RNGPCLK))
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/* Domain 2 (DOMAINID_AHB0APB1), Clocks 40-49, Fraction dividers 9-10. Clocks
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* not defined in the clock sets will be sourced with AHB_APB1_BASE_CLK.
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*/
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/* Domain 2, Fractional divider 9: */
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#define CGU_CLKSET_DOMAIN2_DIV9 \
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(_D2B(CLKID_AHB2APB1PCLK)|_D2B(CLKID_TIMER0PCLK)|_D2B(CLKID_TIMER1PCLK)|\
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_D2B(CLKID_TIMER2PCLK)|_D2B(CLKID_TIMER3PCLK)|_D2B(CLKID_PWMPCLK)|\
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_D2B(CLKID_PWMPCLKREGS)|_D2B(CLKID_I2C0PCLK)|_D2B(CLKID_I2C1PCLK))
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/* Domain 2, Fractional divider 10: */
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#define CGU_CLKSET_DOMAIN2_DIV10 \
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(_D2B(CLKID_PWMCLK))
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/* Domain 3 (DOMAINID_AHB0APB2), Clocks 50-57, Fraction dividers 11-13. Clocks
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* not defined in the clock sets will be sourced with AHB_APB2_BASE_CLK.
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*/
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/* Domain 3, Fractional divider 11: */
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#define CGU_CLKSET_DOMAIN3_DIV11 \
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( _D3B(CLKID_AHB2APB2PCLK)|_D3B(CLKID_PCMPCLK)|_D3B(CLKID_PCMAPBPCLK)|\
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_D3B(CLKID_UARTAPBCLK)|_D3B(CLKID_LCDPCLK)|_D3B(CLKID_SPIPCLK)|\
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_D3B(CLKID_SPIPCLKGATED))
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/* Domain 3, Fractional divider 12: */
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#define CGU_CLKSET_DOMAIN3_DIV12 \
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(_D3B(CLKID_LCDCLK))
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/* Domain 3, Fractional divider 13: */
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#define CGU_CLKSET_DOMAIN3_DIV13 \
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(0)
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/* Domain 4 (DOMAINID_AHB0APB3), Clocks 58-70, Fraction divider 14. Clocks
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* not defined in the clock sets will be sourced with AHB_APB3_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN4_DIV14 \
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(_D4B(CLKID_AHB2APB3PCLK)|_D4B(CLKID_I2SCFGPCLK)|_D4B(CLKID_EDGEDETPCLK)|\
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_D4B(CLKID_I2STXFIFO0PCLK)|_D4B(CLKID_I2STXIF0PCLK)|_D4B(CLKID_I2STXFIFO1PCLK)|\
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_D4B(CLKID_I2STXIF1PCLK)|_D4B(CLKID_I2SRXFIFO0PCLK)|_D4B(CLKID_I2SRXIF0PCLK)|\
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_D4B(CLKID_I2SRXFIFO1PCLK)|_D4B(CLKID_I2SRXIF1PCLK))
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/* Domain 5 (DOMAINID_PCM), Clock 71, Fraction divider 15. Clocks not
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* defined in the clock sets will be sourced with AHB_APB3_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN5_DIV15 \
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(_D5B(CLKID_PCMCLKIP))
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/* Domain 6 (DOMAINID_UART), Clock 72, Fraction divider 16. Clocks mpt
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* defined in the clock sets will be sourced with UART_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN6_DIV16 \
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(0)
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/* Domain 7 (DOMAINID_CLK1024FS), Clocks 73-86, Fraction dividers 17-22. Clocks
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* not defined in the clock sets will be sourced with CLK1024FS_BASE_CLK.
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*/
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/* Domain 7, Fractional divider 17: */
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#define CGU_CLKSET_DOMAIN7_DIV17 \
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( _D7B(CLKID_I2SEDGEDETECTCLK)|_D7B(CLKID_I2STXWS0)|_D7B(CLKID_I2STXWS1)|\
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_D7B(CLKID_I2SRXWS0)|_D7B(CLKID_I2SRXWS1))
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/* Domain 7, Fractional divider 18: */
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#define CGU_CLKSET_DOMAIN7_DIV18 \
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( _D7B(CLKID_I2STXBCK0N)|_D7B(CLKID_I2STXBCK1N))
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/* Domain 7, Fractional divider 19: */
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#define CGU_CLKSET_DOMAIN7_DIV19 \
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( _D7B(CLKID_I2STXCLK0)|_D7B(CLKID_CLK256FS))
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/* Domain 7, Fractional divider 20: */
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#define CGU_CLKSET_DOMAIN7_DIV20 \
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( _D7B(CLKID_I2SRXBCK0N)|_D7B(CLKID_I2SRXBCK1N))
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/* Domain 7, Fractional divider 21: */
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#define CGU_CLKSET_DOMAIN7_DIV21 \
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(0)
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/* Domain 7, Fractional divider 22: */
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#define CGU_CLKSET_DOMAIN7_DIV22 \
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(0)
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/* Domain 8 (DOMAINID_BCK0, clock 87, and domain 9 (DOMAINID_BCK1), clock 88,
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* are directly connected
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*/
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/* Domain 10 (DOMAINID_SPI), Clocks 89-90, Fraction divider 23. Clocks
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* not defined in the clock sets will be sourced with SPI_CLK_BASE_CLK.
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*/
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#define CGU_CLKSET_DOMAIN10_DIV23 \
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( _D10B(CLKID_SPICLK)|_D10B(CLKID_SPICLKGATED))
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/* Domain 11 (DOMAINID_SYSCLKO, clock 91, is directly connected */
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Default clock configuration for the EA3152 board. Every board must
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* provide an implementation of g_boardclks. This rather complex structure
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* is used by the boot-up logic to configure initial lpc313x clocking.
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*
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* FFAST: 12MHz
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* MASTER PLL Freq: 180MHz;
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* AUDIOPLL Freq: 1024Fs, Fs = 44.1kHz
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*
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* Domain Input Subdomain Divider Ratio
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* ------------------------ ----------------- ----------------- -------------
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* 0 - DOMAIN_SYS MASTER PLL(HPLL1) DOMAIN0_DIV0 1/2
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* DOMAIN0_DIV1 1
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* DOMAIN0_DIV2 1/2
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* DOMAIN0_DIV3 1/4
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* DOMAIN0_DIV4 1/4
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* DOMAIN0_DIV5 1/2
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* DOMAIN0_DIV6 1/2
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*
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* 1 - DOMAIN_AHB0APB0 FFAST DOMAIN1_DIV7 1/38
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* DOMAIN1_DIV8 1/2
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*
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* 2 - DOMAIN_AHB0APB1 FFAST DOMAIN2_DIV9 1/2
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* DOMAIN2_DIV10 1/2
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*
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* 3 - DOMAIN_AHB0APB2 MASTER PLL(HPLL1) DOMAIN3_DIV11 1/2
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* DOMAIN3_DIV12 1/40
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* DOMAIN3_DIV13 1 (not used)
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*
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* 4 - DOMAIN_AHB0APB3 FFAST DOMAIN4_DIV14 1/2
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*
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* 5 - DOMAIN_PCM MASTER PLL(HPLL1) DOMAIN5_DIV15 1/2
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*
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* 6 - DOMAIN_UART FFAST DOMAIN6_DIV16 1
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*
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* 7 - DOMAIN_CLCK1024FS AUDIO PLL(HPLL0) DOMAIN7_DIV17 1/256
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* DOMAIN7_DIV18 1/4
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* DOMAIN7_DIV19 1
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* DOMAIN7_DIV20 1/4
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* DOMAIN7_DIV21 1/32
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* DOMAIN7_DIV22 1/2
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*
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* 8 - DOMAIN_I2SRXBCK0 I2SRX_BCK0 - -
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*
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* 9 - DOMAIN_I2SRXBCK1 I2SRX_BCK1 - -
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*
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* 10 - DOMAIN_SPI MASTER PLL(HPLL1) DOMAIN10_DIV23 1/2
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*
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* 11 - DOMAIN_SYSCLKO FFAST - -
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*/
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const struct lpc31_clkinit_s g_boardclks =
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{
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/* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6 */
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{
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CGU_FREQIN_HPPLL1,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV0},
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{{0, 0, 0}, CGU_CLKSET_DOMAIN0_DIV1},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV2},
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{{1, 1, 4}, CGU_CLKSET_DOMAIN0_DIV3},
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{{1, 1, 4}, CGU_CLKSET_DOMAIN0_DIV4},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV5},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN0_DIV6}
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}
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},
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/* Domain 1 (DOMAINID_AHB0APB0), Clocks 30-39, Fraction dividers 7-8 */
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{
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CGU_FREQIN_FFAST,
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{
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{{1, 1, 38}, CGU_CLKSET_DOMAIN1_DIV7},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN1_DIV8}
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}
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},
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/* Domain 2 (DOMAINID_AHB0APB1), Clocks 40-49, Fraction dividers 9-10 */
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{
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CGU_FREQIN_FFAST,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN2_DIV9},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN2_DIV10}
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}
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},
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/* Domain 3 (DOMAINID_AHB0APB2), Clocks 50-57, Fraction dividers 11-13 */
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{
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CGU_FREQIN_HPPLL1,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN3_DIV11},
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{{1, 1, 40}, CGU_CLKSET_DOMAIN3_DIV12},
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{{0, 0, 0}, CGU_CLKSET_DOMAIN3_DIV13}
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}
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},
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/* Domain 4 (DOMAINID_AHB0APB3), Clocks 58-70, Fraction divider 14 */
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{
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CGU_FREQIN_FFAST,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN4_DIV14}
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}
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},
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/* Domain 5 (DOMAINID_PCM), Clock 71, Fraction divider 15 */
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{
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CGU_FREQIN_HPPLL1,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN5_DIV15}
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}
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},
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/* Domain 6 (DOMAINID_UART), Clock 72, Fraction divider 16 */
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{
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CGU_FREQIN_FFAST,
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{
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{{0, 0, 0}, CGU_CLKSET_DOMAIN6_DIV16}
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}
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},
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/* Domain 7 (DOMAINID_CLK1024FS), Clocks 73-86, Fraction dividers 17-22 */
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{
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CGU_FREQIN_HPPLL0,
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{
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{{1, 1, 256}, CGU_CLKSET_DOMAIN7_DIV17},
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{{1, 1, 4}, CGU_CLKSET_DOMAIN7_DIV18},
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{{0, 0, 0}, CGU_CLKSET_DOMAIN7_DIV19},
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{{1, 1, 4}, CGU_CLKSET_DOMAIN7_DIV20},
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{{1, 1, 32}, CGU_CLKSET_DOMAIN7_DIV21},
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{{1, 1, 2}, CGU_CLKSET_DOMAIN7_DIV22}
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}
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},
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/* Domain 8 (DOMAINID_BCK0, clock 87 */
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{
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CGU_FREQIN_I2SRXBCK0
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},
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/* Domain 9 (DOMAINID_BCK1, clock 88 */
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{
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CGU_FREQIN_I2SRXBCK1
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},
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/* Domain 10 (DOMAINID_SPI), Clocks 89-90, Fraction divider 23 */
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{
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CGU_FREQIN_HPPLL1,
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{
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{{1, 1, 2}, CGU_CLKSET_DOMAIN10_DIV23}
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}
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},
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/* Domain 11 (DOMAINID_SYSCLKO, clock 91 */
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{
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CGU_FREQIN_FFAST
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},
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/* Dynamic fractional divider configuration (7) */
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#if 0 /* Dynamic fractional divider initialization not implemented */
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{
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 64}
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},
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{
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CGU_DYNSEL_ALLBITS, {0, 0, 0}
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},
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 3}
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},
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 6}
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},
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 6}
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},
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 6}
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},
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{
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CGU_DYNSEL_ALLBITS, {1, 1, 3}
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}
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}
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_ledinit
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****************************************************************************/
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