Make MMC header file consistent with other NuttX periperhal header files
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3051 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
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140c658342
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edc751ad77
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_mmc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* MMC Sub-block */
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#define HCS12_MMC_INITRM 0x0010 /* Internal RAM Position Register */
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# define MMC_INITRM_RAMHAL (1 << 0) /* Bit 0: RAM High-Align */
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# define MMC_INITRM_RAM_SHIFT (3) /* Bits 3-7: Internal RAM Map Position */
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# define MMC_INITRM_RAM_MASK (0x1f << MMC_INITRM_RAM_SHIFT)
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# define MMC_INITRM_RAM(addr) (((addr) >> (11-MMC_INITRM_RAM_SHIFT)) & MMC_INITRM_RAM_MASK)
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#define HCS12_MMC_INITRG 0x0011 /* Internal Registers Position Register */
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# define MMC_INITRG_REG_SHIFT (3) /* Bits 3-6: Internal RAM Map Position */
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# define MMC_INITRG_REG_MASK (0x0f << MMC_INITRG_REG_SHIFT)
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# define MMC_INITRG_REG(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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#define HCS12_MMC_INITEE 0x0012 /* Internal EEPROM Position Register */
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# define MMC_INITEE_EEON (1 << 0) /* Bit 0: Enable EEPROM */
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# define MMC_INITEE_EE_SHIFT (3) /* Bits 3-7: Internal EEPROM Map Position */
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# define MMC_INITEE_EE_MASK (0x1f << MMC_INITEE_EE_SHIFT)
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# define MMC_INITEE_EE(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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#define HCS12_MMC_MISC 0x0013 /* Miscellaneous System Control Register */
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# define MMC_MISC_ROMON (1 << 0) /* Bit 0: Enable FLASH EEPROM or ROM */
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# define MMC_MISC_ROMHM (1 << 1) /* Bit 1: FLASH EEPROM or ROM Only in Second Half of Memory Map */
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# define MMC_MISC_EXSTR_SHIFT (3) /* Bits 3-7: External Access Stretch Bits */
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# define MMC_MISC_EXSTR_MASK (0x1f << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS0 (0 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS1 (1 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS2 (2 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS3 (3 << MMC_MISC_EXSTR_SHIFT)
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#define HCS12_MMC_TESTREG0 0x0014 /* Reserved Test Register 0 */
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#define HCS12_MMC_TESTREG1 0x0017 /* Reserved Test Register 1 */
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#define HCS12_MMC_MEMSIZ0 0x001c /* Memory Size Register 0 */
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# define MMC_MEMSIZ0_RAMSW_SHIFT (0) /* Bits 0-2: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ0_RAMSW_MASK (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_2KB (0 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_4KB (1 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_6KB (2 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_8KB (3 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_10KB (4 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_12KB (5 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_14KB (6 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_16KB (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MMC_MEMSIZ0_EEPSW_SHIFT (4) /* Bits 4-5: Allocated EEPROM Memory Space */
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# define MMC_MEMSIZ0_EEPSW_MASK (3 << MMC_MEMSIZ0_EEPSW_SHIFT)
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# define MEMSIZ0_EEPSW_OKB (0 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_2KB (1 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_4KB (2 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_5KB (3 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MMC_MEMSIZ0_REGSW (1 << 7) /* Bits 7: Allocated System Register Space */
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#define HCS12_MMC_MEMSIZ1 0x001d /* Memory Size Register 1 */
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# define MMC_MEMSIZ1_PAGSW_SHIFT (0) /* Bits 0-1: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ1_PAGSW_MASK (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_128KB (0 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_256KB (1 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_512KB (2 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_1MB (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MMC_MEMSIZ1_ROMSW_SHIFT (6) /* Bits 6-7: Allocated System RAM Memory Space */
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# define MMC_MEMSIZ1_ROMSW_MASK (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_0KB (0 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_16KB (1 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_48KB (2 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_64KB (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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#define HCS12_MMC_PPAGE 0x0030 /* Program Page Index Register */
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# define MMC_PPAGE_PIX_SHIFT (0) /* Bits 0-5 Program Page Index Bits 5–0 */
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# define MMC_PPAGE_PIX_MASK (0x3f << MMC_PPAGE_PIX_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMC_H */
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@ -0,0 +1,161 @@
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMCV4_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMCV4_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_MMC_INITRM_OFFSET 0x0010 /* Internal RAM Position Register */
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#define HCS12_MMC_INITRG_OFFSET 0x0011 /* Internal Registers Position Register */
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#define HCS12_MMC_INITEE_OFFSET 0x0012 /* Internal EEPROM Position Register */
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#define HCS12_MMC_MISC_OFFSET 0x0013 /* Miscellaneous System Control Register */
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#define HCS12_MMC_MTST0_OFFSET 0x0014 /* Reserved Test Register 0 */
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#define HCS12_MMC_MTST1_OFFSET 0x0017 /* Reserved Test Register 1 */
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#define HCS12_MMC_MEMSIZ0_OFFSET 0x001c /* Memory Size Register 0 */
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#define HCS12_MMC_MEMSIZ1_OFFSET 0x001d /* Memory Size Register 1 */
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#define HCS12_MMC_PPAGE_OFFSET 0x0030 /* Program Page Index Register */
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/* Register Addresses ***************************************************************/
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#define HCS12_MMC_INITRM (HCS12_CORE1_BASE+HCS12_MMC_INITRM_OFFSET)
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#define HCS12_MMC_INITRG (HCS12_CORE1_BASE+HCS12_MMC_INITRG_OFFSET)
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#define HCS12_MMC_INITEE (HCS12_CORE1_BASE+HCS12_MMC_INITEE_OFFSET)
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#define HCS12_MMC_MISC (HCS12_CORE1_BASE+HCS12_MMC_MISC_OFFSET)
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#define HCS12_MMC_MTST0 (HCS12_CORE1_BASE+HCS12_MMC_MTST0_OFFSET)
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#define HCS12_MMC_MTST1 (HCS12_CORE1_BASE+HCS12_MMC_MTST1_OFFSET)
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#define HCS12_MMC_MEMSIZ0 (HCS12_CORE1_BASE+HCS12_MMC_MEMSIZ0_OFFSET)
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#define HCS12_MMC_MEMSIZ1 (HCS12_CORE1_BASE+HCS12_MMC_MEMSIZ1_OFFSET)
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#define HCS12_MMC_PPAGE (HCS12_CORE1_BASE+HCS12_MMC_PPAGE_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Internal RAM Position Register */
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#define MMC_INITRM_RAMHAL (1 << 0) /* Bit 0: RAM High-Align */
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#define MMC_INITRM_RAM_SHIFT (3) /* Bits 3-7: Internal RAM Map Position */
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#define MMC_INITRM_RAM_MASK (0x1f << MMC_INITRM_RAM_SHIFT)
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#define MMC_INITRM_RAM(addr) (((addr) >> (11-MMC_INITRM_RAM_SHIFT)) & MMC_INITRM_RAM_MASK)
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/* Internal Registers Position Register */
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#define MMC_INITRG_REG_SHIFT (3) /* Bits 3-6: Internal RAM Map Position */
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#define MMC_INITRG_REG_MASK (0x0f << MMC_INITRG_REG_SHIFT)
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#define MMC_INITRG_REG(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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/* Internal EEPROM Position Register */
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#define MMC_INITEE_EEON (1 << 0) /* Bit 0: Enable EEPROM */
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#define MMC_INITEE_EE_SHIFT (3) /* Bits 3-7: Internal EEPROM Map Position */
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#define MMC_INITEE_EE_MASK (0x1f << MMC_INITEE_EE_SHIFT)
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#define MMC_INITEE_EE(addr) (((addr) >> (11-MMC_INITRG_REG_SHIFT)) & MMC_INITRG_REG_SHIFT)
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/* Miscellaneous System Control Register */
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#define MMC_MISC_ROMON (1 << 0) /* Bit 0: Enable FLASH EEPROM or ROM */
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#define MMC_MISC_ROMHM (1 << 1) /* Bit 1: FLASH EEPROM or ROM Only in Second Half of Memory Map */
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#define MMC_MISC_EXSTR_SHIFT (2) /* Bits 2-3: External Access Stretch Bits */
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#define MMC_MISC_EXSTR_MASK (3 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS0 (0 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS1 (1 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS2 (2 << MMC_MISC_EXSTR_SHIFT)
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# define MISC_EXSTR_CLKS3 (3 << MMC_MISC_EXSTR_SHIFT)
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/* Reserved Test Register 0/1 -- Not documented */
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/* Memory Size Register 0 */
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#define MMC_MEMSIZ0_RAMSW_SHIFT (0) /* Bits 0-2: Allocated System RAM Memory Space */
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#define MMC_MEMSIZ0_RAMSW_MASK (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_2KB (0 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_4KB (1 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_6KB (2 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_8KB (3 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_10KB (4 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_12KB (5 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_14KB (6 << MMC_MEMSIZ0_RAMSW_SHIFT)
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# define MEMSIZ0_RAMSW_16KB (7 << MMC_MEMSIZ0_RAMSW_SHIFT)
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#define MMC_MEMSIZ0_EEPSW_SHIFT (4) /* Bits 4-5: Allocated EEPROM Memory Space */
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#define MMC_MEMSIZ0_EEPSW_MASK (3 << MMC_MEMSIZ0_EEPSW_SHIFT)
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# define MEMSIZ0_EEPSW_OKB (0 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_2KB (1 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_4KB (2 << MMC_MEMSIZ0_EEPSW_MASK)
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# define MEMSIZ0_EEPSW_5KB (3 << MMC_MEMSIZ0_EEPSW_MASK)
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#define MMC_MEMSIZ0_REGSW (1 << 7) /* Bits 7: Allocated System Register Space */
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/* Memory Size Register 1 */
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#define MMC_MEMSIZ1_PAGSW_SHIFT (0) /* Bits 0-1: Allocated System RAM Memory Space */
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#define MMC_MEMSIZ1_PAGSW_MASK (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_128KB (0 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_256KB (1 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_512KB (2 << MMC_MEMSIZ1_PAGSW_SHIFT)
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# define MEMSIZ1_PAGSW_1MB (3 << MMC_MEMSIZ1_PAGSW_SHIFT)
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#define MMC_MEMSIZ1_ROMSW_SHIFT (6) /* Bits 6-7: Allocated System RAM Memory Space */
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#define MMC_MEMSIZ1_ROMSW_MASK (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_0KB (0 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_16KB (1 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_48KB (2 << MMC_MEMSIZ1_ROMSW_SHIFT)
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# define MEMSIZ1_ROMSW_64KB (3 << MMC_MEMSIZ1_ROMSW_SHIFT)
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/* Program Page Index Register */
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#define MMC_PPAGE_PIX_SHIFT (0) /* Bits 0-5 Program Page Index Bits 5–0 */
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#define MMC_PPAGE_PIX_MASK (0x3f << MMC_PPAGE_PIX_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_MMCV4_H */
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@ -41,7 +41,7 @@
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#include <nuttx/config.h>
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#include "mc9s12ne64_internal.h"
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#include "mc9s12ne64_mmc.h"
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#include "mc9s12ne64_mmcv4.h"
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#include "mc9s12ne64_crg.h"
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#include "mc9s12ne64_flash.h"
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