From ec69455a810f85f6933ea37da99c79d133396099 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 5 Dec 2011 16:41:20 +0000 Subject: [PATCH] Fixes for STM32F40xxx port git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4135 7fd9a85b-ad96-42d3-883c-3090e2eb8679 --- nuttx/ChangeLog | 9 +++---- .../arm/src/stm32/chip/stm32f40xxx_gpio.h | 24 +++++++++---------- .../src/stm32/chip/stm32f40xxx_memorymap.h | 2 +- nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 4 ++-- 4 files changed, 20 insertions(+), 19 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 1150fd2c3..2cf3dea33 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -2217,14 +2217,13 @@ * fs/fat/fs_fat32util.c: In fat_systime2fattime(void) should be clock_gettime() and not clock_gettime(). Also, there is a place where FAT date is used instead of FAT time. (Thanks to David Sidrane). - * arch/arm/src/stm32: Add support for the STM3240xxx MCU family. * arch/arm/src/stm32 and arch/arm/include/stm32: Add support for the - STM32F50xxx family of MCUs. + STM32F40xxx family of MCUs. * configs/stm3240g-eval: Add framework for the STMicro STM3240G-EVAL board. * include/sys/types.h: wchar_t is a builtin type in C++ and its declaration can cause errors with certain C++ compilers. - * sched/sig_timedwait.c: Fix signal handling with the returned info + * sched/sig_timedwait.c: Fix signal handling when the returned info is NULL. Before this change, it would derefence a NULL pointer in this case. * graphics/nxfonts/nxfonts_sans17x22.h and nxfonts_sans20x26.h: Add @@ -2234,4 +2233,6 @@ * drivers/input/ads7843e.c and tsc2007.c: Fix some errors in the poll setup error checking that was cloned into both drivers. * sched/mq_notify.c: Set errno appropriately on failures. There are - still severl message queue functions that do not set errno! \ No newline at end of file + still several message queue functions that do not set errno! + * arch/arm/src/stm32: Fixes to several STM32F40xxx files (contributed by + Mikhail Bychek). diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index c1704fdf2..aa7353ed9 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -183,7 +183,7 @@ #define GPIO_MODER_ALT (2) /* Alternate mode */ #define GPIO_MODER_ANALOG (3) /* Analog mode */ -#define GPIO_MODER_SHIFT(n) ((n) << 2) +#define GPIO_MODER_SHIFT(n) ((n) << 1) #define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) #define GPIO_MODER0_SHIFT (0) @@ -231,7 +231,7 @@ #define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */ #define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -#define GPIO_OSPEED_SHIFT(n) ((n) << 2) +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) #define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) #define GPIO_OSPEED0_SHIFT (0) @@ -273,7 +273,7 @@ #define GPIO_PUPDR_PULLUP (1) /* Pull-up */ #define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ -#define GPIO_PUPDR_SHIFT(n) ((n) << 2) +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) #define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) #define GPIO_PUPDR0_SHIFT (0) @@ -329,7 +329,7 @@ /* GPIO alternate function low/high register */ -#define GPIO_AFR_SHIFT(n) ((n) << 4) +#define GPIO_AFR_SHIFT(n) ((n) << 2) #define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) #define GPIO_AFRL0_SHIFT (0) @@ -350,21 +350,21 @@ #define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) #define GPIO_AFRH8_SHIFT (0) -#define GPIO_AFRH8_MASK (15 << GPIO_AFRH0_SHIFT) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) #define GPIO_AFRH9_SHIFT (4) -#define GPIO_AFRH9_MASK (15 << GPIO_AFRH1_SHIFT) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) #define GPIO_AFRH10_SHIFT (8) -#define GPIO_AFRH10_MASK (15 << GPIO_AFRH2_SHIFT) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) #define GPIO_AFRH11_SHIFT (12) -#define GPIO_AFRH11_MASK (15 << GPIO_AFRH3_SHIFT) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) #define GPIO_AFRH12_SHIFT (16) -#define GPIO_AFRH12_MASK (15 << GPIO_AFRH4_SHIFT) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) #define GPIO_AFRH13_SHIFT (20) -#define GPIO_AFRH13_MASK (15 << GPIO_AFRH5_SHIFT) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) #define GPIO_AFRH14_SHIFT (24) -#define GPIO_AFRH14_MASK (15 << GPIO_AFRH6_SHIFT) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) #define GPIO_AFRH15_SHIFT (28) -#define GPIO_AFRH15_MASK (15 << GPIO_AFRH7_SHIFT) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h index 3d118fd8c..ad2e6f000 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h @@ -164,8 +164,8 @@ #define STM32_GPIOH_BASE 0x40021C00 /* 0x40021C00-0x40021fff: GPIO Port H */ #define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIO Port I */ #define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: Reset and Clock control RCC */ #define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash memory interface */ -#define STM32_RCC_BASE 0x40038000 /* 0x40023800-0x40023bff: Reset and Clock control RCC */ #define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: Backup SRAM (BKPSRAM) */ #define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */ #define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */ diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c index 57227f08f..6453c619f 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -118,7 +118,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32_RCC_APB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); /* Enable GPIOA, GPIOB, .... GPIOI*/ @@ -194,7 +194,7 @@ static inline void rcc_enableahb1(void) regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN); #endif - putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /****************************************************************************