Added ST71x system timer logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1115 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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d647ebf797
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e0dbb11563
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@ -81,7 +81,7 @@
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#define STR71X_IRQ_T0OC1 (30)
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#define STR71X_IRQ_T0OC2 (31)
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#define LPC214X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define NR_IRQS 32
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/* FIQ channels */
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@ -118,5 +118,5 @@ EXTERN int up_irqpriority(int irq, ubyte priority); /* Set interrupt priority (0
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#endif
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#endif
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#endif /* __ARCH_LPC214X_IRQ_H */
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#endif /* __ARCH_ARM_INCLUDE_STR71X_IRQ_H */
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@ -49,38 +49,11 @@
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*****************************************************************************/
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/* This file holds the NuttX start logic that runs when the STR711
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* is reset. This logic must be located at address 0x0000:0000 in
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* flash but may be linked to run at different locations based on
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* the selected mode:
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*
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* default: Executes from 0x0000:0000. In non-default modes, the
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* MEMAP register is set override the settings of the CPU configuration
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* pins.
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*
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* CONFIG_EXTMEM_MODE: Code executes from external memory starting at
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* address 0x6000:0000.
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*
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* CONFIG_RAM_MODE: Code executes from on-chip RAM at address
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* 0x2000:0000.
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*
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* Starupt Code must be linked to run at the correct address
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* corresponding to the selected mode.
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* is reset. This logic must be located at address 0x4000:0000 in
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* flash. It will also be mapped to address zero when the STR711 is
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* reset.
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*/
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#if defined(CONFIG_EXTMEM_MODE)
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# if CONFIG_CODE_BASE != STR71X_EXTMEM_BASE
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# error "CONFIG_CODE_BASE must be 0x60000000 in EXTMEM mode"
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# endif
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#elif defined(CONFIG_RAM_MODE)
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# if CONFIG_CODE_BASE != STR71X_ONCHIP_RAM_BASE
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# error "CONFIG_CODE_BASE must be 0x20000000 in EXTMEM mode"
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# endif
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#else
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# if CONFIG_CODE_BASE != STR71X_FLASH_BASE
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# error "CONFIG_CODE_BASE must be 0x00000000 in default mode"
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# endif
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#endif
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/*****************************************************************************
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* External references
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*****************************************************************************/
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@ -331,7 +304,7 @@
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/* Zero IVR 31:16 */
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str \value, [\eicbase, STR71X_EIC_IVR_OFFSET]
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str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
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/* Set up the loop to initialize each SIR register. Start
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* with IRQ number 0 and SIR0
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@ -435,9 +408,9 @@ eicloop:
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*
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* Description:
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* Interrrupt vector table. This must be located at the beginning
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* of the memory space (at CONFIG_CODE_BASE). The first entry in
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* the vector table is the reset vector and this is the code that
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* will execute whn the processor is reset.
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* of the memory space (at the beginning FLASH which will be mapped to
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* address 0x00000000). The first entry in the vector table is the reset
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* vector and this is the code that will execute whn the processor is reset.
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*
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*****************************************************************************/
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@ -125,6 +125,7 @@
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#define STR71X_TIMERCR1_PWMI (0x4000) /* Bit 14: Pulse width modulation input */
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#define STR71X_TIMERCR1_EN (0x8000) /* Bit 15: Timer count enable */
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#define STR71X_TIMERCR2_DIVMASK (0x00ff) /* Bits 0-7: Timer prescaler value */
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#define STR71X_TIMERCR2_OCBIE (0x0800) /* Bit 11: Output capture B enable */
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#define STR71X_TIMERCR2_ICBIE (0x1000) /* Bit 12: Input capture B enable */
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#define STR71X_TIMERCR2_TOIE (0x2000) /* Bit 13: Timer overflow enable */
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@ -0,0 +1,217 @@
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/****************************************************************************
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* arch/arm/src/str71x/str71x_timerisr.c
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*
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* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "clock_internal.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Calculate the value of PCLK2 from settings in board.h.
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*
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* Example:
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* STR71X_RCCU_MAIN_OSC = 4MHz
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* CLK2 = 4MHz (not divided by 2)
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* PLL1OUT = 16 * CLK2 / 2 = 32MHz
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* CLK3 = 32MHz
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* RCLK = 32MHz
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* PCLK2 = 32MHz / 1 = 32MHz
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*/
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#ifdef STR71X_PLL1IN_DIV2 /* Input may be divided by 2 */
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# define CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is input to PLL1 */
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#else
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# define CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is input to PLL1 */
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#endif
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/* PLL1OUT derives from CLK2 */
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#define PLL1OUT (STR71X_PLL1OUT_MUL * CLK2 / STR71X_PLL1OUT_DIV)
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#define CLK3 PLL1OUT /* CLK3 hard coded to be PLL1OUT */
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#define RCLK CLK3 /* RCLK hard coded to be CLK3 */
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#define PCLK2 (RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* The best accuracy would be obtained by using the largest value in the
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* the output compare register (OCAR), i.e., 0xffff = 65,535:
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*/
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#define MAX_OCAR 65535
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/* In this case, the desired, maximum clocking would be MAX_TIM0CLK. For
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* example if CLK_TCK is the default of 100Hz, then the ideal clocking for
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* timer0 would be 6,553,500 */
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#define MAX_TIM0CLK (MAX_OCAR * CLK_TCK)
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/* The best divider then would be the one that reduces PCLK2 to MAX_TIM0CLK.
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* Note that the following calculation forces an integer divisor to the next
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* integer above the optimal. So, for example, if MAX_TIM0CLK is 6,553,500
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* and PCLK2 is 32MHz, then ideal PCLK2_DIVIDER would be 4.88 but 5 is used
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* instead. The value 5 would give an actual TIM0CLK of 6,400,000, less
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* than the maximum.
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*/
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#if PCLK2 > MAX_TIM0CLK
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# define PCLK2_DIVIDER (((PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK)
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#else
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# define PCLK2_DIVIDER (1)
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#endif
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#if PCLK2_DIVIDER > 255
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# error "PCLK2 is too fast for any divisor"
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#endif
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/* Then we can get the actual OCAR value from the selected divider value.
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* For example, if PCLK2 is 32MHz and PCLK2_DIVIDER is 5, then the actual
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* TIM0CLK would 6,4000,000 and the final OCAR_VALUE would be 64,000.
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*/
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#define ACTUAL_TIM0CLK (PCLK2 / PCLK2_DIVIDER)
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#define OCAR_VALUE (ACTUAL_TIM0CLK / CLK_TCK)
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#if OCAR_VALUE > 65535
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# error "PCLK2 is too fast for the configured CLK_TCK"
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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int up_timerisr(int irq, uint32 *regs)
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{
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/* Process timer interrupt */
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sched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Function: up_timerinit
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timerinit(void)
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{
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uint16 cr1;
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uint16 cr2;
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/* Make sure that timer0 is disabled */
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putreg16(0x0000, STR71X_TIMER0_CR1);
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putreg16(0x0000, STR71X_TIMER0_CR2);
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putreg16(0x0000, STR71X_TIMER0_SR);
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/* Start The TIM0 Counter */
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cr1 = STR71X_TIMERCR1_EN;
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putreg16(cr1, STR71X_TIMER0_CR1);
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/* Configure TIM0 so that it is clocked by the internal APB2 frequency (PCLK2)
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* divided by the above prescaler value (1) -- versus an external Clock.
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* -- Nothing to do because STR71X_TIMERCR1_ECKEN is already cleared.
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*
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*
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* Select a divisor to reduce the frequency of clocking. This must be
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* done so that the entire timer interval can fit in the 16-bit OCAR register.
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* (see the discussion above).
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*/
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cr2 = PCLK2_DIVIDER;
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putreg16(cr2, STR71X_TIMER0_CR2);
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/* Setup output compare A for desired interrupt frequency. Note that
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* the OCAE and OCBE bits are cleared and the pins are available for other
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* functions.
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*/
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putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
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putreg16(0, STR71X_TIMER0_CNTR);
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/* Enable TIM0 Output Compare A interrupt */
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cr2 |= STR71X_TIMERCR2_OCAIE;
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putreg16(cr2, STR71X_TIMER0_CR2);
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/* Set the IRQ interrupt priority */
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up_irqpriority(STR71X_IRQ_SYSTIMER, 1);
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/* Attach the timer interrupt vector */
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(void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
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/* And enable the timer interrupt */
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up_enable_irq(STR71X_IRQ_SYSTIMER);
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}
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@ -108,7 +108,7 @@ CONFIG_STR71X_BSPI1=n
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CONFIG_STR71X_HDLC=n
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CONFIG_STR71X_XTI=n
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CONFIG_STR71X_GPIO0=y
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CONFIG_STR71X_GPIO1=n
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CONFIG_STR71X_GPIO1=y
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CONFIG_STR71X_GPIO2=n
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CONFIG_STR71X_ADC12=n
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CONFIG_STR71X_CKOUT=n
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@ -82,15 +82,15 @@ void up_buttoninit(void)
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/* Configure the GPIO pins as inputs */
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reg16 = getreg16(STR71X_GPIO1_PC0);
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reg16 |= STR71X_BOTHBUTTONS_GPIO1
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reg16 |= STR71X_BOTHBUTTONS_GPIO1;
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putreg16(reg16, STR71X_GPIO1_PC0);
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reg16 = getreg16(STR71X_GPIO1_PC1);
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reg16 &= ~STR71X_BOTHBUTTONS_GPIO1
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reg16 &= ~STR71X_BOTHBUTTONS_GPIO1;
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putreg16(reg16, STR71X_GPIO1_PC1);
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reg16 = getreg16(STR71X_GPIO1_PC2);
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reg16 &= ~STR71X_BOTHBUTTONS_GPIO1
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reg16 &= ~STR71X_BOTHBUTTONS_GPIO1;
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putreg16(reg16, STR71X_GPIO1_PC2);
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}
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@ -106,21 +106,21 @@ void up_ledinit(void)
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/* Set normal function output */
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reg16 = getreg16(STR71X_GPIO1_PC0);
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reg16 |= STR71X_LEDGPIO1_BITS
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reg16 |= STR71X_LEDGPIO1_BITS;
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putreg16(reg16, STR71X_GPIO1_PC0);
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reg16 = getreg16(STR71X_GPIO1_PC1);
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reg16 &= ~STR71X_LEDGPIO1_BITS
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reg16 &= ~STR71X_LEDGPIO1_BITS;
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putreg16(reg16, STR71X_GPIO1_PC1);
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reg16 = getreg16(STR71X_GPIO1_PC2);
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reg16 |= STR71X_LEDGPIO1_BITS
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reg16 |= STR71X_LEDGPIO1_BITS;
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putreg16(reg16, STR71X_GPIO1_PC2);
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/* Clear the LEDs (1 clears; 0 sets) */
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reg16 = getreg16(STR71X_GPIO1_PD);
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reg16 |= STR71X_LEDGPIO1_BITS
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reg16 |= STR71X_LEDGPIO1_BITS;
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putreg16(reg16, STR71X_GPIO1_PD);
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}
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