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More progress on the STM32 OTG FS device driver 

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4558 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-04-05 14:12:41 +00:00
parent 9f8d4d940a
commit dcbed0e5f8
7 changed files with 320 additions and 227 deletions
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6
misc/pascal/ChangeLog
View File

@ -22,7 +22,7 @@ pascal-2.0 2009-12-21 Gregory Nutt <spudmonkey@racsa.co.cr>
stdbool.h. This change was necessary for compatibility
with NuttX-5.0 (any beyond).
pascal-3.0 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
pascal-3.0 2010-05-15 Gregory Nutt <spudmonkey@racsa.co.cr>
* nuttx/: The Pascal add-on module now installs and builds under the
apps/interpreters directory. This means that the pascal-3.0 module is
@ -31,7 +31,7 @@ pascal-3.0 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
pascal-3.1 2012-xx-xx Gregory Nutt <gnutt@nuttx.org>
* nuttx/Makefile: If DIRLINK is defined, then INCDIR is not setup
correctly and the build fails. The value of INCDIR must be
* nuttx/Makefile: If DIRLINK is defined, then INCDIR was not setup
correctly and the build failed. The value of INCDIR must be
initialized unconditionally.

2
nuttx/Documentation/NuttX.html
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@ -2912,7 +2912,7 @@ NxWidgets-1.0 2012-03-22 Gregory Nutt &lt;gnutt@nuttx.org&gt;
* This is the initial release of NxWidgets, the C++ graphics package for NuttX.
pascal-1.0 2011-05-15 Gregory Nutt &lt;gnutt@nuttx.org&gt;
pascal-3.0 2011-05-15 Gregory Nutt &lt;gnutt@nuttx.org&gt;
* nuttx/: The Pascal add-on module now installs and builds under the
apps/interpreters directory. This means that the pascal-2.1 module is

41
nuttx/arch/arm/src/stm32/chip/stm32_usbotgfs.h → nuttx/arch/arm/src/stm32/chip/stm32_otgfs.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32_usbotgfs.h
* arch/arm/src/stm32/chip/stm32_otgfs.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H
/****************************************************************************************************
* Included Files
@ -83,10 +83,10 @@
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
#define STM32_OTGFS_HCCHAR_OFFSET 0x0000 /* Host channel characteristics register */
#define STM32_OTGFS_HCINT_OFFSET 0x0008 /* Host channel interrupt register */
#define STM32_OTGFS_HCINTMSK_OFFSET 0x000c /* Host channel interrupt mask register */
#define STM32_OTGFS_HCTSIZ_OFFSET 0x0010 /* Host channel interrupt register */
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */
@ -142,10 +142,10 @@
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGFS_DIEPCTL_OFFSET 0x0900 /* Device endpoint control register */
#define STM32_OTGFS_DIEPINT_OFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTGFS_DIEPTSIZ_OFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32_OTGFS_DTXFSTS_OFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */
@ -171,9 +171,9 @@
#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 transfer size register */
#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 transfer size register */
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL_OFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTGFS_DOEPINT_OFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32_OTGFS_DOEP_OFFSET(n) 0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */
@ -304,10 +304,6 @@
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
#define STM32_OTGFS_DIEPCTL (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET)
#define STM32_OTGFS_DIEPINT (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET)
#define STM32_OTGFS_DIEPTSIZ (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET)
#define STM32_OTGFS_DTXFSTS (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET)
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
#define STM32_OTGFS_DIEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET)
@ -497,7 +493,7 @@
# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
/* Bits 21-31: Reserved, must be kept at reset value.
/* Bits 21-31: Reserved, must be kept at reset value */
/* Receive status debug read/OTG status read and pop registers (device mode) */
#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
@ -519,7 +515,7 @@
# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-31: Reserved, must be kept at reset value.
/* Bits 25-31: Reserved, must be kept at reset value */
/* Receive FIFO size register */
#define OTGFS_GRXFSIZ_MASK (0xffff)
@ -717,7 +713,6 @@
# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT)
/* Bit 31 Reserved, must be kept at reset value */
/* Device-mode control and status registers */
/* Device configuration register */
@ -734,7 +729,7 @@
# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTGFS_DCFG_PFIVL_85PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bits 13-31 Reserved, must be kept at reset value */
/* Device control register */
@ -996,4 +991,4 @@
#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
/* Bits 5-31: Reserved, must be kept at reset value */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H */

93
nuttx/arch/arm/src/stm32/stm32_otgfs.h Normal file
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@ -0,0 +1,93 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_otgfs.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H
#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "stm32.h"
#include "chip/stm32_otgfs.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGFS_PRI
# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver
* is used. This function is called whenever the USB enters or leaves suspend
* mode. This is an opportunity for the board logic to shutdown clocks, power,
* etc. while the USB is suspended.
*
************************************************************************************/
EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */

365
nuttx/arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -59,7 +59,9 @@
#include "up_arch.h"
#include "up_internal.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_OTGFSDEV)
#include "stm32_otgfs.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_OTGFS)
/*******************************************************************************
* Definitions
@ -216,6 +218,16 @@
#define stm32_rqempty(ep) ((ep)->head == NULL)
#define stm32_rqpeek(ep) ((ep)->head)
/* Standard stuff **************************************************************/
#ifndef MIN
# define MIN(a,b) ((a) < (b) ? (a) : (b))
#endif
#ifndef MAX
# define MAX(a,b) ((a) > (b) ? (a) : (b))
#endif
/*******************************************************************************
* Private Types
*******************************************************************************/
@ -224,10 +236,10 @@
enum stm32_devstate_e
{
DEVSTATE_DEFAULT = 0,
DEVSTATE_ADDRESSED
DEVSTATE_CONFIGURED
DEVSTATE_SUSPENDED
DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state */
DEVSTATE_ADDRESSED, /* Device address has been assigned, not configured */
DEVSTATE_CONFIGURED, /* Address assigned and configured */
DEVSTATE_SUSPENDED, /* Suspended */
};
/* Endpoint 0 states */
@ -282,11 +294,13 @@ struct stm32_ep_s
struct stm32_req_s *head; /* Request list for this endpoint */
struct stm32_req_s *tail;
uint8_t epphy; /* Physical EP address */
uint8_t eptype:2; /* Endpoint type */
uint8_t configured:1; /* 1: Endpoint has been configured */
uint8_t active:1; /* 1: A request is being processed */
uint8_t stalled:1; /* 1: Endpoint is stalled */
uint8_t isin:1; /* 1: IN Endpoint */
uint8_t odd:1; /* 1: Odd frame */
uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */
};
/* This structure retains the state of the USB device controller */
@ -352,14 +366,13 @@ static bool stm32_addlast(FAR struct stm32_ep_s *privep,
/* Low level data transfers and request operations *****************************/
static inline void stm32_ep0xfer(uint8_t epphy, uint8_t *data, uint32_t nbytes);
static void stm32_ep0read(FAR uint8_t *dest, uint16_t len)
static void stm32_ep0read(FAR uint8_t *dest, uint16_t len);
static void stm32_flushep(struct stm32_ep_s *privep);
static inline void stm32_abortrequest(struct stm32_ep_s *privep,
struct stm32_req_s *privreq, int16_t result);
static void stm32_reqcomplete(struct stm32_ep_s *privep,
struct stm32_req_s *privreq, int16_t result);
static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result);
static int stm32_wrrequest(struct stm32_usbdev_s *priv,
struct stm32_ep_s *privep);
@ -398,6 +411,14 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv,
uint8_t epno);
static inline void stm32_epoutinterrupt(FAR struct stm32_usbdev_s *priv);
/* Other second level interrupt processing */
static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv);
#ifdef CONFIG_USBDEV_ISOCHRONOUS
static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv);
static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv);
#endif
/* First level interrupt processing */
static int stm32_usbinterrupt(int irq, FAR void *context);
@ -421,10 +442,8 @@ static int stm32_epcancel(FAR struct usbdev_ep_s *ep,
/* Stall handling */
static int stm32_epsetstall(FAR struct stm32_usbdev_s *priv,
FAR struct stm32_ep_s *privep);
static int stm32_epclrstall(FAR struct stm32_usbdev_s *priv,
FAR struct stm32_ep_s *privep)
static int stm32_epsetstall(FAR struct stm32_ep_s *privep);
static int stm32_epclrstall(FAR struct stm32_ep_s *privep);
static int stm32_epstall(FAR struct usbdev_ep_s *ep, bool resume);
static void stm32_ep0stall(FAR struct stm32_usbdev_s *priv);
@ -444,9 +463,8 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable);
/* Initialization **************************************************************/
static int stm32_flushtxfifo(FAR struct stm32_usbdev_s *priv,
uint32_t txfnum);
static int stm32_flushrxfifo(FAR struct stm32_usbdev_s *priv);
static int stm32_flushtxfifo(uint32_t txfnum);
static int stm32_flushrxfifo(void);
static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv);
static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv);
@ -670,7 +688,7 @@ static void stm32_ep0read(FAR uint8_t *dest, uint16_t len)
/* Read 1 x 32-bits of EP0 packet data */
data.w = stm32_getreg(fifo);
data.w = stm32_getreg(regaddr);
/* Write 4 x 8-bits of EP0 packet data */
@ -693,11 +711,11 @@ static void stm32_flushep(struct stm32_ep_s *privep)
{
if (privep->isin)
{
stm32_flushtxfifo(priv, OTGFS_GRSTCTL_TXFNUM_D(privep->epphy);
stm32_flushtxfifo(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy));
}
else
{
stm32_flushrxfifo(priv);
stm32_flushrxfifo();
}
}
@ -732,9 +750,15 @@ static inline void stm32_abortrequest(struct stm32_ep_s *privep,
*
*******************************************************************************/
static void stm32_reqcomplete(struct stm32_ep_s *privep,
struct stm32_req_s *privreq, int16_t result)
static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result)
{
FAR struct stm32_req_s *privreq;
/* Remove the request at the head of the request list */
privreq = stm32_remfirst(privep);
DEBUGASSERT(privreq != NULL);
/* If endpoint 0, temporarily reflect the state of protocol stalled
* in the callback.
*/
@ -778,7 +802,7 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
* there is no TX transfer in progress.
*/
privep->txbusy = false;
privep->active = false;
/* Check the request from the head of the endpoint request queue */
@ -796,15 +820,13 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
epno = USB_EPNO(privep->ep.eplog);
ullvdbg("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
epno, privreq, privreq->req.len, privreq->req.xfrd, privep->zlp);
/* Get the number of bytes left to be sent in the packet */
bytesleft = privreq->req.len - privreq->req.xfrd;
nbytes = bytesleft;
#warning "REVISIT: If the EP supports double buffering, then we can do better"
/* Send the next packet */
if (nbytes > 0)
@ -813,7 +835,7 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
* the request.
*/
privep->txnullpkt = 0;
privep->zlp = 0;
if (nbytes >= privep->ep.maxpacket)
{
nbytes = privep->ep.maxpacket;
@ -826,7 +848,7 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
if (bytesleft == privep->ep.maxpacket &&
(privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
{
privep->txnullpkt = 1;
privep->zlp = 1;
}
}
}
@ -846,10 +868,10 @@ static int stm32_wrrequest(struct stm32_usbdev_s *priv, struct stm32_ep_s *prive
* then we are finished with the transfer
*/
if (bytesleft == 0 && !privep->txnullpkt)
if (bytesleft == 0 && !privep->zlp)
{
usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
privep->txnullpkt = 0;
privep->zlp = 0;
stm32_reqcomplete(privep, OK);
privep->active = false;
}
@ -954,11 +976,9 @@ static void stm32_cancelrequests(struct stm32_ep_s *privep, int16_t status)
while (!stm32_rqempty(privep))
{
// FIXME: the entry at the head should be sync'd with the DTD
// FIXME: only report the error status if the transfer hasn't completed
usbtrace(TRACE_COMPLETE(privep->epphy),
(stm32_rqpeek(privep))->req.xfrd);
stm32_reqcomplete(privep, stm32_remfirst(privep), status);
stm32_reqcomplete(privep, status);
}
}
@ -976,7 +996,6 @@ static struct stm32_ep_s *stm32_epfindbyaddr(struct stm32_usbdev_s *priv,
{
struct stm32_ep_s *privep;
uint8_t epphy = USB_EPNO(eplog);
int i;
if (epphy >= STM32_NENDPOINTS)
{
@ -1051,10 +1070,10 @@ static int stm32_dispatchrequest(struct stm32_usbdev_s *priv,
static void stm32_ep0configure(struct stm32_usbdev_s *priv)
{
/* Enable ep0 IN and ep0 OUT */
#waning "Missing Logic"
#warning "Missing Logic"
/* Enable EP0 */
#waning "Missing Logic"
#warning "Missing Logic"
}
/*******************************************************************************
@ -1196,6 +1215,7 @@ bool stm32_epcomplete(struct stm32_usbdev_s *priv, uint8_t epphy)
{
struct stm32_ep_s *privep = &priv->epin[epphy];
struct stm32_req_s *privreq = privep->head;
int xfrd;
if (privreq == NULL) /* This shouldn't really happen */
{
@ -1206,11 +1226,12 @@ bool stm32_epcomplete(struct stm32_usbdev_s *priv, uint8_t epphy)
else
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), 0);
|
}
return true;
}
int xfrd = dtd->xfer_len - (dtd->config >> 16);
/* Get the number of bytes transferred */
#warning "Missing logic"
privreq->req.xfrd += xfrd;
@ -1232,24 +1253,20 @@ bool stm32_epcomplete(struct stm32_usbdev_s *priv, uint8_t epphy)
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTCOMPLETE), complete);
}
/* If the transfer is complete, then dequeue and progress any further queued requests */
if (complete)
{
privreq = stm32_remfirst (privep);
}
if (!stm32_rqempty(privep))
{
stm32_???(privep);
}
/* Now it's safe to call the completion callback as it may well submit a new request */
/* Handle the transfer completion by returning the request to class driver */
if (complete)
{
usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
stm32_reqcomplete(privep, privreq, OK);
stm32_reqcomplete(privep, OK);
/* If the transfer is complete, process the next request in the request list */
if (!stm32_rqempty(privep))
{
/* Process the next request in the request list */
#warning "Missing logic"
}
}
return complete;
@ -1265,7 +1282,7 @@ bool stm32_epcomplete(struct stm32_usbdev_s *priv, uint8_t epphy)
static inline void stm32_runtestmode(FAR struct stm32_usbdev_s *priv)
{
uint32_t regval = stm32_gettreg(TM32_OTGFS_DCTL);
uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL);
regval &= OTGFS_DCTL_TCTL_MASK;
regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT;
stm32_putreg(regval , STM32_OTGFS_DCTL);
@ -1285,14 +1302,12 @@ static inline void stm32_runtestmode(FAR struct stm32_usbdev_s *priv)
static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
{
FAR struct stm32_ep_s *privep;
FAR struct stm32_ep_s *privep = &priv->epin[epno];
/* Endpoint 0 is a special case. */
if (epno == 0)
{
privep = &priv->epin[EP0];
/* In the EP0STATE_DATA_IN state, we are sending data from request
* buffer. In that case, we must continue the request processing.
*/
@ -1331,7 +1346,6 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
(void)stm32_wrrequest(priv, privep);
}
return OK;
}
/*******************************************************************************
@ -1380,7 +1394,7 @@ static inline void stm32_epininterrupt(FAR struct stm32_usbdev_s *priv)
*/
empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK);
if ((empty & OTGFS_DIEPEMPMSK(epno)) != ))
if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0)
{
mask |= OTGFS_DIEPINT_TXFE;
}
@ -1452,8 +1466,6 @@ static inline void stm32_epininterrupt(FAR struct stm32_usbdev_s *priv)
epno++;
daint >>= 1;
}
return 1;
}
/*******************************************************************************
@ -1467,46 +1479,27 @@ static inline void stm32_epininterrupt(FAR struct stm32_usbdev_s *priv)
static inline void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address)
{
uint32_t regval;
uint8_t address;
if ((req->index == 0) && (req->len == 0))
/* Set the device address in the DCFG register */
regval = stm32_getreg(STM32_OTGFS_DCFG);
regval &= ~OTGFS_DCFG_DAD_MASK;
regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT);
stm32_putreg(regval, STM32_OTGFS_DCFG);
/* Are we now addressed? (i.e., do we have a non-NULL device
* address?)
*/
if (address != 0)
{
if (priv->devstate == DEVSTATE_CONFIGURED)
{
stm32_ep0stall(priv, req);
}
else
{
/* Set the device address in the DCFG register */
regval = stm32_getreg(STM32_OTGFS_DCFG);
regval &= ~OTGFS_DCFG_DAD_MASK;
regval |= (address << OTGFS_DCFG_DAD_SHIFT);
stm32_putreg(regval, STM32_OTGFS_DCFG);
/* Send a null packet in response */
stm32_ep0nullpacket(priv);
/* Are we now addressed? (i.e., do we have a non-NULL device
* address?
*/
if (address != 0)
{
priv->devstate = DEVSTATE_ADDRESSED;
priv->addressed = true;
}
else
{
priv->devstate = DEVSTATE_DEFAULT;
priv->addressed = false;
}
}
priv->devstate = DEVSTATE_ADDRESSED;
priv->addressed = true;
}
else
{
stm32_ep0stall(priv, req);
priv->devstate = DEVSTATE_DEFAULT;
priv->addressed = false;
}
}
@ -1551,7 +1544,7 @@ static inline void stm32_testmode(FAR struct stm32_usbdev_s *priv, uint16_t inde
default:
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode);
priv->dotest = false;
priv->testmode = OTGFS_TESTMODE_DISABLED
priv->testmode = OTGFS_TESTMODE_DISABLED;
priv->stalled = true;
}
@ -1682,11 +1675,11 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
if (priv->addressed != 0 && ctrlreq->len == 0)
{
uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK;
if (recipient == USB_REQ_RECIPIENT_ENDPOINT
if (recipient == USB_REQ_RECIPIENT_ENDPOINT &&
ctrlreq->value == USB_FEATURE_ENDPOINTHALT &&
(privep = stm32_epfindbyaddr(priv, ctrlreq->index)) != NULL)
{
stm32_epclrstall(priv, &privep->ep);
stm32_epclrstall(privep);
stm32_ep0nullpacket(priv);
priv->ep0state = EP0STATE_NAK_IN;
}
@ -1723,15 +1716,15 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
if (priv->addressed != 0 && ctrlreq->len == 0)
{
uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK;
if (recipient == USB_REQ_RECIPIENT_ENDPOINT
if (recipient == USB_REQ_RECIPIENT_ENDPOINT &&
ctrlreq->value == USB_FEATURE_ENDPOINTHALT &&
(privep = stm32_epfindbyaddr(priv, ctrlreq->index)) != NULL)
{
stm32_epsetstall(priv, privep);
stm32_epsetstall(privep);
stm32_ep0nullpacket(priv);
priv->ep0state = EP0STATE_NAK_IN;
}
else if (recipient == USB_REQ_RECIPIENT_DEVICE
else if (recipient == USB_REQ_RECIPIENT_DEVICE &&
ctrlreq->value == USB_FEATURE_REMOTEWAKEUP)
{
priv->wakeup = 1;
@ -1739,7 +1732,7 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
}
else if (recipient == USB_REQ_RECIPIENT_DEVICE &&
ctrlreq->value == USB_FEATURE_TESTMODE &&
((req->index & 0xff) == 0))
((ctrlreq->index & 0xff) == 0))
{
stm32_testmode(priv, ctrlreq->index);
}
@ -1775,13 +1768,15 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
if ((ctrlreq->type &USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
ctrlreq->index == 0 &&
ctrlreq->len == 0 &&
ctrlreq->value < 128)
ctrlreq->value < 128 &&
priv->devstate != DEVSTATE_CONFIGURED)
{
/* Save the address. We cannot actually change to the next address until
* the completion of the status phase.
*/
stm32_setaddress(priv, (uint16_t)priv->ctrlreq->value[0]);
stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]);
stm32_ep0nullpacket(priv);
priv->ep0state = EP0STATE_NAK_IN;
}
else
@ -1861,7 +1856,7 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
{
/* Give the configuration to the class driver */
ret = stm32_dispatchrequest(priv, &priv->ctrlreq);
int ret = stm32_dispatchrequest(priv, &priv->ctrlreq);
/* If the class driver accepted the configuration, then mark the
* device state as configured (or not, depending on the
@ -1870,7 +1865,7 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
if (ret == OK)
{
uint8_t cfg = (uint8_t)req->value;
uint8_t cfg = (uint8_t)ctrlreq->value;
if (cfg != 0)
{
priv->devstate = DEVSTATE_CONFIGURED;
@ -1943,7 +1938,6 @@ static inline void stm32_stdrequest(struct stm32_usbdev_s *priv,
static inline void stm32_ep0setup(struct stm32_usbdev_s *priv)
{
FAR struct stm32_ep_s *privep;
struct stm32_ctrlreq_s ctrlreq;
/* Terminate any pending requests - since all DTDs will have been retired
@ -2050,7 +2044,6 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno)
{
(void)stm32_rdrequest(priv, &priv->epout[epno]);
}
return OK;
}
/*******************************************************************************
@ -2102,7 +2095,7 @@ static inline void stm32_epoutinterrupt(FAR struct stm32_usbdev_s *priv)
/* Handle the RX transer data ready event */
stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno)
stm32_epout(priv, epno);
}
/* Endpoint disabled interrupt */
@ -2132,10 +2125,62 @@ static inline void stm32_epoutinterrupt(FAR struct stm32_usbdev_s *priv)
epno++;
daint >>= 1;
}
return 1;
}
/*******************************************************************************
* Name: stm32_isocininterrupt
*
* Description:
* Enumeration done interrupt
*
*******************************************************************************/
static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv)
{
uint32_t regval;
/* Activate EP0 */
stm32_ep0activate(priv);
/* Set USB turn-around time for the full speed device with internal PHY interface. */
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);
regval &= ~OTGFS_GUSBCFG_TRDT_MASK;
regval |= OTGFS_GUSBCFG_TRDT(5);
stm32_putreg(regval, STM32_OTGFS_GUSBCFG);
}
/*******************************************************************************
* Name: stm32_isocininterrupt
*
* Description:
* Incomplete isochronous IN transfer interrupt
*
*******************************************************************************/
#ifdef CONFIG_USBDEV_ISOCHRONOUS
static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv)
{
#warning "Missing logic"
}
#endif
/*******************************************************************************
* Name: stm32_isocoutinterrupt
*
* Description:
* Incomplete periodic transfer interrupt
*
*******************************************************************************/
#ifdef CONFIG_USBDEV_ISOCHRONOUS
static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
{
#warning "Missing logic"
}
#endif
/*******************************************************************************
* Name: stm32_usbinterrupt
*
@ -2241,14 +2286,17 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval);
(void)stm32_enuminterrupt(priv);
stm32_putreg(OTGFS_GINT_ENUMDNE, STM32_OTGFS_GINTSTS);
}
/* Incomplete isochronous IN transfer interrupt */
#ifdef CONFIG_USBDEV_ISOCHRONOUS
if ((regval & OTGFS_GINT_IISOIXFR) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval);
(void)stm32_isocininterrupt(priv);
stm32_isocininterrupt(priv);
stm32_putreg(OTGFS_GINT_IISOIXFR, STM32_OTGFS_GINTSTS);
}
/* Incomplete periodic transfer interrupt*/
@ -2256,8 +2304,10 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_IPXFR) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IPXFR), (uint16_t)regval);
(void)stm32_isocoutinterrupt(priv);
stm32_isocoutinterrupt(priv);
stm32_putreg(OTGFS_GINT_IPXFR, STM32_OTGFS_GINTSTS);
}
#endif
/* Session request/new session detected interrupt */
@ -2305,13 +2355,14 @@ static int stm32_epconfigure(FAR struct usbdev_ep_s *ep,
bool last)
{
FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
uint16_t maxsize;
usbtrace(TRACE_EPCONFIGURE, privep->epphy);
DEBUGASSERT(desc->addr == ep->eplog);
/* Initialise EP capabilities */
uint16_t maxsize = GETUINT16(desc->mxpacketsize);
maxsize = GETUINT16(desc->mxpacketsize);
#warning "Missing Logic"
/* Setup Endpoint Control Register */
@ -2626,8 +2677,7 @@ static int stm32_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
*
*******************************************************************************/
static int stm32_epsetstall(FAR struct stm32_usbdev_s *priv,
FAR struct stm32_ep_s *privep)
static int stm32_epsetstall(FAR struct stm32_ep_s *privep)
{
uint32_t regaddr;
uint32_t regval;
@ -2688,8 +2738,7 @@ static int stm32_epsetstall(FAR struct stm32_usbdev_s *priv,
*
*******************************************************************************/
static int stm32_epclrstall(FAR struct stm32_usbdev_s *priv,
FAR struct stm32_ep_s *privep)
static int stm32_epclrstall(FAR struct stm32_ep_s *privep)
{
uint32_t regaddr;
uint32_t regval;
@ -2759,11 +2808,11 @@ static int stm32_epstall(FAR struct usbdev_ep_s *ep, bool resume)
flags = irqsave();
if (resume)
{
ret = stm32_epclrstall(priv, privep);
ret = stm32_epclrstall(privep);
}
else
{
ret = stm32_epsetstall(priv, privep);
ret = stm32_epsetstall(privep);
}
irqrestore(flags);
@ -2780,8 +2829,9 @@ static int stm32_epstall(FAR struct usbdev_ep_s *ep, bool resume)
static void stm32_ep0stall(FAR struct stm32_usbdev_s *priv)
{
stm32_epsetstall(priv, &priv->epin[EP0]);
stm32_epsetstall(priv, &priv->epout[EP0]);
stm32_epsetstall(&priv->epin[EP0]);
stm32_epsetstall(&priv->epout[EP0]);
priv->stalled = true;
stm32_ep0outstart(priv);
}
@ -2953,6 +3003,7 @@ static int stm32_getframe(struct usbdev_s *dev)
usbtrace(TRACE_DEVGETFRAME, 0);
#warning "Missing logic"
return 0;
}
/*******************************************************************************
@ -3034,7 +3085,7 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
*
*******************************************************************************/
static int stm32_flushtxfifo(FAR struct stm32_usbdev_s *priv, uint32_t txfnum)
static int stm32_flushtxfifo(uint32_t txfnum)
{
uint32_t regval;
uint32_t timeout;
@ -3069,7 +3120,7 @@ static int stm32_flushtxfifo(FAR struct stm32_usbdev_s *priv, uint32_t txfnum)
*
*******************************************************************************/
static int stm32_flushrxfifo(FAR struct stm32_usbdev_s *priv)
static int stm32_flushrxfifo(void)
{
uint32_t regval;
uint32_t timeout;
@ -3106,6 +3157,7 @@ static int stm32_flushrxfifo(FAR struct stm32_usbdev_s *priv)
static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv)
{
FAR struct stm32_ep_s *privep;
int i;
/* Initialize the device state structure */
@ -3118,8 +3170,6 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv)
for (i = 0; i < STM32_NENDPOINTS; i++)
{
uint32_t bit = 1 << i;
/* Set endpoint operations, reference to driver structure (not
* really necessary because there is only one controller), and
* the physical endpoint number (which is just the index to the
@ -3148,8 +3198,6 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv)
for (i = 0; i < STM32_NENDPOINTS; i++)
{
uint32_t bit = 1 << i;
/* Set endpoint operations, reference to driver structure (not
* really necessary because there is only one controller), and
* the physical endpoint number (which is just the index to the
@ -3189,7 +3237,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
uint32_t address;
int i;
/* At startup the core is in FS mode.
/* At startup the core is in FS mode. */
/* Disable the USB global interrupt by clearing GINTMSK in the global OTG
* FS AHB configuration register.
@ -3218,7 +3266,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
for (timeout = 0; timeout < STM32_READY_DELAY; timeout++)
{
regval = stm32_getreg(STM32_OTGFS_GRSTCTL);
if ((reval & OTGFS_GRSTCTL_CSRST) == 0)
if ((regval & OTGFS_GRSTCTL_CSRST) == 0)
{
break;
}
@ -3230,7 +3278,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Deactivate the power down */
regval = OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | OTGFS_GCCFG_VBUSBSEN
regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | OTGFS_GCCFG_VBUSBSEN);
#ifndef CONFIG_USBDEV_VBUSSENSING
regval |= OTGFS_GCCFG_NOVBUSSENS;
#endif
@ -3256,14 +3304,14 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Device configuration register */
regval = stm32_getreg(STM32_OTGFS_DCFG);
regval &= ~OTGFS_DCFG_PFIVL_MASK
regval &= ~OTGFS_DCFG_PFIVL_MASK;
regval |= OTGFS_DCFG_PFIVL_80PCT;
stm32_putreg(regval, STM32_OTGFS_DCFG);
/* Set full speed phy */
regval = stm32_getreg(STM32_OTGFS_DCFG);
regval &= ~OTGFS_DCFG_DSPD_MASK
regval &= ~OTGFS_DCFG_DSPD_MASK;
regval |= OTGFS_DCFG_DSPD_FS;
stm32_putreg(regval, STM32_OTGFS_DCFG);
@ -3273,7 +3321,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* EP0 TX */
address = CONFIG_USBDEV_RXFIFO_SIZE
address = CONFIG_USBDEV_RXFIFO_SIZE;
regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) ||
(CONFIG_USBDEV_EP0_TXFIFO_SIZE << OTGFS_DIEPTXF0_TX0FSA_SHIFT);
stm32_putreg(regval, STM32_OTGFS_DIEPTXF0);
@ -3283,7 +3331,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
address += CONFIG_USBDEV_EP0_TXFIFO_SIZE;
regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) ||
(CONFIG_USBDEV_EP1_TXFIFO_SIZE << OTGFS_DIEPTXF_INEPTXFD_SHIFT);
stm32_putreg(regval, STM32_OTGFS_DIEPTXF);
stm32_putreg(regval, STM32_OTGFS_DIEPTXF1);
/* EP2 TX */
@ -3301,8 +3349,8 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Flush the FIFOs */
stm32_flushtxfifo(priv, OTGFS_GRSTCTL_TXFNUM_DALL);
stm32_flushrxfifo(priv);
stm32_flushtxfifo(OTGFS_GRSTCTL_TXFNUM_DALL);
stm32_flushrxfifo();
/* Clear all pending Device Interrupts */
@ -3373,8 +3421,11 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Enable the interrupts in the INTMSK */
regval = (OTGFS_GINT_RXFLVL | OTGFS_GINT_USBSUSP | OTGFS_GINT_ENUMDNE |
OTGFS_GINT_IEP | OTGFS_GINT_OEP | OTGFS_GINT_IISOIXFR |
OTGFS_GINT_IPXFR | regval);
OTGFS_GINT_IEP | OTGFS_GINT_OEP | regval);
#ifdef CONFIG_USBDEV_ISOCHRONOUS
regval |= (OTGFS_GINT_IISOIXFR | OTGFS_GINT_IPXFR);
#endif
#ifdef CONFIG_USBDEV_SOFINTERRUPT
regval |= OTGFS_GINT_SOF;
@ -3395,7 +3446,6 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
*/
stm32_putreg(OTGFS_GAHBCFG_GINTMSK, STM32_OTGFS_GAHBCFG);
return OK;
}
/*******************************************************************************
@ -3426,7 +3476,7 @@ void up_usbinitialize(void)
*/
FAR struct stm32_usbdev_s *priv = &g_otgfsdev;
int i;
int ret;
usbtrace(TRACE_DEVINIT, 0);
@ -3449,22 +3499,13 @@ void up_usbinitialize(void)
/* Uninitialize the hardware so that we know that we are starting from a
* known state. */
up_usbuninitialize(priv);
up_usbuninitialize();
/* Initialie the driver data structure */
stm32_swinitialize(priv);
/* Initialize the USB OTG core */
ret = stm32_hwinitialize(priv);
if (ret < 0)
{
udbg("stm32_hwinitialize failed\n", ret);
goto errout;
}
/* Attach and enable interrupts */
/* Attach the OTG FS interrupt handler */
ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt);
if (ret < 0)
@ -3473,6 +3514,10 @@ void up_usbinitialize(void)
goto errout;
}
/* Initialize the USB OTG core */
stm32_hwinitialize(priv);
/* Disconnect device */
stm32_pullup(&priv->usbdev, false);
@ -3487,7 +3532,7 @@ void up_usbinitialize(void)
/* Set the interrrupt priority */
up_prioritize_irq(STM32_IRQ_OTGFS, CONFIG_USB_PRI);
up_prioritize_irq(STM32_IRQ_OTGFS, CONFIG_OTGFS_PRI);
return;
errout:
@ -3525,19 +3570,15 @@ void up_usbuninitialize(void)
/* Disable and detach IRQs */
up_disable_irq(STM32_IRQ_USBOTG);
irq_detach(STM32_IRQ_USBOTG);
up_disable_irq(STM32_IRQ_OTGFS);
irq_detach(STM32_IRQ_OTGFS);
/* Reset the controller */
stm32_putreg (USBDEV_USBCMD_RST, STM32_USBDEV_USBCMD);
while (stm32_getreg (STM32_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
#warning "Missing logic"
;
/* Turn off USB power and clocking */
stm32_disableclock(CLKID_USBOTGAHBCLK);
stm32_disableclock CLKID_EVENTROUTERPCLK);
#warning "Missing logic"
irqrestore(flags);
}
@ -3588,7 +3629,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
{
/* Enable USB controller interrupts */
up_enable_irq(STM32_IRQ_USBOTG);
up_enable_irq(STM32_IRQ_OTGFS);
/* FIXME: nothing seems to call DEV_CONNECT(), but we need to set
* the RS bit to enable the controller. It kind of makes sense
@ -3632,7 +3673,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
/* Disable USB controller interrupts */
up_disable_irq(STM32_IRQ_USBOTG);
up_disable_irq(STM32_IRQ_OTGFS);
/* Unhook the driver */

20
nuttx/configs/stm3240g-eval/src/up_usbdev.c
View File

@ -79,30 +79,12 @@ void stm32_usbinitialize(void)
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32_OTGFS
stm32_configgpio(GPIO_USB_PULLUP);
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/************************************************************************************
* Name: stm32_usbpullup
*
* Description:
* If USB is supported and the board supports a pullup via GPIO (for USB software
* connect and disconnect), then the board software must provide stm32_pullup.
* See include/nuttx/usb/usbdev.h for additional description of this method.
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
* NULL.
*
************************************************************************************/
int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
{
usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
return OK;
}
/************************************************************************************
* Name: stm32_usbsuspend
*

20
nuttx/configs/stm32f4discovery/src/up_usbdev.c
View File

@ -79,30 +79,12 @@ void stm32_usbinitialize(void)
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32_OTGFS
stm32_configgpio(GPIO_USB_PULLUP);
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/************************************************************************************
* Name: stm32_usbpullup
*
* Description:
* If USB is supported and the board supports a pullup via GPIO (for USB software
* connect and disconnect), then the board software must provide stm32_pullup.
* See include/nuttx/usb/usbdev.h for additional description of this method.
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
* NULL.
*
************************************************************************************/
int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
{
usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
return OK;
}
/************************************************************************************
* Name: stm32_usbsuspend
*