STM32 IWDG watchdog works
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4619 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
26d6eea6cb
commit
d8d410ba2e
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@ -42,8 +42,10 @@
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/watchdog.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "stm32_rcc.h"
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@ -55,12 +57,39 @@
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The minimum frequency of the IWDG clock is:
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*
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* Fmin = Flsi / 256
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*
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* So the maximum delay (in milliseconds) is then:
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*
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* 1000 * IWDG_RLR_MAX / Fmin
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*
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* For example, if Flsi = 30Khz (the nominal, uncalibrathed value), then the
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* maximum delay is:
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*
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* Fmin = 117.1875
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* 1000 * 4095 / Fmin = 34,944 MSec
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*/
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#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256)
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#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN)
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/* Configuration ************************************************************/
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#ifndef CONFIG_STM32_IWDG_DEFTIMOUT
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# define CONFIG_STM32_IWDG_DEFTIMOUT 3000 /* Three seconds */
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# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
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#endif
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/* REVISIT: It appears that you can only setup the prescaler and reload
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* registers once. After that, the SR register's PVU and RVU bits never go
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* to zero. So we defer setting up these registers until the watchdog
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* is started, then refuse any further attempts to change timeout.
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*/
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#define CONFIG_STM32_IWDG_ONETIMESETUP 1
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/* Debug ********************************************************************/
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/* Non-standard debug that may be enabled just for testing the watchdog
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* driver. NOTE: that only lldbg types are used so that the output is
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@ -99,13 +128,15 @@ struct stm32_lowerhalf_s
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/* Register operations ******************************************************/
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#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG)
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static uint32_t stm32_getreg(uint32_t addr);
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static void stm32_putreg(uint32_t val, uint32_t addr);
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static uint16_t stm32_getreg(uint32_t addr);
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static void stm32_putreg(uint16_t val, uint32_t addr);
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#else
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# define stm32_getreg(addr) getreg16(addr)
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# define stm32_putreg(val,addr) putreg16(val,addr)
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#endif
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static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv);
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/* "Lower half" driver methods **********************************************/
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static int stm32_start(FAR struct watchdog_lowerhalf_s *lower);
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@ -223,6 +254,51 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
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}
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#endif
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/****************************************************************************
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* Name: stm32_setprescaler
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*
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* Description:
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* Set up the prescaler and reload values. This seems to be something
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* that can only be done one time.
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*
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* Input Parameters:
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* priv - A pointer the internal representation of the "lower-half"
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* driver state structure.
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* timeout - The new timeout value in millisecnds.
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*
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* Returned Values:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
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{
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/* Enable write access to IWDG_PR and IWDG_RLR registers */
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stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
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/* Wait for the PVU anrd RVU bit to be reset be hardware. These bits
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* were set the last time that the PR register was written and may not
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* yet be cleared.
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*/
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#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
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while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU|IWDG_SR_RVU)) != 0);
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#endif
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/* Set the prescaler */
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stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR);
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/* Set the reload value */
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stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR);
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/* Reload the counter (and disable write access) */
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stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
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}
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/****************************************************************************
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* Name: stm32_start
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*
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@ -230,7 +306,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
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* Start the watchdog timer, resetting the time to the current timeout,
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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@ -242,19 +318,33 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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wdvdbg("Entry: started=%d\n");
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DEBUGASSERT(priv);
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/* Reload IWDG counter */
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/* Have we already been started? */
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stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
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if (!priv->started)
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{
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/* REVISIT: It appears that you can only setup the prescaler and reload
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* registers once. After that, the SR register's PVU and RVU bits never go
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* to zero. So we defer setting up these registers until the watchdog
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* is started, then refuse any further attempts to change timeout.
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*/
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/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
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* If the "Hardware watchdog" feature is enabled through the device option
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* bits, the watchdog is automatically enabled at power-on.
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*/
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/* Set up prescaler and reload value for the selected timeout */
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stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR);
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priv->started = true;
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#ifdef CONFIG_STM32_IWDG_ONETIMESETUP
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stm32_setprescaler(priv);
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#endif
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/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
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* If the "Hardware watchdog" feature is enabled through the device option
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* bits, the watchdog is automatically enabled at power-on.
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*/
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stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR);
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priv->started = true;
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}
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return OK;
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}
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@ -265,7 +355,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
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* Stop the watchdog timer
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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@ -277,6 +367,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
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{
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/* There is no way to disable the IDWG timer once it has been started */
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wdvdbg("Entry\n");
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return -ENOSYS;
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}
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@ -289,7 +380,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
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* the atchdog timer or "petting the dog".
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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*
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* Returned Values:
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@ -301,6 +392,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
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{
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/* Reload the IWDG timer */
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wdvdbg("Entry\n");
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stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
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return OK;
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}
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@ -312,7 +404,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
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* Get the current watchdog timer status
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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* stawtus - The location to return the watchdog status information.
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*
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@ -328,6 +420,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
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uint32_t elapsed;
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uint16_t reload;
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wdvdbg("Entry\n");
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DEBUGASSERT(priv);
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/* Return the status bit */
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@ -350,6 +443,11 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
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reload = stm32_getreg(STM32_IWDG_RLR);
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elapsed = priv->reload - reload;
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status->timeleft = (priv->timeout * elapsed) / priv->reload;
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wdvdbg("Status :\n");
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wdvdbg(" flags : %08x\n", status->flags);
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wdvdbg(" timeout : %d\n", status->timeout);
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wdvdbg(" timeleft : %d\n", status->flags);
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return OK;
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}
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@ -360,7 +458,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
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* Set a new timeout value (and reset the watchdog timer)
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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* timeout - The new timeout value in millisecnds.
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*
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@ -373,18 +471,41 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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uint32_t timeout)
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{
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FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
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uint32_t frequency;
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uint32_t fiwdg;
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uint64_t reload;
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int pr;
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int prescaler;
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int shift;
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wdvdbg("Entry: timeout=%d\n", timeout);
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DEBUGASSERT(priv);
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/* Can this timeout be represented? */
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if (timeout < 1 || timeout > IWDG_MAXTIMEOUT)
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{
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wddbg("Cannot represent timeout=%d > %d\n",
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timeout, IWDG_MAXTIMEOUT);
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return -ERANGE;
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}
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/* REVISIT: It appears that you can only setup the prescaler and reload
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* registers once. After that, the SR register's PVU and RVU bits never go
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* to zero.
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*/
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#ifdef CONFIG_STM32_IWDG_ONETIMESETUP
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if (priv->started)
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{
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wddbg("Timer is already started\n");
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return -EBUSY;
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}
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#endif
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/* Select the smallest prescaler that will result in a reload value that is
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* less than the maximum.
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*/
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for (pr = 0; ; pr++)
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for (prescaler = 0; ; prescaler++)
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{
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/* PR = 0 -> Divider = 4 = 1 << 2
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* PR = 1 -> Divider = 8 = 1 << 3
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@ -396,32 +517,32 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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* PR = n -> Divider = 1 << (n+2)
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*/
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shift = pr + 2;
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shift = prescaler + 2;
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/* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
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* this is value in the range of 7500 and 125.
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*/
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frequency = priv->lsifreq >> shift;
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fiwdg = priv->lsifreq >> shift;
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/* We want:
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* 1000 * reload / frequency = timeout
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* 1000 * reload / Fiwdg = timeout
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* Or:
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* reload = frequency * timeout / 1000
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* reload = Fiwdg * timeout / 1000
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*/
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reload = (uint64_t)frequency * (uint64_t)timeout / 1000;
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reload = (uint64_t)fiwdg * (uint64_t)timeout / 1000;
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/* If this reload valid is less than the maximum or we are not ready
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* at the prescaler value, then break out of the loop to use these
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* settings.
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*/
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if (reload <= IWDG_RLR_MAX || pr == 6)
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if (reload <= IWDG_RLR_MAX || prescaler == 6)
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{
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/* Note that we explicity break out of the loop rather than using
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* the 'for' loop termination logic because we do not want the
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* value of pr to be incremented.
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* value of prescaler to be incremented.
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*/
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break;
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@ -435,33 +556,35 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
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reload = IWDG_RLR_MAX;
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}
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/* Enable write access to IWDG_PR and IWDG_RLR registers */
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stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
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/* Set the prescaler */
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stm32_putreg((uint16_t)pr << IWDG_PR_SHIFT, STM32_IWDG_PR);
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/* Set the reload value */
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stm32_putreg((uint16_t)reload, STM32_IWDG_RLR);
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/* Get the actual timeout value in milliseconds.
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*
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* We have:
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* reload = frequency * timeout / 1000
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* reload = Fiwdg * timeout / 1000
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* So we want:
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* timeout = 1000 * reload / frequency
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* timeout = 1000 * reload / Fiwdg
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*/
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priv->timeout = (1000 * reload) / frequency;
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priv->timeout = (1000 * (uint32_t)reload) / fiwdg;
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/* Save setup values for later use */
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priv->prescaler = pr; /* Not needed */
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priv->prescaler = prescaler;
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priv->reload = reload;
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/* Write the prescaler and reload values to the IWDG registers.
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*
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* REVISIT: It appears that you can only setup the prescaler and reload
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* registers once. After that, the SR register's PVU and RVU bits never go
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* to zero.
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*/
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#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
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stm32_setprescaler(priv);
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#endif
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wdvdbg("prescaler=%d fiwdg=%d reload=%d timeout=%d\n",
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prescaler, fiwdg, reload, priv->timeout);
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return OK;
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}
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@ -491,15 +614,17 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
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{
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FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
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wdvdbg("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
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/* NOTE we assume that clocking to the IWDG has already been provided by
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* the RCC initialization logic.
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*/
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/* Initialize the driver state structure. */
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priv->ops = &g_wdgops;
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priv->ops = &g_wdgops;
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priv->lsifreq = lsifreq;
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priv->lsifreq = false;
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priv->started = false;
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/* Make sure that the LSI ocsillator is enabled. NOTE: The LSI oscillator
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* is enabled here but is not disabled by this file (because this file does
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@ -509,6 +634,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
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*/
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stm32_rcc_enablelsi();
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wdvdbg("RCC CSR: %08x\n", getreg32(STM32_RCC_CSR));
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/* Select an arbitrary initial timeout value. But don't start the watchdog
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* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
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@ -73,7 +73,11 @@ void stm32_rcc_enablelsi(void)
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* the RCC CSR register.
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*/
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modifyreg16(STM32_RCC_CSR, 0, RCC_CSR_LSION);
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modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
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/* Wait for the internal RC 40 kHz oscillator to be stable. */
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while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
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}
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/****************************************************************************
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@ -90,5 +94,7 @@ void stm32_rcc_disablelsi(void)
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* the RCC CSR register.
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*/
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modifyreg16(STM32_RCC_CSR, RCC_CSR_LSION, 0);
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modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
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/* LSIRDY should go low after 3 LSI clock cycles */
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}
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@ -57,7 +57,7 @@
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* Pre-Processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The minimum frequency of the WWD clock is:
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/* The minimum frequency of the WWDG clock is:
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*
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* Fmin = PCLK1 / 4096 / 8
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*
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@ -334,7 +334,7 @@ static int stm32_interrupt(int irq, FAR void *context)
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* Start the watchdog timer, resetting the time to the current timeout,
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of the "lower
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* lower - A pointer the publicly visible representation of the "lower-half"
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* driver state structure.
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||||
*
|
||||
* Returned Values:
|
||||
|
|
@ -366,7 +366,7 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
|
|||
* Stop the watchdog timer
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
|
|
@ -400,7 +400,7 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
|
|||
* 0xff and 0xC0:
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
|
|
@ -430,7 +430,7 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
|
|||
* Get the current watchdog timer status
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* stawtus - The location to return the watchdog status information.
|
||||
*
|
||||
|
|
@ -486,7 +486,7 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
|
|||
* Set a new timeout value (and reset the watchdog timer)
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* timeout - The new timeout value in millisecnds.
|
||||
*
|
||||
|
|
@ -583,7 +583,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
|
|||
|
||||
/* Calculate and save the actual timeout value in milliseconds:
|
||||
*
|
||||
* timeout = 1000 * (reload + 1) / Fwwdg, OR
|
||||
* timeout = 1000 * (reload + 1) / Fwwdg
|
||||
*/
|
||||
|
||||
priv->timeout = 1000 * (reload + 1) / fwwdg;
|
||||
|
|
@ -620,7 +620,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
|
|||
* behavior.
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* newhandler - The new watchdog expiration function pointer. If this
|
||||
* function pointer is NULL, then the the reset-on-expiration
|
||||
|
|
@ -687,7 +687,7 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
|
|||
* are forwarded to the lower half driver through this method.
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* cmd - The ioctol command value
|
||||
* arg - The optional argument that accompanies the 'cmd'. The
|
||||
|
|
|
|||
|
|
@ -843,3 +843,13 @@ Where <subdir> is one of the following:
|
|||
CONFIG_WATCHDOG=y : Enables watchdog timer driver support
|
||||
CONFIG_STM32_WWDG=y : Enables the WWDG timer facility, OR
|
||||
CONFIG_STM32_IWDG=y : Enables the IWDG timer facility (but not both)
|
||||
|
||||
The WWDG watchdog is driven off the (fast) 42MHz PCLK1 and, as result,
|
||||
has a maximum timout value of 49 milliseconds. for WWDG watchdog, you
|
||||
should also add the fillowing to the configuration file:
|
||||
|
||||
CONFIG_EXAMPLES_WATCHDOG_PINGDELAY=20
|
||||
CONFIG_EXAMPLES_WATCHDOG_TIMEOUT=49
|
||||
|
||||
The IWDG timer has a range of about 35 seconds and should not be an issue.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue