PIC32MZ: Add a basic SPI driver
This commit is contained in:
Gregory Nutt
parent
8192318148
commit
cf88b8d8b9
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@ -63,7 +63,7 @@
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#define PIC32MX_SPI_BRGINV_OFFSET 0x003c /* SPI baud rate invert register */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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#define PIC32MX_SPI_CON2_OFFSET 0x0020 /* SPI control register 2*/
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#define PIC32MX_SPI_CON2_OFFSET 0x0040 /* SPI control register 2*/
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#endif
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/* Register Addresses *******************************************************/
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@ -168,10 +168,10 @@
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# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 32-bit data width */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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/* With AUDEN=1: */
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# define SPI_CON_MODE_243232 (0 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_323232 (0 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_161632 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_161616 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 16-bit channel */
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# define SPI_CON_MODE_161632 (1 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_323232 (2 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */
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# define SPI_CON_MODE_243232 (3 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */
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#endif
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#define SPI_CON_DISSDO (1 << 12) /* Bits 12: Disable SDOx pin */
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#define SPI_CON_SIDL (1 << 13) /* Bits 13: Stop in idle mode */
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@ -215,7 +215,7 @@
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# define SPI2_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
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# define SPI2_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
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/* Bit 2: Reserved */
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# define SPI2_CON2_AUDMONO (1 << 6) /* Bit 3: Transmit Audio Data Format */
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# define SPI2_CON2_AUDMONO (1 << 3) /* Bit 3: Transmit Audio Data Format */
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/* Bits 5-6: Reserved */
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# define SPI2_CON2_AUDEN (1 << 7) /* Bit 7: Enable Audio CODEC Support */
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# define SPI2_CON2_IGNTUR (1 << 8) /* Bit 8: Ignore Transmit Underrun bit */
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@ -33,6 +33,10 @@ config PIC32MZ_MVEC
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bool
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default n
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config PIC32MZ_SPI
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bool
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default y
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config PIC32MZ_T1
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bool
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default y
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@ -138,18 +142,32 @@ config PIC32MZ_I2C5
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config PIC32MZ_SPI1
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bool "SPI1"
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default n
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select PIC32MX_SPI
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config PIC32MZ_SPI2
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bool "SPI2"
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default n
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select PIC32MX_SPI
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config PIC32MZ_SPI3
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bool "SPI3"
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default n
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select PIC32MX_SPI
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config PIC32MZ_SPI4
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bool "SPI4"
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default n
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select PIC32MX_SPI
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config PIC32MZ_SPI5
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bool "SPI5"
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default n
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select PIC32MX_SPI
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config PIC32MZ_SPI6
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bool "SPI6"
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default n
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select PIC32MX_SPI
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config PIC32MZ_UART1
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bool "UART1"
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@ -246,7 +264,7 @@ config PIC32MZ_CTMU
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bool "Charge Time Measurement Unit (CMTU)"
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default n
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endmenu
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endmenu # PIC32MX Peripheral Support
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menuconfig PIC32MZ_GPIOIRQ
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bool "GPIO Interrupt Support"
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@ -256,48 +274,61 @@ menuconfig PIC32MZ_GPIOIRQ
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if PIC32MZ_GPIOIRQ
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menuconfig PIC32MZ_GPIOIRQ_PORTA
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config PIC32MZ_GPIOIRQ_PORTA
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bool "I/O PORTA Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTB
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config PIC32MZ_GPIOIRQ_PORTB
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bool "I/O PORTB Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTC
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config PIC32MZ_GPIOIRQ_PORTC
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bool "I/O PORTC Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTD
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config PIC32MZ_GPIOIRQ_PORTD
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bool "I/O PORTD Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTE
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config PIC32MZ_GPIOIRQ_PORTE
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bool "I/O PORTE Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTF
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config PIC32MZ_GPIOIRQ_PORTF
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bool "I/O PORTF Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTG
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config PIC32MZ_GPIOIRQ_PORTG
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bool "I/O PORTG Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTH
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config PIC32MZ_GPIOIRQ_PORTH
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bool "I/O PORTH Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTJ
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config PIC32MZ_GPIOIRQ_PORTJ
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bool "I/O PORTJ Interrupt Support"
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default n
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menuconfig PIC32MZ_GPIOIRQ_PORTK
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config PIC32MZ_GPIOIRQ_PORTK
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bool "I/O PORTK Interrupt Support"
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default n
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endif # PIC32MZ_GPIOIRQ
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menu "SPI Driver Configuration"
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depends on PIC32MZ_SPI && EXPERIMENTAL
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config PIC32MZ_SPI_INTERRUPTS
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bool "SPI Interrupt Driven"
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default n
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config PIC32MZ_SPI_ENHBUF
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bool "SPI Enhanced Buffer Mode"
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default n
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endmenu # SPI Driver Configuration
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config PIC32MZ_T1_SOSC
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bool
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default n
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@ -377,7 +408,7 @@ config NET_MULTICAST
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Enable receipt of multicast (and unicast) frames. Automatically set if
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NET_IGMP is selected.
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endmenu
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endmenu # PIC32MZ PHY/Ethernet device driver settings
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menu "Device Configuration 0 (DEVCFG0)"
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@ -417,7 +448,7 @@ config PIC32MZ_ECC_OPTION
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2: ECC / dynamic ECC disabled (locked) */
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3: ECC / dynamic ECC disabled (writable) */
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endmenu
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endmenu # Device configuration 0 (DEVCFG0)
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menu "Device Configuration 1 (DEVCFG1)"
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@ -440,7 +471,7 @@ config PIC32MZ_WDTENABLE
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1: Watchdog enabled, cannot be disabled
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0: Watchdog disabled, can be enabled
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endmenu
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endmenu # Device Configuration 2 (DEVCFG2)
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menu "Device Configuration 3 (DEVCFG3)"
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@ -496,5 +527,5 @@ config PIC32MZ_FUSBIDIO
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0 = USBID pin is controlled by the port function
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1 = USBID pin is controlled by the USB module
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endmenu
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endmenu # Device Configuration 3 (DEVCFG3)
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endif
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@ -73,3 +73,7 @@ CHIP_CSRCS += pic32mz-lowconsole.c pic32mz-serial.c
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ifeq ($(CONFIG_PIC32MZ_GPIOIRQ),y)
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CHIP_CSRCS += pic32mz-gpioirq.c
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endif
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ifeq ($(CONFIG_PIC32MZ_SPI),y)
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CHIP_CSRCS += pic32mz-spi.c
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endif
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@ -0,0 +1,330 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mz-spi.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H
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#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/pic32mz/chip.h>
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#include "chip/pic32mz-memorymap.h"
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#if CHIP_NSPI > 0
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* SPI Peripheral Offsets ***************************************************/
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#define PIC32MZ_SPIn_OFFSET(n) ((n) << 9)
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# define PIC32MZ_SPI1_OFFSET 0x0000
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# define PIC32MZ_SPI2_OFFSET 0x0200
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# define PIC32MZ_SPI3_OFFSET 0x0400
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# define PIC32MZ_SPI4_OFFSET 0x0600
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# define PIC32MZ_SPI5_OFFSET 0x0800
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# define PIC32MZ_SPI6_OFFSET 0x0a00
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/* SPI Register Offsets *****************************************************/
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#define PIC32MZ_SPI_CON_OFFSET 0x0000 /* SPI control register */
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#define PIC32MZ_SPI_CONCLR_OFFSET 0x0004 /* SPI control clear register */
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#define PIC32MZ_SPI_CONSET_OFFSET 0x0008 /* SPI control set register */
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#define PIC32MZ_SPI_CONINV_OFFSET 0x000c /* SPI control invert register */
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#define PIC32MZ_SPI_STAT_OFFSET 0x0010 /* SPI status register */
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#define PIC32MZ_SPI_STATCLR_OFFSET 0x0014 /* SPI status clear register */
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#define PIC32MZ_SPI_BUF_OFFSET 0x0020 /* SPI buffer register */
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#define PIC32MZ_SPI_BRG_OFFSET 0x0030 /* SPI baud rate register */
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#define PIC32MZ_SPI_BRGCLR_OFFSET 0x0034 /* SPI baud rate clear register */
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#define PIC32MZ_SPI_BRGSET_OFFSET 0x0038 /* SPI baud rate set register */
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#define PIC32MZ_SPI_BRGINV_OFFSET 0x003c /* SPI baud rate invert register */
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#define PIC32MZ_SPI_CON2_OFFSET 0x0040 /* SPI control register 2*/
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#define PIC32MZ_SPI_CON2CLR_OFFSET 0x0040 /* SPI control register 2*/
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#define PIC32MZ_SPI_CON2SET_OFFSET 0x0040 /* SPI control register 2*/
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#define PIC32MZ_SPI_CON2INV_OFFSET 0x0040 /* SPI control register 2*/
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/* SPI Peripheral Addresses *************************************************/
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#define PIC32MZ_SPIn_K1BASE(n) (PIC32MZ_SPI_K1BASE + PIC32MZ_SPIn_OFFSET(n))
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# define PIC32MZ_SPI1_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI1_OFFSET)
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# define PIC32MZ_SPI2_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI2_OFFSET)
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# define PIC32MZ_SPI3_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI3_OFFSET)
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# define PIC32MZ_SPI4_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI4_OFFSET)
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# define PIC32MZ_SPI5_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI5_OFFSET)
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# define PIC32MZ_SPI6_K1BASE (PIC32MZ_SPI_K1BASE + PIC32MZ_SPI6_OFFSET)
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/* SPI Register Addresses ***************************************************/
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#define PIC32MZ_SPI1_CON (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON_OFFSET)
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#define PIC32MZ_SPI1_CONCLR (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
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#define PIC32MZ_SPI1_CONSET (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
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#define PIC32MZ_SPI1_CONINV (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
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#define PIC32MZ_SPI1_STAT (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
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#define PIC32MZ_SPI1_STATCLR (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
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#define PIC32MZ_SPI1_BUF (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
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#define PIC32MZ_SPI1_BRG (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
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#define PIC32MZ_SPI1_BRGCLR (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
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#define PIC32MZ_SPI1_BRGSET (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
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#define PIC32MZ_SPI1_BRGINV (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
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#define PIC32MZ_SPI1_CON2 (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2_OFFSET)
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#define PIC32MZ_SPI1_CON2CLR (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
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#define PIC32MZ_SPI1_CON2SET (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
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#define PIC32MZ_SPI1_CON2INV (PIC32MZ_SPI1_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
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#if PIC32MZ_NSPI > 1
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# define PIC32MZ_SPI2_CON (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON_OFFSET)
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# define PIC32MZ_SPI2_CONCLR (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
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# define PIC32MZ_SPI2_CONSET (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
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# define PIC32MZ_SPI2_CONINV (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
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# define PIC32MZ_SPI2_STAT (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
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# define PIC32MZ_SPI2_STATCLR (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
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# define PIC32MZ_SPI2_BUF (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
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# define PIC32MZ_SPI2_BRG (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
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# define PIC32MZ_SPI2_BRGCLR (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
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# define PIC32MZ_SPI2_BRGSET (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
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# define PIC32MZ_SPI2_BRGINV (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
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# define PIC32MZ_SPI2_CON2 (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON2_OFFSET)
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# define PIC32MZ_SPI2_CON2CLR (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
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# define PIC32MZ_SPI2_CON2SET (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
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# define PIC32MZ_SPI2_CON2INV (PIC32MZ_SPI2_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
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#endif
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#if PIC32MZ_NSPI > 2
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# define PIC32MZ_SPI3_CON (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON_OFFSET)
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# define PIC32MZ_SPI3_CONCLR (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
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# define PIC32MZ_SPI3_CONSET (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
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# define PIC32MZ_SPI3_CONINV (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
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# define PIC32MZ_SPI3_STAT (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
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# define PIC32MZ_SPI3_STATCLR (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
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# define PIC32MZ_SPI3_BUF (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
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# define PIC32MZ_SPI3_BRG (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
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# define PIC32MZ_SPI3_BRGCLR (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
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# define PIC32MZ_SPI3_BRGSET (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
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# define PIC32MZ_SPI3_BRGINV (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
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# define PIC32MZ_SPI3_CON2CLR (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
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# define PIC32MZ_SPI3_CON2SET (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
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# define PIC32MZ_SPI3_CON2INV (PIC32MZ_SPI3_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
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#endif
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#if PIC32MZ_NSPI > 3
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# define PIC32MZ_SPI4_CON (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON_OFFSET)
|
||||
# define PIC32MZ_SPI4_CONCLR (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
|
||||
# define PIC32MZ_SPI4_CONSET (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
|
||||
# define PIC32MZ_SPI4_CONINV (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
|
||||
# define PIC32MZ_SPI4_STAT (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
|
||||
# define PIC32MZ_SPI4_STATCLR (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
|
||||
# define PIC32MZ_SPI4_BUF (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
|
||||
# define PIC32MZ_SPI4_BRG (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
|
||||
# define PIC32MZ_SPI4_BRGCLR (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
|
||||
# define PIC32MZ_SPI4_BRGSET (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
|
||||
# define PIC32MZ_SPI4_BRGINV (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
|
||||
# define PIC32MZ_SPI4_CON2CLR (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
|
||||
# define PIC32MZ_SPI4_CON2SET (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
|
||||
# define PIC32MZ_SPI4_CON2INV (PIC32MZ_SPI4_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
|
||||
#endif
|
||||
|
||||
#if PIC32MZ_NSPI > 4
|
||||
# define PIC32MZ_SPI5_CON (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON_OFFSET)
|
||||
# define PIC32MZ_SPI5_CONCLR (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
|
||||
# define PIC32MZ_SPI5_CONSET (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
|
||||
# define PIC32MZ_SPI5_CONINV (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
|
||||
# define PIC32MZ_SPI5_STAT (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
|
||||
# define PIC32MZ_SPI5_STATCLR (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
|
||||
# define PIC32MZ_SPI5_BUF (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
|
||||
# define PIC32MZ_SPI5_BRG (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
|
||||
# define PIC32MZ_SPI5_BRGCLR (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
|
||||
# define PIC32MZ_SPI5_BRGSET (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
|
||||
# define PIC32MZ_SPI5_BRGINV (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
|
||||
# define PIC32MZ_SPI5_CON2CLR (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
|
||||
# define PIC32MZ_SPI5_CON2SET (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
|
||||
# define PIC32MZ_SPI5_CON2INV (PIC32MZ_SPI5_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
|
||||
#endif
|
||||
|
||||
#if PIC32MZ_NSPI > 5
|
||||
# define PIC32MZ_SPI6_CON (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CON_OFFSET)
|
||||
# define PIC32MZ_SPI6_CONCLR (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CONCLR_OFFSET)
|
||||
# define PIC32MZ_SPI6_CONSET (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CONSET_OFFSET)
|
||||
# define PIC32MZ_SPI6_CONINV (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CONINV_OFFSET)
|
||||
# define PIC32MZ_SPI6_STAT (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_STAT_OFFSET)
|
||||
# define PIC32MZ_SPI6_STATCLR (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_STATCLR_OFFSET)
|
||||
# define PIC32MZ_SPI6_BUF (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_BUF_OFFSET)
|
||||
# define PIC32MZ_SPI6_BRG (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_BRG_OFFSET)
|
||||
# define PIC32MZ_SPI6_BRGCLR (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_BRGCLR_OFFSET)
|
||||
# define PIC32MZ_SPI6_BRGSET (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_BRGSET_OFFSET)
|
||||
# define PIC32MZ_SPI6_BRGINV (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_BRGINV_OFFSET)
|
||||
# define PIC32MZ_SPI6_CON2CLR (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CON2CLR_OFFSET)
|
||||
# define PIC32MZ_SPI6_CON2SET (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CON2SET_OFFSET)
|
||||
# define PIC32MZ_SPI6_CON2INV (PIC32MZ_SPI6_K1BASE+PIC32MZ_SPI_CON2INV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bit-Field Definitions *******************************************/
|
||||
|
||||
/* SPI control register */
|
||||
|
||||
#define SPI_CON_SRXISEL_SHIFT (0) /* Bits 0-1: SPI Receive Buffer Full Interrupt Mode */
|
||||
#define SPI_CON_SRXISEL_MASK (3 << SPI_CON_SRXISEL_SHIFT)
|
||||
# define SPI_CON_SRXISEL_EMPTY (0 << SPI_CON_SRXISEL_SHIFT) /* Buffer empty */
|
||||
# define SPI_CON_SRXISEL_NEMPTY (1 << SPI_CON_SRXISEL_SHIFT) /* Buffer not empty */
|
||||
# define SPI_CON_SRXISEL_HALF (2 << SPI_CON_SRXISEL_SHIFT) /* Buffer half full or more */
|
||||
# define SPI_CON_SRXISEL_FULL (3 << SPI_CON_SRXISEL_SHIFT) /* Buffer full */
|
||||
#define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */
|
||||
#define SPI_CON_STXISEL_MASK (3 << SPI_CON_STXISEL_SHIFT)
|
||||
# define SPI_CON_STXISEL_DONE (0 << SPI_CON_STXISEL_SHIFT) /* Buffer empty (and data shifted out) */
|
||||
# define SPI_CON_STXISEL_EMPTY (1 << SPI_CON_STXISEL_SHIFT) /* Buffer empty */
|
||||
# define SPI_CON_STXISEL_HALF (2 << SPI_CON_STXISEL_SHIFT) /* Buffer half empty or more */
|
||||
# define SPI_CON_STXISEL_NFULL (3 << SPI_CON_STXISEL_SHIFT) /* Buffer not full */
|
||||
#define SPI_CON_DISSDI (1 << 4) /* Bit 4: Disable SDI */
|
||||
#define SPI_CON_MSTEN (1 << 5) /* Bit 5: Master mode enable */
|
||||
#define SPI_CON_CKP (1 << 6) /* Bit 6: Clock polarity select */
|
||||
#define SPI_CON_SSEN (1 << 7) /* Bit 7: Slave select enable (slave mode) */
|
||||
#define SPI_CON_CKE (1 << 8) /* Bit 8: SPI clock edge select */
|
||||
#define SPI_CON_SMP (1 << 9) /* Bit 9: SPI data input sample phase */
|
||||
#define SPI_CON_MODE_SHIFT (10) /* Bits 10-11: 32/16-Bit Communication Select */
|
||||
#define SPI_CON_MODE_MASK (3 << SPI_CON_MODE_SHIFT)
|
||||
/* With AUDEN=0: */
|
||||
# define SPI_CON_MODE_8BIT (0 << SPI_CON_MODE_SHIFT) /* 8-bit data width */
|
||||
# define SPI_CON_MODE_16BIT (1 << SPI_CON_MODE_SHIFT) /* 16-bit data width */
|
||||
# define SPI_CON_MODE_32BIT (2 << SPI_CON_MODE_SHIFT) /* 32-bit data width */
|
||||
/* With AUDEN=1: */
|
||||
# define SPI_CON_MODE_161616 (0 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 16-bit channel */
|
||||
# define SPI_CON_MODE_161632 (1 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */
|
||||
# define SPI_CON_MODE_323232 (2 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */
|
||||
# define SPI_CON_MODE_243232 (3 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */
|
||||
#define SPI_CON_DISSDO (1 << 12) /* Bit 12: Disable SDOx pin */
|
||||
#define SPI_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define SPI_CON_ON (1 << 15) /* Bit 15: SPI peripheral on */
|
||||
#define SPI_CON_ENHBUF (1 << 16) /* Bit 16: Enhanced buffer enable */
|
||||
#define SPI_CON_SPIFE (1 << 17) /* Bit 17: Frame sync pulse edge select */
|
||||
/* Bits 18-23: Reserved */
|
||||
#define SPI_CON_MCLKSEL (1 << 23) /* Bit 23: Master clock enable */
|
||||
#define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */
|
||||
#define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT)
|
||||
# define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */
|
||||
# define SPI_CON_FRMCNT_CHAR2 (1 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 2 chars */
|
||||
# define SPI_CON_FRMCNT_CHAR4 (2 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 4 chars */
|
||||
# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
|
||||
# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
|
||||
# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
|
||||
#define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
|
||||
#define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
|
||||
#define SPI_CON_FRMPOL (1 << 29) /* Bits 29: Frame sync polarity */
|
||||
#define SPI_CON_FRMSYNC (1 << 30) /* Bits 30: Frame sync pulse direction control on SSx pin */
|
||||
#define SPI_CON_FRMEN (1 << 31) /* Bits 31: Framed SPI support */
|
||||
|
||||
/* SPI control register 2 */
|
||||
|
||||
#define SPI2_CON2_AUDMOD_SHIFT (0) /* Bits 0-1: Audio Protocol Mode */
|
||||
#define SPI2_CON2_AUDMOD_MASK (3 << SPI2_CON2_AUDMOD_SHIFT)
|
||||
# define SPI2_CON2_AUDMOD_I2S (0 << SPI2_CON2_AUDMOD_SHIFT) /* I2S mode */
|
||||
# define SPI2_CON2_AUDMOD_LJ (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
|
||||
# define SPI2_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
|
||||
# define SPI2_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
|
||||
/* Bit 2: Reserved */
|
||||
#define SPI2_CON2_AUDMONO (1 << 3) /* Bit 3: Transmit Audio Data Format */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define SPI2_CON2_AUDEN (1 << 7) /* Bit 7: Enable Audio CODEC Support */
|
||||
#define SPI2_CON2_IGNTUR (1 << 8) /* Bit 8: Ignore Transmit Underrun bit */
|
||||
#define SPI2_CON2_IGNROV (1 << 9) /* Bit 9: Ignore Receive Overflow */
|
||||
#define SPI2_CON2_SPITUREN (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */
|
||||
#define SPI2_CON2_SPIROVEN (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */
|
||||
#define SPI2_CON2_FRMERREN (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */
|
||||
/* Bits 13-14: Reserved */
|
||||
#define SPI2_CON2_SPISGNEXT (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_STAT_SPIRBF (1 << 0) /* Bit 0: SPI receive buffer full status */
|
||||
#define SPI_STAT_SPITBF (1 << 1) /* Bit 1: SPI transmit buffer full status */
|
||||
#define SPI_STAT_SPITBE (1 << 3) /* Bit 3: SPI transmit buffer empty status */
|
||||
/* Bit 4: Reserved */
|
||||
#define SPI_STAT_SPIRBE (1 << 5) /* Bit 5: RX FIFO Empty */
|
||||
#define SPI_STAT_SPIROV (1 << 6) /* Bit 6: Receive overflow flag */
|
||||
#define SPI_STAT_SRMT (1 << 7) /* Bit 6: Shift Register Empty */
|
||||
#define SPI_STAT_SPITUR (1 << 8) /* Bit 8: Transmit under run */
|
||||
/* Bits 9-10: Reserved */
|
||||
#define SPI_STAT_SPIBUSY (1 << 11) /* Bit 11: SPI activity status */
|
||||
#define SPI_STAT_FRMERR (1 << 12) /* Bit 12: SPI Frame Error status */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */
|
||||
#define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT)
|
||||
# define SPI_STAT_TXBUFELM(n) ((uint32_t)(n) << SPI_STAT_TXBUFELM_SHIFT)
|
||||
/* Bits 21-23: Reserved */
|
||||
#define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */
|
||||
#define SPI_STAT_RXBUFELM_MASK (31 << SPI_STAT_RXBUFELM_SHIFT)
|
||||
# define SPI_STAT_RXBUFELM(n) ((uint32_t)(n) << SPI_STAT_RXBUFELM_SHIFT)
|
||||
|
||||
/* SPI buffer register (32-bits wide) */
|
||||
|
||||
/* SPI baud rate register */
|
||||
|
||||
#define SPI_BRG_MASK 0x00001fff
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CHIP_NSPI > 0 */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H */
|
||||
|
|
@ -191,6 +191,47 @@
|
|||
# undef HAVE_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
/* SPI ******************************************************************************/
|
||||
/* Don't enable SPI peripherals not supported by the chip. */
|
||||
|
||||
#if CHIP_NSPI < 1
|
||||
# undef CONFIG_PIC32MZ_SPI1
|
||||
# undef CONFIG_PIC32MZ_SPI2
|
||||
# undef CONFIG_PIC32MZ_SPI3
|
||||
# undef CONFIG_PIC32MZ_SPI4
|
||||
# undef CONFIG_PIC32MZ_SPI5
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#elif CHIP_NSPI < 2
|
||||
# undef CONFIG_PIC32MZ_SPI2
|
||||
# undef CONFIG_PIC32MZ_SPI3
|
||||
# undef CONFIG_PIC32MZ_SPI4
|
||||
# undef CONFIG_PIC32MZ_SPI5
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#elif CHIP_NSPI < 3
|
||||
# undef CONFIG_PIC32MZ_SPI3
|
||||
# undef CONFIG_PIC32MZ_SPI4
|
||||
# undef CONFIG_PIC32MZ_SPI5
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#elif CHIP_NSPI < 4
|
||||
# undef CONFIG_PIC32MZ_SPI4
|
||||
# undef CONFIG_PIC32MZ_SPI5
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#elif CHIP_NSPI < 5
|
||||
# undef CONFIG_PIC32MZ_SPI5
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#elif CHIP_NSPI < 6
|
||||
# undef CONFIG_PIC32MZ_SPI6
|
||||
#endif
|
||||
|
||||
/* Are any SPI peripherals enabled? */
|
||||
|
||||
#undef CONFIG_PIC32MZ_SPI
|
||||
#if defined(CONFIG_PIC32MZ_SPI1) || defined(CONFIG_PIC32MZ_SPI2) || \
|
||||
defined(CONFIG_PIC32MZ_SPI4) || defined(CONFIG_PIC32MZ_SPI4) || \
|
||||
defined(CONFIG_PIC32MZ_SPI5) || defined(CONFIG_PIC32MZ_SPI6)
|
||||
# define CONFIG_PIC32MZ_SPI 1
|
||||
#endif
|
||||
|
||||
/* Device Configuration *************************************************************/
|
||||
/* DEVCFG3 */
|
||||
/* Configurable settings */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue