Clean up LPC43 USART vs UART naming
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4903 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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<tr align="center" bgcolor="#e4e4e4">
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<td>
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<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
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<p>Last Updated: June 29, 2012</p>
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<p>Last Updated: July 4, 2012</p>
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</td>
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</tr>
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</table>
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@ -107,6 +107,8 @@
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| | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/lm3s8962-ek/README.txt?view=log"><b><i>README.txt</i></b></a>
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| | |- lpcxpresso-lpc1768/
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| | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/lpcxpresso-lpc1768/README.txt?view=log"><b><i>README.txt</i></b></a>
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| | |- lpc4330-xplorer/
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| | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/llpc4330-xplorer/README.txt?view=log"><b><i>README.txt</i></b></a>
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| | |- m68332evb/
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| | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/m68332evb/include/README.txt?view=log">include/README.txt</a>
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| | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/m68332evb/src/README.txt?view=log">src/README.txt</a>
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@ -670,6 +670,8 @@ nuttx
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| | `- README.txt
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| |- lpcxpresso-lpc1768/
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| | `- README.txt
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| |- lpc4330-xplorer/
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| | `- README.txt
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| |- m68332evb/
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| | |- include/README.txt
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| | `- src/README.txt
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@ -111,8 +111,8 @@
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#define LPC43_CCU1_M4_EEPROM_STAT_OFFSET 0x04a4 /* CLK_M4_EEPROM status register */
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#define LPC43_CCU1_M4_WWDT_CFG_OFFSET 0x0500 /* CLK_M4_WWDT configuration register */
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#define LPC43_CCU1_M4_WWDT_STAT_OFFSET 0x0504 /* CLK_M4_WWDT status register */
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#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_UART0 configuration register */
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#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_UART0 status register */
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#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_USART0 configuration register */
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#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_USART0 status register */
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#define LPC43_CCU1_M4_UART1_CFG_OFFSET 0x0510 /* CLK_M4_UART1 configuration register */
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#define LPC43_CCU1_M4_UART1_STAT_OFFSET 0x0514 /* CLK_M4_UART1 status register */
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#define LPC43_CCU1_M4_SSP0_CFG_OFFSET 0x0518 /* CLK_M4_SSP0 configuration register */
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@ -127,10 +127,10 @@
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#define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */
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#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */
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#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */
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#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_UART2 configuration register */
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#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_UART2 status register */
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#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_UART3 configuration register */
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#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_UART3 status register */
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#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */
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#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_USART2 status register */
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#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_USART3 configuration register */
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#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_USART3 status register */
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#define LPC43_CCU1_M4_TIMER2_CFG_OFFSET 0x0618 /* CLK_M4_TIMER2 configuration register */
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#define LPC43_CCU1_M4_TIMER2_STAT_OFFSET 0x061c /* CLK_M4_TIMER2 status register */
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#define LPC43_CCU1_M4_TIMER3_CFG_OFFSET 0x0620 /* CLK_M4_TIMER3 configuration register */
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@ -158,14 +158,14 @@
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#define LPC43_CCU2_BASE_STAT_OFFSET 0x0004 /* CCU2 base clocks status register */
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#define LPC43_CCU2_APLL_CFG_OFFSET 0x0100 /* CLK_APLL configuration register */
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#define LPC43_CCU2_APLL_STAT_OFFSET 0x0104 /* CLK_APLL status register */
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#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_UART3 configuration register */
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#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_UART3 status register */
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#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_UART2 configuration register */
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#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_UART2 status register */
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#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_USART3 configuration register */
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#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_USART3 status register */
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#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_USART2 configuration register */
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#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_USART2 status register */
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#define LPC43_CCU2_APB0_UART1_CFG_OFFSET 0x0400 /* CLK_APB0_UART1 configuration register */
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#define LPC43_CCU2_APB0_UART1_STAT_OFFSET 0x0404 /* CLK_APB0_UART1 status register */
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#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_UART0 configuration register */
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#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_UART0 status register */
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#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_USART0 configuration register */
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#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_USART0 status register */
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#define LPC43_CCU2_APB2_SSP1_CFG_OFFSET 0x0600 /* CLK_APB2_SSP1 configuration register */
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#define LPC43_CCU2_APB2_SSP1_STAT_OFFSET 0x0604 /* CLK_APB2_SSP1 status register */
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#define LPC43_CCU2_APB0_SSP0_CFG_OFFSET 0x0700 /* CLK_APB0_SSP0 configuration register */
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@ -321,10 +321,10 @@
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/* Bits 10-31: Reserved */
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/* CCU2 Base Clock Status Register */
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/* Bit 0: Reserved */
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#define CCU2_BASE_STAT_UART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_UART3_CLK */
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#define CCU2_BASE_STAT_UART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_UART2_CLK */
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#define CCU2_BASE_STAT_USART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_USART3_CLK */
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#define CCU2_BASE_STAT_USART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_USART2_CLK */
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#define CCU2_BASE_STAT_UART1 (1 << 3) /* Bit 3: Base clock indicator for BASE_UART1_CLK */
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#define CCU2_BASE_STAT_UART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_UART0_CLK */
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#define CCU2_BASE_STAT_USART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_USART0_CLK */
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#define CCU2_BASE_STAT_SSP1 (1 << 5) /* Bit 5: Base clock indicator for BASE_SSP1_CLK */
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#define CCU2_BASE_STAT_SSP0 (1 << 6) /* Bit 6: Base clock indicator for BASE_SSP0_CLK */
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/* Bits 7-31: Reserved */
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File diff suppressed because it is too large
Load Diff
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@ -49,7 +49,7 @@
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/* Timer capture input multiplexor registers */
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#define LPC32_GIMA_CAP_OFFSET(t,i) (((t) << 4) | ((i) << 2))
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#define LPC43_GIMA_CAP_OFFSET(t,i) (((t) << 4) | ((i) << 2))
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#define LPC43_GIMA_CAP00_OFFSET 0x0000 /* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
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#define LPC43_GIMA_CAP01_OFFSET 0x0004 /* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
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#define LPC43_GIMA_CAP02_OFFSET 0x0008 /* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
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@ -67,7 +67,7 @@
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#define LPC43_GIMA_CAP32_OFFSET 0x0038 /* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
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#define LPC43_GIMA_CAP33_OFFSET 0x003c /* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
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#define LPC32_GIMA_CTIN_OFFSET(i) (0x0040 + ((i) << 2))
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#define LPC43_GIMA_CTIN_OFFSET(i) (0x0040 + ((i) << 2))
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#define LPC43_GIMA_CTIN0_OFFSET 0x0040 /* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
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#define LPC43_GIMA_CTIN1_OFFSET 0x0044 /* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
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#define LPC43_GIMA_CTIN2_OFFSET 0x0048 /* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
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@ -86,7 +86,7 @@
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/* Register Addresses *******************************************************************************/
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#define LPC32_GIMA_CAP(t,i) (LPC43_GIMA_BASE+LPC32_GIMA_CAP_OFFSET(t,i))
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#define LPC43_GIMA_CAP(t,i) (LPC43_GIMA_BASE+LPC43_GIMA_CAP_OFFSET(t,i))
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#define LPC43_GIMA_CAP00 (LPC43_GIMA_BASE+LPC43_GIMA_CAP00_OFFSET)
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#define LPC43_GIMA_CAP01 (LPC43_GIMA_BASE+LPC43_GIMA_CAP01_OFFSET)
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#define LPC43_GIMA_CAP02 (LPC43_GIMA_BASE+LPC43_GIMA_CAP02_OFFSET)
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@ -104,7 +104,7 @@
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#define LPC43_GIMA_CAP32 (LPC43_GIMA_BASE+LPC43_GIMA_CAP32_OFFSET)
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#define LPC43_GIMA_CAP33 (LPC43_GIMA_BASE+LPC43_GIMA_CAP33_OFFSET)
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#define LPC32_GIMA_CTIN(i) (LPC43_GIMA_BASE+LPC32_GIMA_CTIN_OFFSET(i))
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#define LPC43_GIMA_CTIN(i) (LPC43_GIMA_BASE+LPC43_GIMA_CTIN_OFFSET(i))
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#define LPC43_GIMA_CTIN0 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN0_OFFSET)
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#define LPC43_GIMA_CTIN1 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN1_OFFSET)
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#define LPC43_GIMA_CTIN2 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN2_OFFSET)
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# define GPDMA_CONFIG_SRCPER_SSP1RX_2 (6 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 receive */
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# define GPDMA_CONFIG_SRCPER_SGPIO14_2 (6 << GPDMA_CONFIG_SRCPER_SHIFT) /* SGPIO14 */
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# define GPDMA_CONFIG_SRCPER_T3MAT0_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* Timer3 match 0 */
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# define GPDMA_CONFIG_SRCPER_U3TX_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* UART3 transmit */
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# define GPDMA_CONFIG_SRCPER_U3TX_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 transmit */
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# define GPDMA_CONFIG_SRCPER_SCTD0_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT DMA request 0 */
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# define GPDMA_CONFIG_SRCPER_VADCWR (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* VADC write */
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# define GPDMA_CONFIG_SRCPER_T3MAT1_2 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* Timer3 match 1 */
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# define GPDMA_CONFIG_SRCPER_U3RX_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* UART3 receive */
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# define GPDMA_CONFIG_SRCPER_U3RX_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 receive */
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# define GPDMA_CONFIG_SRCPER_SCTD1_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT DMA request 1 */
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# define GPDMA_CONFIG_SRCPER_VADCRD (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* VADC read */
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# define GPDMA_CONFIG_SRCPER_SSP0RX (9 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP0 receive */
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# define GPDMA_CONFIG_DESTPER_SSP1RX_2 (6 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 receive */
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# define GPDMA_CONFIG_DESTPER_SGPIO14_2 (6 << GPDMA_CONFIG_DESTPER_SHIFT) /* SGPIO14 */
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# define GPDMA_CONFIG_DESTPER_T3MAT0_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* Timer3 match 0 */
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# define GPDMA_CONFIG_DESTPER_U3TX_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* UART3 transmit */
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# define GPDMA_CONFIG_DESTPER_U3TX_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 transmit */
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# define GPDMA_CONFIG_DESTPER_SCTD0_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT DMA request 0 */
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# define GPDMA_CONFIG_DESTPER_VADCWR (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* VADC write */
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# define GPDMA_CONFIG_DESTPER_T3MAT1_2 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* Timer3 match 1 */
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# define GPDMA_CONFIG_DESTPER_U3RX_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* UART3 receive */
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# define GPDMA_CONFIG_DESTPER_U3RX_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 receive */
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# define GPDMA_CONFIG_DESTPER_SCTD1_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT DMA request 1 */
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# define GPDMA_CONFIG_DESTPER_VADCRD (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* VADC read */
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# define GPDMA_CONFIG_DESTPER_SSP0RX (9 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP0 receive */
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@ -47,88 +47,88 @@
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */
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#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */
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#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */
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#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */
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#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */
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#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */
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#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */
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#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */
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#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */
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#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */
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#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */
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#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */
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#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */
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#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */
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#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */
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#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */
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#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */
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#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */
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#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */
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#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */
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#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */
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#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */
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#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */
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#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */
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#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */
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#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */
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#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */
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#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */
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#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */
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#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */
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#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */
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#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */
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#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */
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#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */
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#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */
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#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */
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#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */
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#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */
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#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */
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#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */
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#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */
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#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */
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/* Register Addresses ***************************************************************/
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#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET)
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#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET)
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#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET)
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#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET)
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#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET)
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#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET)
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#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET)
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#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET)
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#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET)
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#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET)
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#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET)
|
||||
#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET)
|
||||
#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET)
|
||||
#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET)
|
||||
#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET)
|
||||
#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET)
|
||||
|
||||
#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET)
|
||||
#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET)
|
||||
#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET)
|
||||
#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET)
|
||||
#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET)
|
||||
#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET)
|
||||
|
||||
#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET)
|
||||
#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET)
|
||||
#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET)
|
||||
#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET)
|
||||
#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET)
|
||||
#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET)
|
||||
#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET)
|
||||
#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET)
|
||||
|
||||
#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET)
|
||||
#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET)
|
||||
#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET)
|
||||
#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET)
|
||||
#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET)
|
||||
#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET)
|
||||
#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET)
|
||||
#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET)
|
||||
|
||||
#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET)
|
||||
#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET)
|
||||
#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET)
|
||||
#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* Customer control data */
|
||||
/* Bits 0-22: Reserved */
|
||||
#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */
|
||||
/* Bit 24: Reserved */
|
||||
#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */
|
||||
#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT)
|
||||
# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */
|
||||
# define OPT_CCD_BOOTSRC_UART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* UART0 */
|
||||
# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */
|
||||
# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */
|
||||
# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */
|
||||
# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */
|
||||
# define OPT_CCD_BOOTSRC_UART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* UART3 */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */
|
||||
/* Bits 0-22: Reserved */
|
||||
#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */
|
||||
/* Bit 24: Reserved */
|
||||
#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */
|
||||
#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT)
|
||||
# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */
|
||||
# define OPT_CCD_BOOTSRC_USART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* USART0 */
|
||||
# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */
|
||||
# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */
|
||||
# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */
|
||||
# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */
|
||||
# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */
|
||||
# define OPT_CCD_BOOTSRC_USART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* USART3 */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */
|
||||
|
||||
/* USB ID */
|
||||
|
||||
#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */
|
||||
#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT)
|
||||
#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */
|
||||
#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT)
|
||||
#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */
|
||||
#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT)
|
||||
#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */
|
||||
#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT)
|
||||
|
||||
/* OTP API *************************************************************************/
|
||||
/* The AES is controlled through a set of simple API calls located in the LPC43xx
|
||||
|
|
|
|||
|
|
@ -47,13 +47,13 @@
|
|||
************************************************************************************/
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define LPC32_PD0_SLEEP0_HWENA_OFFSET 0x0000 /* Hardware sleep event enable register */
|
||||
#define LPC32_PD0_SLEEP0_MODE_OFFSET 0x001c /* Power-down mode control register */
|
||||
#define LPC43_PD0_SLEEP0_HWENA_OFFSET 0x0000 /* Hardware sleep event enable register */
|
||||
#define LPC43_PD0_SLEEP0_MODE_OFFSET 0x001c /* Power-down mode control register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define LPC32_PD0_SLEEP0_HWENA (LPC43_PMC_BASE+LPC32_PD0_SLEEP0_HWENA_OFFSET)
|
||||
#define LPC32_PD0_SLEEP0_MODE (LPC43_PMC_BASE+LPC32_PD0_SLEEP0_MODE_OFFSET)
|
||||
#define LPC43_PD0_SLEEP0_HWENA (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_HWENA_OFFSET)
|
||||
#define LPC43_PD0_SLEEP0_MODE (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_MODE_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *********************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -88,10 +88,10 @@
|
|||
#define RGU_ADC0_RST 40
|
||||
#define RGU_ADC1_RST 41
|
||||
#define RGU_DAC_RST 42
|
||||
#define RGU_UART0_RST 44
|
||||
#define RGU_USART0_RST 44
|
||||
#define RGU_UART1_RST 45
|
||||
#define RGU_UART2_RST 46
|
||||
#define RGU_UART3_RST 47
|
||||
#define RGU_USART2_RST 46
|
||||
#define RGU_USART3_RST 47
|
||||
#define RGU_I2C0_RST 48
|
||||
#define RGU_I2C1_RST 49
|
||||
#define RGU_SSP0_RST 50
|
||||
|
|
@ -137,10 +137,10 @@
|
|||
#define LPC43_RGU_EXTSTAT40_OFFSET 0x4a0 /* Reset external status register 40 for ADC0_RST */
|
||||
#define LPC43_RGU_EXTSTAT41_OFFSET 0x4a4 /* Reset external status register 41 for ADC1_RST */
|
||||
#define LPC43_RGU_EXTSTAT42_OFFSET 0x4a8 /* Reset external status register 42 for DAC_RST */
|
||||
#define LPC43_RGU_EXTSTAT44_OFFSET 0x4b0 /* Reset external status register 44 for UART0_RST */
|
||||
#define LPC43_RGU_EXTSTAT44_OFFSET 0x4b0 /* Reset external status register 44 for USART0_RST */
|
||||
#define LPC43_RGU_EXTSTAT45_OFFSET 0x4b4 /* Reset external status register 45 for UART1_RST */
|
||||
#define LPC43_RGU_EXTSTAT46_OFFSET 0x4b8 /* Reset external status register 46 for UART2_RST */
|
||||
#define LPC43_RGU_EXTSTAT47_OFFSET 0x4bc /* Reset external status register 47 for UART3_RST */
|
||||
#define LPC43_RGU_EXTSTAT46_OFFSET 0x4b8 /* Reset external status register 46 for USART2_RST */
|
||||
#define LPC43_RGU_EXTSTAT47_OFFSET 0x4bc /* Reset external status register 47 for USART3_RST */
|
||||
#define LPC43_RGU_EXTSTAT48_OFFSET 0x4c0 /* Reset external status register 48 for I2C0_RST */
|
||||
#define LPC43_RGU_EXTSTAT49_OFFSET 0x4c4 /* Reset external status register 49 for I2C1_RST */
|
||||
#define LPC43_RGU_EXTSTAT50_OFFSET 0x4c8 /* Reset external status register 50 for SSP0_RST */
|
||||
|
|
@ -245,10 +245,10 @@
|
|||
#define LPC43_RGU_EXTSTAT_ADC0_RST LPC43_RGU_EXTSTAT40
|
||||
#define LPC43_RGU_EXTSTAT_ADC1_RST LPC43_RGU_EXTSTAT41
|
||||
#define LPC43_RGU_EXTSTAT_DAC_RST LPC43_RGU_EXTSTAT42
|
||||
#define LPC43_RGU_EXTSTAT_UART0_RST LPC43_RGU_EXTSTAT44
|
||||
#define LPC43_RGU_EXTSTAT_USART0_RST LPC43_RGU_EXTSTAT44
|
||||
#define LPC43_RGU_EXTSTAT_UART1_RST LPC43_RGU_EXTSTAT45
|
||||
#define LPC43_RGU_EXTSTAT_UART2_RST LPC43_RGU_EXTSTAT46
|
||||
#define LPC43_RGU_EXTSTAT_UART3_RST LPC43_RGU_EXTSTAT47
|
||||
#define LPC43_RGU_EXTSTAT_USART2_RST LPC43_RGU_EXTSTAT46
|
||||
#define LPC43_RGU_EXTSTAT_USART3_RST LPC43_RGU_EXTSTAT47
|
||||
#define LPC43_RGU_EXTSTAT_I2C0_RST LPC43_RGU_EXTSTAT48
|
||||
#define LPC43_RGU_EXTSTAT_I2C1_RST LPC43_RGU_EXTSTAT49
|
||||
#define LPC43_RGU_EXTSTAT_SSP0_RST LPC43_RGU_EXTSTAT50
|
||||
|
|
@ -305,10 +305,10 @@
|
|||
#define RGU_CTRL1_ADC1_RST (1 << 9)
|
||||
#define RGU_CTRL1_DAC_RST (1 << 10)
|
||||
/* Bit 11: Reserved */
|
||||
#define RGU_CTRL1_UART0_RST (1 << 12)
|
||||
#define RGU_CTRL1_USART0_RST (1 << 12)
|
||||
#define RGU_CTRL1_UART1_RST (1 << 13)
|
||||
#define RGU_CTRL1_UART2_RST (1 << 14)
|
||||
#define RGU_CTRL1_UART3_RST (1 << 15)
|
||||
#define RGU_CTRL1_USART2_RST (1 << 14)
|
||||
#define RGU_CTRL1_USART3_RST (1 << 15)
|
||||
#define RGU_CTRL1_I2C0_RST (1 << 16)
|
||||
#define RGU_CTRL1_I2C1_RST (1 << 17)
|
||||
#define RGU_CTRL1_SSP0_RST (1 << 18)
|
||||
|
|
@ -485,26 +485,26 @@
|
|||
# define RGU_STATUS2_DAC_RST_HW (1 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_DAC_RST_SW (3 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by software */
|
||||
/* Bits 22-23: Reserved */
|
||||
#define RGU_STATUS2_UART0_RST_SHIFT (24) /* Bits 24-24: 25:24 Status of the UART0_RST reset generator output */
|
||||
#define RGU_STATUS2_UART0_RST_MASK (3 << RGU_STATUS2_UART0_RST_SHIFT)
|
||||
# define RGU_STATUS2_UART0_RST_NONE (0 << RGU_STATUS2_UART0_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_UART0_RST_HW (1 << RGU_STATUS2_UART0_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_UART0_RST_SW (3 << RGU_STATUS2_UART0_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_USART0_RST_SHIFT (24) /* Bits 24-24: 25:24 Status of the USART0_RST reset generator output */
|
||||
#define RGU_STATUS2_USART0_RST_MASK (3 << RGU_STATUS2_USART0_RST_SHIFT)
|
||||
# define RGU_STATUS2_USART0_RST_NONE (0 << RGU_STATUS2_USART0_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_USART0_RST_HW (1 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_USART0_RST_SW (3 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_UART1_RST_SHIFT (26) /* Bits 26-27: 27:26 Status of the UART1_RST reset generator output */
|
||||
#define RGU_STATUS2_UART1_RST_MASK (3 << RGU_STATUS2_UART1_RST_SHIFT)
|
||||
# define RGU_STATUS2_UART1_RST_NONE (0 << RGU_STATUS2_UART1_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_UART1_RST_HW (1 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_UART1_RST_SW (3 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_UART2_RST_SHIFT (28) /* Bits 28-29: 29:28 Status of the UART2_RST reset generator output */
|
||||
#define RGU_STATUS2_UART2_RST_MASK (3 << RGU_STATUS2_UART2_RST_SHIFT)
|
||||
# define RGU_STATUS2_UART2_RST_NONE (0 << RGU_STATUS2_UART2_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_UART2_RST_HW (1 << RGU_STATUS2_UART2_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_UART2_RST_SW (3 << RGU_STATUS2_UART2_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_UART3_RST_SHIFT (30) /* Bits 30-31: 31:30 Status of the UART3_RST reset generator output */
|
||||
#define RGU_STATUS2_UART3_RST_MASK (3 << RGU_STATUS2_UART3_RST_SHIFT)
|
||||
# define RGU_STATUS2_UART3_RST_NONE (0 << RGU_STATUS2_UART3_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_UART3_RST_HW (1 << RGU_STATUS2_UART3_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_UART3_RST_SW (3 << RGU_STATUS2_UART3_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_USART2_RST_SHIFT (28) /* Bits 28-29: 29:28 Status of the USART2_RST reset generator output */
|
||||
#define RGU_STATUS2_USART2_RST_MASK (3 << RGU_STATUS2_USART2_RST_SHIFT)
|
||||
# define RGU_STATUS2_USART2_RST_NONE (0 << RGU_STATUS2_USART2_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_USART2_RST_HW (1 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_USART2_RST_SW (3 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by software */
|
||||
#define RGU_STATUS2_USART3_RST_SHIFT (30) /* Bits 30-31: 31:30 Status of the USART3_RST reset generator output */
|
||||
#define RGU_STATUS2_USART3_RST_MASK (3 << RGU_STATUS2_USART3_RST_SHIFT)
|
||||
# define RGU_STATUS2_USART3_RST_NONE (0 << RGU_STATUS2_USART3_RST_SHIFT) /* No reset activated */
|
||||
# define RGU_STATUS2_USART3_RST_HW (1 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by reset generator */
|
||||
# define RGU_STATUS2_USART3_RST_SW (3 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by software */
|
||||
|
||||
/* Reset status register 3 */
|
||||
|
||||
|
|
@ -606,10 +606,10 @@
|
|||
#define RGU_ACTIVE1_ADC1_RST (1 << 9)
|
||||
#define RGU_ACTIVE1_DAC_RST (1 << 10)
|
||||
/* Bit 11: Reserved */
|
||||
#define RGU_ACTIVE1_UART0_RST (1 << 12)
|
||||
#define RGU_ACTIVE1_USART0_RST (1 << 12)
|
||||
#define RGU_ACTIVE1_UART1_RST (1 << 13)
|
||||
#define RGU_ACTIVE1_UART2_RST (1 << 14)
|
||||
#define RGU_ACTIVE1_UART3_RST (1 << 15)
|
||||
#define RGU_ACTIVE1_USART2_RST (1 << 14)
|
||||
#define RGU_ACTIVE1_USART3_RST (1 << 15)
|
||||
#define RGU_ACTIVE1_I2C0_RST (1 << 16)
|
||||
#define RGU_ACTIVE1_I2C1_RST (1 << 17)
|
||||
#define RGU_ACTIVE1_SSP0_RST (1 << 18)
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@
|
|||
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* ICA IrDA Control Register (UART0,2,3 only) */
|
||||
/* ICA IrDA Control Register (USART0,2,3 only) */
|
||||
|
||||
#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */
|
||||
#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,109 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/lpc43_config.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART
|
||||
#if defined(CONFIG_LPC43_USART0) || defined(CONFIG_LPC43_UART1) || \
|
||||
defined(CONFIG_LPC43_USART2) || defined(CONFIG_LPC43_USART3)
|
||||
# define HAVE_UART 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? There should be at most one defined. It could be on
|
||||
* any UARTn, n=0,1,2,3
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART0)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC43_UART1)
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART2)
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART3)
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_USART0_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||
# undef HAVE_CONSOLE
|
||||
#endif
|
||||
|
||||
/* Check UART flow control (Only supported by UART1) */
|
||||
|
||||
# undef CONFIG_USART0_FLOWCONTROL
|
||||
# undef CONFIG_USART2_FLOWCONTROL
|
||||
# undef CONFIG_USART3_FLOWCONTROL
|
||||
#ifndef CONFIG_LPC43_UART1
|
||||
# undef CONFIG_UART1_FLOWCONTROL
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H */
|
||||
|
|
@ -1460,6 +1460,10 @@ configs/lpcxpresso-lpc1768
|
|||
is based on the NXP LPC1768. The Code Red toolchain is used by default.
|
||||
STATUS: Under development.
|
||||
|
||||
configs/lpc4330-xplorer
|
||||
NuttX port to the LPC4330-Xplorer board from NGX Technologies featuring
|
||||
the NXP LPC4330FET100 MCU
|
||||
|
||||
configs/m68322evb
|
||||
This is a work in progress for the venerable m68322evb board from
|
||||
Motorola. This OS is also built with the arm-elf toolchain*. STATUS:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
README
|
||||
^^^^^^
|
||||
|
||||
README for NuttX port to the NGX LPC4330-Xplorer board
|
||||
README for NuttX port to the LPC4330-Xplorer board from NGX Technologies
|
||||
featuring the NXP LPC4330FET100 MCU
|
||||
|
||||
Contents
|
||||
^^^^^^^^
|
||||
|
|
@ -275,10 +276,10 @@ LPC4330-Xplorer Configuration Options
|
|||
CONFIG_LPC43_USBHOST=n
|
||||
CONFIG_LPC43_USBOTG=n
|
||||
CONFIG_LPC43_USBDEV=n
|
||||
CONFIG_LPC43_UART0=y
|
||||
CONFIG_LPC43_USART0=y
|
||||
CONFIG_LPC43_UART1=n
|
||||
CONFIG_LPC43_UART2=n
|
||||
CONFIG_LPC43_UART3=n
|
||||
CONFIG_LPC43_USART2=n
|
||||
CONFIG_LPC43_USART3=n
|
||||
CONFIG_LPC43_CAN1=n
|
||||
CONFIG_LPC43_CAN2=n
|
||||
CONFIG_LPC43_SPI=n
|
||||
|
|
@ -304,16 +305,16 @@ LPC4330-Xplorer Configuration Options
|
|||
|
||||
LPC43xx specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the UART0).
|
||||
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the USART0).
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
CONFIG_UARTn_2STOP - Two stop bits
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
LPC43xx specific CAN device driver settings. These settings all
|
||||
require CONFIG_CAN:
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ CONFIG_ARCH=arm
|
|||
CONFIG_ARCH_ARM=y
|
||||
CONFIG_ARCH_CORTEXM4=y
|
||||
CONFIG_ARCH_CHIP=lpc43xx
|
||||
CONFIG_ARCH_CHIP_LPC4320=y
|
||||
CONFIG_ARCH_CHIP_LPC4330FET100=y
|
||||
CONFIG_ARCH_BOARD=lpc4330-xplorer
|
||||
CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=7982
|
||||
|
|
@ -106,10 +106,10 @@ CONFIG_LPC43_ETHERNET=n
|
|||
CONFIG_LPC43_USBHOST=n
|
||||
CONFIG_LPC43_USBOTG=n
|
||||
CONFIG_LPC43_USBDEV=n
|
||||
CONFIG_LPC43_UART0=y
|
||||
CONFIG_LPC43_USART0=y
|
||||
CONFIG_LPC43_UART1=n
|
||||
CONFIG_LPC43_UART2=n
|
||||
CONFIG_LPC43_UART3=n
|
||||
CONFIG_LPC43_USART2=n
|
||||
CONFIG_LPC43_USART3=n
|
||||
CONFIG_LPC43_CAN1=n
|
||||
CONFIG_LPC43_CAN2=n
|
||||
CONFIG_LPC43_SPI=n
|
||||
|
|
@ -135,51 +135,51 @@ CONFIG_LPC43_GPDMA=n
|
|||
#
|
||||
# LPC43xx specific serial device driver settings
|
||||
#
|
||||
# CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
# CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
# console and ttys0 (default is the UART1).
|
||||
# CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
# CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
# This specific the size of the receive buffer
|
||||
# CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
|
||||
# CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
# being sent. This specific the size of the transmit buffer
|
||||
# CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
# CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
# CONFIG_UARTn_2STOP - Two stop bits
|
||||
# CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
# CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
# CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
# CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
#
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_USART0_SERIAL_CONSOLE=y
|
||||
CONFIG_UART1_SERIAL_CONSOLE=n
|
||||
CONFIG_UART2_SERIAL_CONSOLE=n
|
||||
CONFIG_UART3_SERIAL_CONSOLE=n
|
||||
CONFIG_USART2_SERIAL_CONSOLE=n
|
||||
CONFIG_USART3_SERIAL_CONSOLE=n
|
||||
|
||||
CONFIG_UART0_TXBUFSIZE=256
|
||||
CONFIG_USART0_TXBUFSIZE=256
|
||||
CONFIG_UART1_TXBUFSIZE=256
|
||||
CONFIG_UART2_TXBUFSIZE=256
|
||||
CONFIG_UART3_TXBUFSIZE=256
|
||||
CONFIG_USART2_TXBUFSIZE=256
|
||||
CONFIG_USART3_TXBUFSIZE=256
|
||||
|
||||
CONFIG_UART0_RXBUFSIZE=256
|
||||
CONFIG_USART0_RXBUFSIZE=256
|
||||
CONFIG_UART1_RXBUFSIZE=256
|
||||
CONFIG_UART2_RXBUFSIZE=256
|
||||
CONFIG_UART3_RXBUFSIZE=256
|
||||
CONFIG_USART2_RXBUFSIZE=256
|
||||
CONFIG_USART3_RXBUFSIZE=256
|
||||
|
||||
CONFIG_UART0_BAUD=115200
|
||||
CONFIG_UART2_BAUD=115200
|
||||
CONFIG_UART3_BAUD=115200
|
||||
CONFIG_USART0_BAUD=115200
|
||||
CONFIG_UART1_BAUD=115200
|
||||
CONFIG_USART2_BAUD=115200
|
||||
CONFIG_USART3_BAUD=115200
|
||||
|
||||
CONFIG_UART0_BITS=8
|
||||
CONFIG_USART0_BITS=8
|
||||
CONFIG_UART1_BITS=8
|
||||
CONFIG_UART2_BITS=8
|
||||
CONFIG_UART3_BITS=8
|
||||
CONFIG_USART2_BITS=8
|
||||
CONFIG_USART3_BITS=8
|
||||
|
||||
CONFIG_UART0_PARITY=0
|
||||
CONFIG_USART0_PARITY=0
|
||||
CONFIG_UART1_PARITY=0
|
||||
CONFIG_UART2_PARITY=0
|
||||
CONFIG_UART3_PARITY=0
|
||||
CONFIG_USART2_PARITY=0
|
||||
CONFIG_USART3_PARITY=0
|
||||
|
||||
CONFIG_UART0_2STOP=0
|
||||
CONFIG_USART0_2STOP=0
|
||||
CONFIG_UART1_2STOP=0
|
||||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
CONFIG_USART2_2STOP=0
|
||||
CONFIG_USART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC43xx specific PHY/Ethernet device driver settings
|
||||
|
|
|
|||
|
|
@ -314,19 +314,6 @@ EXTERN int stm32_lm75initialize(FAR const char *devpath);
|
|||
EXTERN xcpt_t stm32_lm75attach(xcpt_t irqhandler);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_pmbuttons
|
||||
*
|
||||
* Description:
|
||||
* Configure all the buttons of the STM3210e-eval board as EXTI,
|
||||
* so any button is able to wakeup the MCU from the PM_STANDBY mode
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_PM) && defined(CONFIG_IDLE_CUSTOM)
|
||||
EXTERN void up_pmbuttons(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -304,6 +304,19 @@ void stm32_deselectlcd(void);
|
|||
|
||||
#endif /* CONFIG_STM32_FSMC */
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_pmbuttons
|
||||
*
|
||||
* Description:
|
||||
* Configure all the buttons of the STM3210e-eval board as EXTI, so any button is
|
||||
* able to wakeup the MCU from the PM_STANDBY mode
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_PM) && defined(CONFIG_IDLE_CUSTOM)
|
||||
EXTERN void up_pmbuttons(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: up_unregisterbuttons
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue