Clean up a few PIC32 link errors
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3631 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
parent
e40881caf0
commit
c7a3fc3b02
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@ -160,14 +160,14 @@
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/* Register Number: 12 Sel: 1 Name: IntCtl */
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#define CP0_CONFIG_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
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#define CP0_CONFIG_VS_MASK (0x1f << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_0BYTES (0x00 << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_32BYTES (0x01 << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_64BYTES (0x02 << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_128BYTES (0x04 << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_256BYTES (0x08 << CP0_CONFIG_VS_SHIFT)
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# define CP0_CONFIG_VS_512BYTES (0x10 << CP0_CONFIG_VS_SHIFT)
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#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
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#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
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/* Register Number: 12 Sel: 2 Name: SRSCtl */
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@ -46,6 +46,19 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifdef CONFIG_PIC32MX_MVEC0
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# error "Multi-vectors not supported"
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# ifndef CONFIG_PIC32MX_EBASE
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# error "EBASE address provided" /* Should come from the linker script */
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# endif
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# ifndef CONFIG_PIC32MX_VECTORSPACING
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# error "No vector spacing provided"
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# endif
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#endif
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/* Linker memory organization ***********************************************/
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/* Data memory is organized as follows:
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*
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* 1) Possible space reserved for debug data
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@ -261,15 +274,17 @@ __start:
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/* Initialize EBase register */
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la t1, _ebase_address
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#ifdef CONFIG_PIC32MX_MVEC
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la t1, CONFIG_PIC32MX_EBASE
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mtc0 t1, PIC32MX_CP0_EBASE
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/* Initialize IntCtl register */
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la t1, _vector_spacing
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li t2, 0 /* Clear t2 */
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ins t2, t1, 5, 5 /* Shift value to VS field */
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li t1, CONFIG_PIC32MX_VECTORSPACING
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li t2, 0
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ins t2, t1, CP0_INTCTL_VS_SHIFT, 5
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mtc0 t2, PIC32MX_CP0_INTCTL
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#endif
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/* Initialize CAUSE registers
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* - Enable counting of Count register (DC = 0)
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@ -296,17 +311,17 @@ __start:
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*/
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mfc0 t0, PIC32MX_CP0_CONFIG
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ext t1, t0, 22,1 /* Extract UDI from Config register */
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sll t1, t1, 17 /* Move UDI to Status.CEE location */
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ext t1, t0, 22,1 /* Extract UDI from Config register */
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sll t1, t1, 17 /* Move UDI to Status.CEE location */
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mfc0 t0, PIC32MX_CP0_STATUS
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and t0, t0, 0x00580000 /* Preserve SR, NMI, and BEV */
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or t0, t1, t0 /* Include Status.CEE (from UDI) */
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and t0, t0, 0x00580000 /* Preserve SR, NMI, and BEV */
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or t0, t1, t0 /* Include Status.CEE (from UDI) */
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mtc0 t0, PIC32MX_CP0_STATUS
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/* Initialize Status BEV for normal exception vectors */
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mfc0 t0, PIC32MX_CP0_STATUS
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and t0, t0, 0xffbfffff # Clear BEV
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and t0, t0, ~CP0_STATUS_BEV /* Clear BEV */
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mtc0 t0, PIC32MX_CP0_STATUS
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/* Start NuttX. We do this via a thunk in the text section so that
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@ -364,11 +379,11 @@ halt:
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nop
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.end __start_nuttx
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/* This global variable is unsigned long g_heapbase and is exported
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/* This global variable is unsigned int g_heapbase and is exported
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* here only because of its coupling to idle thread stack.
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*/
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.data
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.sdata
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.align 4
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.globl g_heapbase
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.type g_heapbase, object
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@ -48,18 +48,18 @@ MEMORY
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*
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* REGION PHYSICAL KSEG SIZE
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* DESCRIPTION START ADDR (BYTES)
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* ------------- ---------- ------ ---------------
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* ------------- ---------- ------ ----------------------
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* Exceptions:*
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* Reset 0x1fc00000 KSEG1 512
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* TLB Refill 0x1fc00200 KSEG1 256
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* Cache Error 0x1fc00300 KSEG1 256
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* Others 0x1fc00380 KSEG1 256
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* Interrupt 0x1fc00400 KSEG1 128
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* JTAG 0x1fc00480 KSEG1 16
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* Startup logic 0x1fc00490 KSEG0 4096-896-256-16
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* Exceptions 0x1fc01000 KSEG0 4096
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* Debug code 0x1fc02000 KSEG1 4096-16
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* DEVCFG3-0 0x1fc02ff0 KSEG1 16
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* Reset 0x1fc00000 KSEG1 512 512
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* TLB Refill 0x1fc00200 KSEG1 256 768
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* Cache Error 0x1fc00300 KSEG1 128 896
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* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
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* Interrupt 0x1fc00400 KSEG1 128 1152
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* JTAG 0x1fc00480 KSEG1 16 1168
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* Startup logic 0x1fc00490 KSEG0 4096-1168 4096 (4Kb)
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* Exceptions 0x1fc01000 KSEG0 4096 8192 (8Kb)
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* Debug code 0x1fc02000 KSEG1 4096-16 12272
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* DEVCFG3-0 0x1fc02ff0 KSEG1 16 12288 (12Kb)
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*
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* Exceptions assme:
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*
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@ -70,9 +70,9 @@ MEMORY
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*/
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kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 896
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kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 256
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kseg1_intexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
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kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
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kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
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kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 4096-1168
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kseg0_excptmem (rx) : ORIGIN = 0x9fc01000, LENGTH = 4096
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kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
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@ -194,7 +194,7 @@ SECTIONS
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/* RAM functions are positioned at the beginning of RAM so that
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* they can be guaranteed to satisfy the 2Kb alignment requirement.
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*/
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/*
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.ramfunc ALIGN(2K) :
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{
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_sramfunc = ABSOLUTE(.);
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@ -207,7 +207,7 @@ SECTIONS
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_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
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_bmxdudba_address = LENGTH(kseg1_datamem) ;
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_bmxdupba_address = LENGTH(kseg1_datamem) ;
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*/
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.dbg_data (NOLOAD) :
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{
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. += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);
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