I2S register bit definitions
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2719 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -86,33 +86,95 @@
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/* Register bit definitions *********************************************************/
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/* Digital Audio Output Register */
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#define I2S_DAO_
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#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
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#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT)
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# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT)
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# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT)
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# define I2S_DAO_WDWID_32BITS (2 << I2S_DAO_WDWID_SHIFT)
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#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */
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#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
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#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
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#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */
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#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
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#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
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#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
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/* Bits 16-31: Reserved */
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/* Digital Audio Input Register */
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#define I2S_DAI_
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/* Transmit FIFO */
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#define I2S_TXFIFO_
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/* Receive FIFO */
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#define I2S_RXFIFO_
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#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
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#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT)
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# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT)
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# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT)
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# define I2S_DAI_WDWID_32BITS (2 << I2S_DAI_WDWID_SHIFT)
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#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */
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#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
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#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
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#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */
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#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
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#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
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/* Bits 15-31: Reserved */
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/* Transmit FIFO: 8 × 32-bit transmit FIFO */
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/* Receive FIFO: 8 × 32-bit receive FIFO */
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/* Status Feedback Register */
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#define I2S_STATE_
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/* DMA Configuration Register 1 */
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#define I2S_DMA1_
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/* DMA Configuration Register 2 */
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#define I2S_DMA2_
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#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */
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#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */
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#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */
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/* Bits 3-7: Reserved */
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#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */
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#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT)
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/* Bits 12-15: Reserved */
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#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
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#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
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/* Bits 20-31: Reserved */
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/* DMA Configuration Register 1 and 2 */
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#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
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#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */
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/* Bits 3-7: Reserved */
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#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
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#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT)
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/* Bits 12-15: Reserved */
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#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
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#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
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/* Bits 20-31: Reserved */
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/* Interrupt Request Control Register */
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#define I2S_IRQ_
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/* Transmit MCLK divider */
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#define I2S_TXRATE_
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/* Receive MCLK divider */
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#define I2S_RXRATE_
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/* Transmit bit rate divider */
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#define I2S_TXBITRATE_
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/* Receive bit rate divider */
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#define I2S_RXBITRATE_
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/* Transmit mode control */
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#define I2S_TXMODE_
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/* Receive mode control */
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#define I2S_RXMODE_
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#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
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#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */
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/* Bits 3-7: Reserved */
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#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */
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#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT)
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/* Bits 12-15: Reserved */
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#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
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#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
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/* Bits 20-31: Reserved */
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/* Transmit and Receive MCLK divider */
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#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
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#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT)
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#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */
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#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT)
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/* Bits 16-31: Reserved */
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/* Transmit and received bit rate divider */
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#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
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#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
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/* Bits 6-31: Reserved */
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/* Transmit and Receive mode control */
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#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
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#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT)
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# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
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# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
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# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
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#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
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#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
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/* Bits 4-31: Reserved */
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/************************************************************************************
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* Public Types
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