Completes coding portion of basic PIC32 port
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3637 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
269aa7e0a5
commit
beb5ab7db2
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@ -61,8 +61,8 @@ endif
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# Required PIC32MX files
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CHIP_ASRCS =
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CHIP_CSRCS = pic32mx-irq.c pic32mx-clockconfig.c pic32mx-decodeirq.c pic32mx-dobev.c \
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pic32mx-lowconsole.c pic32mx-lowinit.c pic32mx-serial.c pic32mx-timerisr.c
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CHIP_CSRCS = pic32mx-irq.c pic32mx-decodeirq.c pic32mx-dobev.c pic32mx-lowconsole.c \
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pic32mx-lowinit.c pic32mx-serial.c pic32mx-timerisr.c
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# Configuration-dependent PIC32MX files
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@ -0,0 +1,166 @@
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-bmx.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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||||
* used to endorse or promote products derived from this software
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||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */
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#define PIC32MX_BMX_CONCLR_OFFSET 0x0000 /* Configuration Clear Register */
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#define PIC32MX_BMX_CONSET_OFFSET 0x0004 /* Configuration Set Register */
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#define PIC32MX_BMX_CONINV_OFFSET 0x0008 /* Configuration Invert Register */
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#define PIC32MX_BMX_DKPBA_OFFSET 0x001c /* Data RAM Kernel Program Base Address Register */
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#define PIC32MX_BMX_DKPBACLR_OFFSET 0x0010 /* Data RAM Kernel Program Base Address Clear Register */
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#define PIC32MX_BMX_DKPBASET_OFFSET 0x0014 /* Data RAM Kernel Program Base Address Set Register */
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#define PIC32MX_BMX_DKPBAINV_OFFSET 0x0018 /* Data RAM Kernel Program Base Address Invert Register */
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#define PIC32MX_BMX_DUDBA_OFFSET 0x002c /* Data RAM User Data Base Address Register */
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#define PIC32MX_BMX_DUDBACLR_OFFSET 0x0020 /* Data RAM User Data Base Address Clear Register */
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#define PIC32MX_BMX_DUDBASET_OFFSET 0x0024 /* Data RAM User Data Base Address Set Register */
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#define PIC32MX_BMX_DUDBAINV_OFFSET 0x0028 /* Data RAM User Data Base Address Invert Register */
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#define PIC32MX_BMX_DUPBA_OFFSET 0x003c /* Data RAM User Program Base Address Register */
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#define PIC32MX_BMX_DUPBACLR_OFFSET 0x0030 /* Data RAM User Program Base Address Clear Register */
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#define PIC32MX_BMX_DUPBASET_OFFSET 0x0034 /* Data RAM User Program Base Address Set Register */
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#define PIC32MX_BMX_DUPBAINV_OFFSET 0x0038 /* Data RAM User Program Base Address Invert Register */
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#define PIC32MX_BMX_DRMSZ_OFFSET 0x0040 /* Data RAM Size Register */
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#define PIC32MX_BMX_PUPBA_OFFSET 0x0050 /* Program Flash (PFM) User Program Base Address Register */
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#define PIC32MX_BMX_PUPBACLR_OFFSET 0x0054 /* Program Flash (PFM) User Program Base Address Clear Register */
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#define PIC32MX_BMX_PUPBASET_OFFSET 0x0058 /* Program Flash (PFM) User Program Base Address Set Register */
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#define PIC32MX_BMX_PUPBINVA_OFFSET 0x005c /* Program Flash (PFM) User Program Base Address Invert Register */
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#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */
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#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET)
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#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET)
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#define PIC32MX_BMX_CONSET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONSET_OFFSET)
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#define PIC32MX_BMX_CONINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONINV_OFFSET)
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#define PIC32MX_BMX_DKPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBA_OFFSET)
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#define PIC32MX_BMX_DKPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBACLR_OFFSET)
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#define PIC32MX_BMX_DKPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBASET_OFFSET)
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#define PIC32MX_BMX_DKPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBAINV_OFFSET)
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#define PIC32MX_BMX_DUDBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBA_OFFSET)
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#define PIC32MX_BMX_DUDBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBACLR_OFFSET)
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#define PIC32MX_BMX_DUDBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBASET_OFFSET)
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#define PIC32MX_BMX_DUDBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBAINV_OFFSET)
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#define PIC32MX_BMX_DUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBA_OFFSET)
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#define PIC32MX_BMX_DUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBACLR_OFFSET)
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#define PIC32MX_BMX_DUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBASET_OFFSET)
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#define PIC32MX_BMX_DUPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBAINV_OFFSET)
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#define PIC32MX_BMX_DRMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DRMSZ_OFFSET)
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#define PIC32MX_BMX_PUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBA_OFFSET)
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#define PIC32MX_BMX_PUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBACLR_OFFSET)
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#define PIC32MX_BMX_PUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBASET_OFFSET)
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#define PIC32MX_BMX_PUPBINVA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBINVA_OFFSET)
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#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET)
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#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET)
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/* Register Bit-Field Definitions ***********************************************************/
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/* Configuration Register */
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#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */
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#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT)
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# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */
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#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */
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#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */
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#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */
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#define BMX_CON_BMXERRDMA (1 << 18) /* Bit 18: Bus error from DMA */
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#define BMX_CON_BMXERRICD (1 << 19) /* Bit 19: Enable bus error from ICD debug unit */
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#define BMX_CON_BMXERRIXI (1 << 20) /* Bit 20: Enable bus error from IXI */
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#define BMX_CON_BMXCHEDMA (1 << 26) /* Bit 26: BMX PFM cacheability for DMA accesses */
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/* Data RAM Kernel Program Base Address Register */
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#define BMX_DKPBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM User Data Base Address Register */
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#define BMX_DUDBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM User Program Base Address Register */
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#define BMX_DUPBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM Size Register -- 32-bit size value */
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/* Program Flash (PFM) User Program Base Address Register */
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#define BMX_PUPBA_MASK 0x000fffff /* Bits 0-19 */
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/* Program Flash Size Register -- 32-bit size value */
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/* Boot Flash Size Register -- 32-bit size value */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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#ifndef __ASSEMBLY__
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/********************************************************************************************
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* Inline Functions
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********************************************************************************************/
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/********************************************************************************************
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* Public Function Prototypes
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********************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H */
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@ -106,32 +106,41 @@
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/* Pre-fetch cache control register */
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#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: xx */
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#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */
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#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT)
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#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: xx */
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# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */
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#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */
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#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT)
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#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: xx */
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# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */
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# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */
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# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */
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# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */
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#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */
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#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT)
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#define CHE_CON_CHECOH (1 << 16) /* Bit 16: xx */
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# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */
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# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */
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# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */
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# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */
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#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */
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/* Pre-fetch cache access register */
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#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: xx */
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#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: Cache line index */
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#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT)
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#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: xx */
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#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: Cache access enable */
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/* Pre-fetch cache tag register */
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#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: xx */
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#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: xx */
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#define CHE_TAG_LVALID (1 << 3) /* Bit 3: xx */
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#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: xx */
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#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: Line type */
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#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: Line lock */
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#define CHE_TAG_LVALID (1 << 3) /* Bit 3: Line valid */
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#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: Line tag address */
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#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT)
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#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: xx */
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#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: Line tag address boot */
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/* Pre-fetch cache tag mask register */
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#define CHE_MSK_SHIFT (5) /* Bits 5-15: xx */
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#define CHE_MSK_SHIFT (5) /* Bits 5-15: Line mask */
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#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT)
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/* Cache word 0-3 register -- 32-bit cache line data */
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@ -1,93 +0,0 @@
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/**************************************************************************
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* arch/mips/src/pic32mx/pic32mx-clockconfig.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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**************************************************************************/
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/**************************************************************************
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* Included Files
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**************************************************************************/
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#include <nuttx/config.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "pic32mx-config.h"
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#include "pic32mx-internal.h"
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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/**************************************************************************
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* Private Types
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**************************************************************************/
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/**************************************************************************
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* Private Function Prototypes
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**************************************************************************/
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/**************************************************************************
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* Global Variables
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**************************************************************************/
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/**************************************************************************
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* Private Variables
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**************************************************************************/
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/**************************************************************************
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* Private Functions
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**************************************************************************/
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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/**************************************************************************
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* Name: pic32mx_clockconfig
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*
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* Description:
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* Called by pic32mx_lowinitto initialize the PIC32MX clocking using the
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* settings in board.h.
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*
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**************************************************************************/
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void pic32mx_clockconfig(void)
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{
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# warning "Missing logic"
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}
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@ -129,17 +129,6 @@ extern "C" {
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EXTERN void pic32mx_lowinit(void);
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/************************************************************************************
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* Name: pic32mx_clockconfig
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*
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* Description:
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* Called by pic32mx_lowinit to initialize the PIC32MX clocking using the settings
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* in board.h.
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*
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************************************************************************************/
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EXTERN void pic32mx_clockconfig(void);
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/************************************************************************************
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* Name: pic32mx_lowsetup
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*
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@ -1,4 +1,4 @@
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/**************************************************************************
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/****************************************************************************
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* arch/mips/src/pic32/pic32mx-lowinit.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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@ -31,58 +31,161 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
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**************************************************************************/
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****************************************************************************/
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/**************************************************************************
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/****************************************************************************
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* Included Files
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**************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <arch/pic32mx/cp0.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "pic32mx-internal.h"
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#include "pic32mx-bmx.h"
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#include "pic32mx-che.h"
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/**************************************************************************
|
||||
* Private Definitions
|
||||
**************************************************************************/
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Maximum Frequencies ******************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
#define MAX_FLASH_HZ 30000000 /* Maximum FLASH speed (Hz) */
|
||||
#define MAX_PBCLOCK 80000000 /* Max peripheral bus speed (Hz) */
|
||||
|
||||
/* Sanity checks ************************************************************/
|
||||
|
||||
/* Make sure that the selected clock parameters are sane */
|
||||
|
||||
#define CALC_SYSCLOCK (((BOARD_POSC_FREQ / BOARD_PLL_IDIV) * BOARD_PLL_MULT) / BOARD_PLL_ODIV)
|
||||
#if CALC_SYSCLOCK != BOARD_CPU_CLOCK
|
||||
# error "Bad BOARD_CPU_CLOCK calculcation in board.h"
|
||||
#endif
|
||||
|
||||
#define CALC_PBCLOCK (CALC_SYSCLOCK / BOARD_PBDIV)
|
||||
#if CALC_PBCLOCK != BOARD_PBCLOCK
|
||||
# error "Bad BOARD_PBCLOCK calculcation in board.h"
|
||||
#endif
|
||||
|
||||
#if CALC_PBCLOCK > MAX_PBCLOCK
|
||||
# error "PBCLOCK exceeds maximum value"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Global Variables
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Private Variables
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: pic32mx_waitstates
|
||||
*
|
||||
* Description:
|
||||
* Configure the optimal number of FLASH wait states.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void pic32mx_waitstates(void)
|
||||
{
|
||||
unsigned int nwaits;
|
||||
unsigned int residual;
|
||||
|
||||
/* Disable DRM wait states */
|
||||
|
||||
putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR);
|
||||
|
||||
/* Configure pre-fetch cache FLASH wait states */
|
||||
|
||||
residual = BOARD_CPU_CLOCK;
|
||||
nwaits = 0;
|
||||
|
||||
while(residual > MAX_FLASH_HZ)
|
||||
{
|
||||
nwaits++;
|
||||
residual -= MAX_FLASH_HZ;
|
||||
}
|
||||
DEBUGASSERT(nwaits < 8);
|
||||
|
||||
/* Set the FLASH wait states -- clearing all other bits! */
|
||||
|
||||
putreg32(nwaits, PIC32MX_CHE_CON);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mx_cache
|
||||
*
|
||||
* Description:
|
||||
* Enable caching.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void pic32mx_cache(void)
|
||||
{
|
||||
register uint32_t regval;
|
||||
|
||||
/* Enable caching on all regions */
|
||||
|
||||
regval = getreg32(PIC32MX_CHE_CON);
|
||||
regval |= CHE_CON_PREFEN_ALL;
|
||||
putreg32(regval, PIC32MX_CHE_CON);
|
||||
|
||||
/* Enable cache on KSEG 0 in the CP0 CONFIG register*/
|
||||
|
||||
asm("\tmfc0 %0,$16,0\n" : "=r"(regval));
|
||||
regval &= ~CP0_CONFIG_K23_MASK;
|
||||
regval |= CP0_CONFIG_K23_CACHEABLE;
|
||||
asm("\tmtc0 %0,$16,0\n" : : "r" (regval));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: pic32mx_lowinit
|
||||
*
|
||||
* Description:
|
||||
* This performs basic low-level initialization of the system.
|
||||
*
|
||||
**************************************************************************/
|
||||
* Assumptions:
|
||||
* Interrupts have not yet been enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void pic32mx_lowinit(void)
|
||||
{
|
||||
/* Initialize MCU clocking */
|
||||
/* Initialize FLASH wait states */
|
||||
|
||||
pic32mx_clockconfig();
|
||||
pic32mx_waitstates();
|
||||
|
||||
/* Enable caching */
|
||||
|
||||
pic32mx_cache();;
|
||||
|
||||
/* Initialize a console (probably a serial console) */
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
|
||||
|
||||
/* PLL configuration and resulting CPU clock.
|
||||
* CPU_CLOCK = ((POSC_XTAL / IDIV) * MULT) / ODIV
|
||||
* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
|
||||
*/
|
||||
|
||||
#define BOARD_PLL_IDIV 2 /* PLL input divider */
|
||||
|
|
@ -68,7 +68,7 @@
|
|||
* USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
|
||||
*/
|
||||
|
||||
#define BOARD_UPLL_IDIV 16 /*2*/ /* USB PLL divider (revisit) */
|
||||
#define BOARD_UPLL_IDIV 16 /* 2*/ /* USB PLL divider (revisit) */
|
||||
#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / (2*48MHz/24)) */
|
||||
|
||||
/* Peripheral clock is divided down from CPU clock.
|
||||
|
|
|
|||
Loading…
Reference in New Issue