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PIC32 start kit port builds successfully 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4037 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2011-10-10 22:40:59 +00:00
parent 95ed0d2b4f
commit bdf638546d
9 changed files with 1035 additions and 935 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
nuttx/ChangeLog
View File

@ -2150,11 +2150,12 @@
* arch/arm/stm32/Make.defs: Don't build stm32_rtc.c if CONFIG_RTC is not
selected. Doing so will cause errors if other configuration dependencies
are not met
are not met.
* configs/stm3210e-eval/src/up_lcd.c: Color corrections for SPFD5408B LCD
do not work with R61580 LCD.
* configs/pic32-starterkit: Beginning of a configuratin for the Microchip
PIC32 Ethernet Starter Kit.
* configs/pic32-starterkit: Beginning of a configuration for the Microchip
PIC32 Ethernet Starter Kit. Hmmm.. I don't have a clue how to test this
with no serial port?!
* lib/stdio/lib_fclose.c: fclose() always returns an error (EOF) when it
closes a read-only file. This is because it calls flush() which will
fail on read-only files. No harm is done other that a bad value is

114
nuttx/arch/mips/include/pic32mx/chip.h
View File

@ -67,7 +67,7 @@
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -97,7 +97,7 @@
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -126,8 +126,8 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -154,10 +154,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -184,10 +183,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -214,10 +212,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -244,10 +241,9 @@
# define CHIP_NDMACH 0 /* No programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -274,10 +270,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -304,10 +299,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -334,10 +328,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -364,10 +357,9 @@
# define CHIP_NDMACH 0 /* No programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -394,10 +386,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -424,10 +415,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -454,10 +444,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -484,10 +473,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -514,10 +502,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -544,10 +531,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -576,7 +562,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -605,7 +591,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -634,7 +620,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -663,7 +649,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -692,7 +678,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -721,7 +707,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -750,7 +736,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -779,7 +765,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -808,7 +794,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -837,7 +823,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -866,7 +852,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -895,7 +881,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -924,7 +910,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -953,7 +939,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -982,7 +968,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1011,7 +997,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1040,7 +1026,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1069,7 +1055,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1098,7 +1084,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1127,7 +1113,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1156,7 +1142,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -1185,7 +1171,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1214,7 +1200,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1243,7 +1229,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1272,7 +1258,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -1301,7 +1287,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1330,7 +1316,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1359,7 +1345,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */

1675
nuttx/arch/mips/src/pic32mx/pic32mx-config.h
View File

File diff suppressed because it is too large Load Diff

15
nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c
View File

@ -243,8 +243,21 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN |
UART_MODE_SIDL | UART_MODE_ON);
/* Configure the FIFOs:
*
* RX: Interrupt at 6 of 8 (for 8-deep FIFO) or 3 o 4 (4-deep FIFO)
* TX: Interrupt on FIFO not full
* Invert transmit polarity.
*/
#ifdef UART_STA_URXISEL_RXB6
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_MASK | UART_STA_URXISEL_RXBF);
UART_STA_UTXINV | UART_STA_UTXISEL_TXBNF | UART_STA_URXISEL_RXB6);
#else
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_TXBNF | UART_STA_URXISEL_RXB3);
#endif
/* Configure the FIFO interrupts */

4
nuttx/configs/pcblogic-pic32mx/include/board.h
View File

@ -3,7 +3,7 @@
* include/arch/board/board.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -69,7 +69,7 @@
*/
#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */
#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / (2*48MHz/24)) */
#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */
/* Peripheral clock is divided down from CPU clock.
* PBCLOCK = CPU_CLOCK / PBDIV

125
nuttx/configs/pic32-starterkit/README.txt
View File

@ -57,9 +57,10 @@ Contents
PIC32MX795F512L Pin Out
=======================
LEFT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
PIN CONFIGURATIONS SIGNAL NAME
(Table 1-1) (User Guide)
LEFT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
--- ---------------------------------- -------------------------- -----------------------------------------------
PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS
(Family Data Sheet Table 1-1) (Starter Kit User Guide)
--- ---------------------------------- -------------------------- -----------------------------------------------
1 RG15/AERXERR ERXERR Ethernet RX_ER/MDIX_IN
2 VDD P32_VDD ---
@ -106,9 +107,10 @@ PIN CONFIGURATIONS SIGNAL NAME
24 AN1/CN3/PGEC1/RB1 PGC1/AN1/CN3/RB1 J2 pin 70 (A/D)
25 AN0/CN2/PGED1/RB0 PGD1/AN0/CN2/RB0 J2 pin 72 (A/D)
BOTTOM SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
PIN CONFIGURATIONS SIGNAL NAME
(Table 1-1) (User Guide)
BOTTOM SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
--- ---------------------------------- -------------------------- -----------------------------------------------
PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS
(Family Data Sheet Table 1-1) (Starter Kit User Guide)
--- ---------------------------------- -------------------------- -----------------------------------------------
26 AN6/OCFA/PGEC2/RB6 PIC32_PGC2 PIC32MX440F512H debug processor
J2 pin 128 (ICSP)
@ -130,7 +132,7 @@ PIN CONFIGURATIONS SIGNAL NAME
38 RA1/TCK TCK/RA1 PIC32MX440F512H debug processor
J2 pin 124 (JTAG/GPIO)
39 AC1TX/RF13/SCK4/U2RTS/U5TX SCM3D/BCLK2/RF13 J2 pin 106 (UART2)
40 AC1RX/RF12/SS4/U2CTS/U5RX SCM3C/FR12 J2 pin 108 (UART2)
40 AC1RX/RF12/SS4/U2CTS/U5RX SCM3C/RF12 J2 pin 108 (UART2)
41 PMA11/AECRS/AN12/ERXD0/RB12 PMPA11/AN12/RB12 J2 pin 105 (PMP address)
42 PMA10/AECOL/AN13/ERXD1/RB13 PMPA10/AN13/RB13 J2 pin 107 (PMP address)
43 PMA1/AETXD3/AN14/ERXD2/PMALH/RB14 PMPA1/AN14/RB14 J2 pin 127 (PMP address)
@ -145,9 +147,10 @@ PIN CONFIGURATIONS SIGNAL NAME
50 PMA8/CN18/RF5/SCL5/SDO4/U2TX PMPA8/SCM3B/CN18/RF5 J2 pin 111 (PMP address)
J2 pin 112 (UART2)
RIGHT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
PIN CONFIGURATIONS SIGNAL NAME
(Table 1-1) (User Guide)
RIGHT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
--- ---------------------------------- -------------------------- -----------------------------------------------
PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS
(Family Data Sheet Table 1-1) (Starter Kit User Guide)
--- ---------------------------------- -------------------------- -----------------------------------------------
75 VSS (grounded)
74 CN0/RC14/SOSCO/T1CK SOSC0/T1CK/CN0/RC14 32kHz Oscillator, J2 pin (timer)
@ -157,7 +160,7 @@ PIN CONFIGURATIONS SIGNAL NAME
72 OC1/INT0/RD0/SDO1 SDO1/INT0/OC1/RD0 User LED D4 (high illuminates)
J2 pin 87 (EXT_INT)
J2 pin 95 (SPI1)
J2 pin 46 (OC/PWN_
J2 pin 46 (OC/PWM)
71 PMA14/AEMDC/EMDC/IC4/PMCS1/RD11 EMDC Ethernet MDC
70 PMA15/IC3/PMCS2/RD10/SCK1 SCK1/IC3/PMPCS2/RD10 J2 pin 29 (PMP control)
J2 pin 91 (SPI1)
@ -183,9 +186,10 @@ PIN CONFIGURATIONS SIGNAL NAME
52 RF2/SDA3/SDI3/U1RX SCM1A/RF2 J2 pin 88 (UART1)
51 RF3/USBID USBID/RF3 Device OTG port (J5)
TOP SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
PIN CONFIGURATIONS SIGNAL NAME
(Table 1-1) (User Guide)
TOP SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
--- ---------------------------------- -------------------------- -----------------------------------------------
PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS
(Family Data Sheet Table 1-1) (Starter Kit User Guide)
--- ---------------------------------- -------------------------- -----------------------------------------------
100 PMD4/RE4 PMPD4/RE4 J2 pin 15 (PMP data)
99 PMD3/RE3 PMPD3/RE3 J2 pin 17 (PMP data)
@ -223,6 +227,99 @@ PIN CONFIGURATIONS SIGNAL NAME
MEB Connector
=============
PIC32 SIGNAL PIN CONNECTION
-------------------------- ------- ----------------------------------
PMPD0 pin 23 Graphics Controller (SSD1926)
PMPD1 pin 21 8-bit or 16-bit Data Bus
PMPD2 pin 19
PMPD3 pin 17
PMPD4 pin 15
PMPD6 pin 9
PMPD7 pin 7
-------------------------- ------- ----------------------------------
PMPD8 pin 10 Graphics Controller (SSD1926)
PMPD9 pin 14 16-bit Data Bus
PMPD10 pin 16
PMPD11 pin 18
PMPD12 pin 20
PMPD13 pin 22
PMPD14 pin 24
PMPD15 pin 26
-------------------------- ------- ----------------------------------
Graphics Controller (SSD1926)
RG13 pin 8 Chip select
RB10 pin 101 Register select
RC3 pin 39 Wait line
RA10 pin 115 Reset (see MRF24WBOMA and PICtail)
-------------------------- ------- ----------------------------------
Touchscreen
RB11 pin 103 X+
RB12 pin 105 Y-
RB13 pin 107 X-
RB14 pin 127 Y+
-------------------------- ------- ----------------------------------
Joystick
CN2/RB0 pin 72 Left
CN3/RB1 pin 70 Up
CN5/RB3 pin 66 Down
CN6/RB4 pin 64 Right
CN12/RB15 pin 36 Fire
-------------------------- ------- ----------------------------------
LEDs
RD1 pin 44 LED1
RD2 pin 42 LED2
RD3 pin 40 LED3
RC1 pin 35 LED4
RC2 pin 37 LED5
-------------------------- ------- ----------------------------------
SDA2 pin 74 I2C2 bus for BMA150, MCHP24LC08
SCL2 pin 76 and WM8731 (see also MRF24WBOMA)
-------------------------- ------- ----------------------------------
SCK1 pin 91 SPI1 bus for WM8731
SDI1 pin 93
SDO1 pin 95
-------------------------- ------- ----------------------------------
RA6 pin 4 CPLD
RA7 pin 6
RG12 pin 5
RG14 pin 3
SCK2 pin 45 (see MRF24WBOMA)
SDI2 pin 47 (see MRF24WBOMA)
SDO2 pin 49 (see MRF24WBOMA)
RG9 pin 51 (see MRF24WBOMA)
SCK3A pin 106 (see PICtail)
SDI3A pin 110 (see PICtail)
SDO3A pin 112 (see PICtail)
RF12 pin 108 (see PICtail)
~SSI pin 97 (see PICtail)
RD9 pin 54
-------------------------- ------- ----------------------------------
INT3 pin 81 MRF24WBOMA
RA10 pin 115 (also Graphics Controller and PICtail)
RB8 pin 71
-------------------------- ------- ----------------------------------
PICtail J5
SDA2 pin 74 I2C2 bus (see above)
SCL2 pin 76 I2C2 bus (see above)
SCK2 pin 45 (see CPLD)
SDI2 pin 47 (see CPLD)
SDO2 pin 49 (see CPLD)
RG9 pin 51 (see CPLD)
U1RX pin 88
U1TX pin 90
~U1RTS pin 92
~U1CTS pin 94
RB9 pin 73
RA10 pin 115 Reset (see Graphics controller and MRF24WBOMA)
INT1 pin 85
SCL1 pin 84
SDA1 pin 86 (see CPLD)
~SSI pin 97 (see CPLD)
U2RX pin 110 (see CPLD)
U2TX pin 112 (see CPLD)
~U2RTS pin 106 (see CPLD)
~U2CTS pin 108 (see CPLD)
Toolchains
==========

22
nuttx/configs/pic32-starterkit/include/board.h
View File

@ -51,32 +51,32 @@
/* Clocking *****************************************************************/
/* Crystal frequencies */
#define BOARD_POSC_FREQ 20000000 /* Primary OSC XTAL frequency (20MHz) */
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
/* PLL configuration and resulting CPU clock.
* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
*/
#define BOARD_PLL_IDIV 5 /* PLL input divider */
#define BOARD_PLL_MULT 15 /* PLL multiplier */
#define BOARD_PLL_ODIV 1 /* PLL output divider */
#define BOARD_PLL_IDIV 2 /* PLL input divider */
#define BOARD_PLL_MULT 20 /* PLL multiplier */
#define BOARD_PLL_ODIV 1 /* PLL output divider */
#define BOARD_CPU_CLOCK 60000000 /* CPU clock (60MHz = (20MHz / 5) * 15 / 1) */
#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */
/* USB PLL configuration.
* USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
*/
#define BOARD_UPLL_IDIV 5 /* USB PLL divider */
#define BOARD_USB_CLOCK 48000000 /* USB clock ((20MHz / 5) * 24) */
#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */
#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */
/* Peripheral clock is *not* divided down from CPU clock.
/* Peripheral clock is divided down from CPU clock.
* PBCLOCK = CPU_CLOCK / PBDIV
*/
#define BOARD_PBDIV 1 /* Peripheral clock divisor (PBDIV) */
#define BOARD_PBCLOCK 60000000 /* Peripheral clock (PBCLK = 60MHz/1) */
#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */
#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */
/* Watchdog pre-scaler (re-visit) */

4
nuttx/configs/pic32-starterkit/ostest/defconfig
View File

@ -124,6 +124,10 @@ CONFIG_PIC32MX_I2C2=n
CONFIG_PIC32MX_SPI2=n
CONFIG_PIC32MX_UART1=n
CONFIG_PIC32MX_UART2=y
CONFIG_PIC32MX_UART3=n
CONFIG_PIC32MX_UART4=n
CONFIG_PIC32MX_UART5=n
CONFIG_PIC32MX_UART6=n
CONFIG_PIC32MX_PMP=n
CONFIG_PIC32MX_ADC=n
CONFIG_PIC32MX_CVR=n

4
nuttx/configs/sure-pic32mx/include/board.h
View File

@ -3,7 +3,7 @@
* include/arch/board/board.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -69,7 +69,7 @@
*/
#define BOARD_UPLL_IDIV 5 /* USB PLL divider */
#define BOARD_USB_CLOCK 48000000 /* USB clock ((20MHz / 5) * 24) */
#define BOARD_USB_CLOCK 48000000 /* USB clock ((20MHz / 5) * 24) / 2 */
/* Peripheral clock is *not* divided down from CPU clock.
* PBCLOCK = CPU_CLOCK / PBDIV