Add GPIO, EXTI header file modifications for STM32F40xxx
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4100 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
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@ -36,16 +36,28 @@
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define STM32_NEXTI 20
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# define STM32_EXTI_MASK 0x000fffff
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#else
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# define STM32_NEXTI 19
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# define STM32_EXTI_MASK 0x0007ffff
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#if defined(CONFIG_STM32_STM32F10XX)
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# ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define STM32_NEXTI 20
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# define STM32_EXTI_MASK 0x000fffff
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# else
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# define STM32_NEXTI 19
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# define STM32_EXTI_MASK 0x0007ffff
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# endif
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define STM32_NEXTI 23
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# define STM32_EXTI_MASK 0x007fffff
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#endif
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#define STM32_EXTI_BIT(n) (1 << (n))
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@ -72,38 +84,38 @@
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/* Interrupt mask register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_IMR_SHIFT (0) /* Bits 18/19-0: Interrupt Mask on line n */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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/* Event mask register */
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#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_EMR_SHIFT (0) /* Bits 18/19-0: Event Mask on line n */
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#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
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#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_EMR_MASK STM32_EXTI_MASK
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/* Rising Trigger selection register */
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#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_RTSR_SHIFT (0) /* Bits 18/19-0: Rising trigger event configuration bit of line n */
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#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
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#define EXTI_RTSR_MASK STM32_EXTI_MASK
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/* Falling Trigger selection register */
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#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_FTSR_SHIFT (0) /* Bits 18/19-0: Falling trigger event configuration bit of line n */
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#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
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#define EXTI_FTSR_MASK STM32_EXTI_MASK
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/* Software interrupt event register */
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#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_SWIER_SHIFT (0) /* Bits 18/19-0: Software Interrupt on line n */
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#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
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#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
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#define EXTI_SWIER_MASK STM32_EXTI_MASK
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/* Pending register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n)
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#define EXTI_IMR_SHIFT (0) /* Bits 18/19-0: Pending bit on line x */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H */
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@ -1,5 +1,5 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_gpio.h
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* arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H
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/************************************************************************************
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* Pre-processor Definitions
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@ -360,5 +360,5 @@
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#define AFIO_EXTICR4_EXTI15_SHIFT (12) /* Bits 15-12: EXTI 15 configuration */
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#define AFIO_EXTICR4_EXTI15_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H */
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@ -0,0 +1,370 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f40xxx_gpio.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#define STM32_NGPIO_PORTS ((STM32_NGPIO + 15) >> 4)
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/* Register Offsets *****************************************************************/
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#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
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#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
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#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
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#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
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#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
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#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
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#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
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#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
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#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
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#define STM32_GPIO_ARFH_OFFSET 0x0024 /* GPIO alternate function high register */
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/* Register Addresses ***************************************************************/
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#if STM32_NGPIO_PORTS > 0
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# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOA_ARFH (STM32_GPIOA_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 1
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# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOB_ARFH (STM32_GPIOB_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 2
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# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOC_ARFH (STM32_GPIOC_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 3
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# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOD_ARFH (STM32_GPIOD_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 4
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# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOE_ARFH (STM32_GPIOE_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 5
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# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOF_ARFH (STM32_GPIOF_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 6
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# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOG_ARFH (STM32_GPIOG_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 7
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# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOH_ARFH (STM32_GPIOH_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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#if STM32_NGPIO_PORTS > 8
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# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET)
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# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET)
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# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET)
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# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET)
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# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET)
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# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET)
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# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET)
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# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
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# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
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# define STM32_GPIOI_ARFH (STM32_GPIOI_BASE+STM32_GPIO_ARFH_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* GPIO port mode register */
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#define GPIO_MODER_INPUT (0) /* Input */
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#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
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#define GPIO_MODER_ALT (2) /* Alternate mode */
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#define GPIO_MODER_ANALOG (3) /* Analog mode */
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#define GPIO_MODER_SHIFT(n) ((n) << 2)
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#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
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#define GPIO_MODER0_SHIFT (0)
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#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
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#define GPIO_MODER1_SHIFT (2)
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#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
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#define GPIO_MODER2_SHIFT (4)
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#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
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#define GPIO_MODER3_SHIFT (6)
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#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
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#define GPIO_MODER4_SHIFT (8)
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#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
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#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */
|
||||
#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n)+16)
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 4)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH0_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH1_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH2_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH3_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH4_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH5_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH6_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH7_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H */
|
||||
|
||||
|
|
@ -46,7 +46,14 @@
|
|||
#include <nuttx/irq.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_gpio.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
# include "chip/stm32f10xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_gpio.h"
|
||||
#else
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-Processor Declarations
|
||||
|
|
@ -62,9 +69,9 @@ extern "C" {
|
|||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Bit-encoded input to stm32_configgpio()
|
||||
* These definitions could be replaced by 'enum' as a stm32_gpio_t data type.
|
||||
*/
|
||||
/* Bit-encoded input to stm32_configgpio() */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
|
||||
/* 16-bit Encoding:
|
||||
* OFFS SX.. VPPP BBBB
|
||||
|
|
@ -130,13 +137,13 @@ extern "C" {
|
|||
|
||||
#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
|
||||
#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
|
||||
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
|
||||
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
* .... .... .... BBBB
|
||||
|
|
@ -161,6 +168,145 @@ extern "C" {
|
|||
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
/* 16-bit Encoding:
|
||||
* Inputs: MMUU X... PPPP BBBB
|
||||
* Outputs: MMUU FFOV PPPP BBBB
|
||||
* Alternate Functions: MMUU AAAA PPPP BBBB
|
||||
* Analog: MMUU .... PPPP BBBB
|
||||
*/
|
||||
|
||||
/* Common mode encodings ***********************************************************/
|
||||
/* Mode:
|
||||
*
|
||||
* MM.. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO port mode */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
#define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
|
||||
#define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
|
||||
#define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
|
||||
#define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
|
||||
|
||||
/* Output pull-ups/downs:
|
||||
* ..UU .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PUPD_SHIFT (12) /* Bits 12-13: Pull-up/pull down */
|
||||
#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
|
||||
# define GPIO_FLLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
|
||||
# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
|
||||
# define GPIO_PULLUP (2 << GPIO_PUPD_SHIFT) /* Pull-down */
|
||||
|
||||
/* Input (only) mode encodings *****************************************************/
|
||||
/* Outputs: MMUU X... PPPP BBBB */
|
||||
|
||||
/* External interrupt selection (GPIO inputs only):
|
||||
* .... X... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_EXTI (1 << 11) /* Bit 11: Configure as EXTI interrupt */
|
||||
|
||||
/* Output (only) mode encodings ****************************************************/
|
||||
/* Outputs: MMUU FFOV PPPP BBBB */
|
||||
|
||||
/* Output frequency selection:
|
||||
* .... FF.. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_MODE_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
|
||||
#define GPIO_OUTPUT_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_OUTPUT_MODE_2MHz (0 << GPIO_MODE_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_OUTPUT_MODE_25MHz (1 << GPIO_MODE_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_OUTPUT_MODE_20MHz (2 << GPIO_MODE_SHIFT) /* 50 MHz Fast speed output */
|
||||
# define GPIOOUTPUT__MODE_100MHz (3 << GPIO_MODE_SHIFT) /* 100 MHz High speed output */
|
||||
|
||||
/* Output type selection:
|
||||
* .... ..O. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_OPENDRAM (1 << 9) /* Open-drain output */
|
||||
#define GPIO_OUTPUT_PUSHPULL (0) /* Push-pull output */
|
||||
|
||||
/* If the pin is a GPIO digital output, then this identifies the initial output value.
|
||||
* If the pin is an input, this bit is overloaded to provide the qualifier to
|
||||
* distinquish input pull-up and -down:
|
||||
*
|
||||
* .... ...V .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, inital value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* Alternate function (only) mode encodings ****************************************/
|
||||
/* Alternate Functions: MMUU AAAA PPPP BBBB */
|
||||
|
||||
#define GPIO_ALTFUNC_SHIFT (8) /* Bits 8-11: Alternate function */
|
||||
#define GPIO_ALTFUNC_MASK (15 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC(n) ((n) << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_0 (0 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_1 (1 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_2 (2 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_3 (3 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_4 (4 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_5 (5 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_6 (6 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_7 (7 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_8 (8 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_9 (9 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_10 (10 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_11 (11 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_12 (12 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_13 (13 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_14 (14 << GPIO_ALTFUNC_SHIFT)
|
||||
# define GPIO_ALTFUNC_15 (15 << GPIO_ALTFUNC_SHIFT)
|
||||
|
||||
/* Common port encodings ***********************************************************/
|
||||
/* This identifies the GPIO port:
|
||||
* .... .... PPPP ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
|
||||
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
|
||||
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
|
||||
# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
* .... .... .... BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */
|
||||
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
|
||||
#else
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
|
|
|||
Loading…
Reference in New Issue