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Back out the last STM32 SDIO DMA change. It is incorrect 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5084 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2012-09-04 12:35:47 +00:00
parent a3f8c46852
commit ae541557b8
2 changed files with 6 additions and 43 deletions
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2
nuttx/ChangeLog
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@ -3254,3 +3254,5 @@
a second, lower priority work queue (CONFIG_SCHED_LPWORK).
* arch/arm/src/stm32/stm32_dma.c, chip/stm32*_memorymap.h: FSMC SRAM is
only 16-bits wide and the SDIO DMA must be set up differently.
* arch/arm/src/stm32/stm32_dma.c: Back out the 16-bit DMA change. It
is incorrect.

47
nuttx/arch/arm/src/stm32/stm32_sdio.c
View File

@ -185,12 +185,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
# define SDIO_RXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
# define SDIO_TXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
/* STM32 F4 stream configuration register (SCR) settings. */
@ -199,18 +195,10 @@
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_RXDMA16_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_16BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_TXDMA16_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_16BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
#else
# error "Unknown STM32 DMA"
#endif
@ -2514,22 +2502,8 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
stm32_configxfrints(priv, SDIO_DMARECV_MASK);
putreg32(1, SDIO_DCTRL_DMAEN_BB);
/* On-chip SRAM is 32-bits wide. FSMC SRAM is 16-bits wide */
#ifdef CONFIG_STM32_FSMC
if (STM32_IS_EXTSRAM(buffer))
{
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 1) >> 1, SDIO_RXDMA16_CONFIG);
}
else
#endif
{
DEBUGASSERT(STM32_IS_SRAM(buffer));
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
}
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
/* Start the DMA */
@ -2597,21 +2571,8 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Configure the TX DMA */
/* On-chip SRAM is 32-bits wide. FSMC SRAM is 16-bits wide */
#ifdef CONFIG_STM32_FSMC
if (STM32_IS_EXTSRAM(buffer))
{
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 1) >> 1, SDIO_TXDMA16_CONFIG);
}
else
#endif
{
DEBUGASSERT(STM32_IS_SRAM(buffer));
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_TXDMA32_CONFIG);
}
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_TXDMA32_CONFIG);
stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE);
putreg32(1, SDIO_DCTRL_DMAEN_BB);