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PIC32MZ: Add support for a timer interrupt

This commit is contained in:
Gregory Nutt 2015-02-24 15:36:08 -06:00
parent a60dde4b23
commit ab08c57a4a
7 changed files with 534 additions and 4 deletions
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4
nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c
View File

@ -83,7 +83,7 @@
*
* TIMER1_PRESCALE >= TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535
*
* Timer 1 does not have very many options for the perscaler value. So we
* Timer 1 does not have very many options for the prescaler value. So we
* can pick the best by brute force. Example:
*
* Example 1. Given:
@ -169,7 +169,7 @@ int up_timerisr(int irq, uint32_t *regs)
void up_timer_initialize(void)
{
/* Configure and enable TIMER1. Used the computed TCKPS divider and timer
* match valude. The source will be either the internal PBCLOCK (TCS=0) or
* match value. The source will be either the internal PBCLOCK (TCS=0) or
* the external SOSC (TCS=1)
*/

21
nuttx/arch/mips/src/pic32mz/Kconfig
View File

@ -59,6 +59,22 @@ config PIC32MZ_T5
bool "Timer 5 (T5)"
default n
config PIC32MZ_T6
bool "Timer 6 (T6)"
default n
config PIC32MZ_T7
bool "Timer 7 (T7)"
default n
config PIC32MZ_T8
bool "Timer 8 (T8)"
default n
config PIC32MZ_T9
bool "Timer 9 (T9)"
default n
config PIC32MZ_IC1
bool "Input Capture 1 (IC1)"
default n
@ -232,6 +248,11 @@ config PIC32MZ_CTMU
endmenu
config PIC32MZ_T1_SOSC
bool
default n
depends on PIC32MZ_T1
menu "PIC32MZ PHY/Ethernet device driver settings"
depends on PIC32MZ_ETHERNET

2
nuttx/arch/mips/src/pic32mz/Make.defs
View File

@ -64,6 +64,6 @@ endif
# Required PIC32MZ files
CHIP_ASRCS =
CHIP_CSRCS = pic32mz-lowinit.c pic32mz-irq.c
CHIP_CSRCS = pic32mz-lowinit.c pic32mz-irq.c pic32mz-timerisr.c
# Configuration-dependent PIC32MZ files

311
nuttx/arch/mips/src/pic32mz/chip/pic32mz-timer.h Normal file
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@ -0,0 +1,311 @@
/************************************************************************************
* arch/mips/src/pic32mz/pic32mz-timer.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/pic32mz/chip.h>
#include "pic32mz-memorymap.h"
#if CHIP_NTIMERS > 0
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Timer Peripheral Offsets *********************************************************/
#define PIC32MZ_TIMER_OFFSET(n) ((n) << 9)
# define PIC32MZ_TIMER1_OFFSET 0x0000
# define PIC32MZ_TIMER2_OFFSET 0x0200
# define PIC32MZ_TIMER3_OFFSET 0x0400
# define PIC32MZ_TIMER4_OFFSET 0x0600
# define PIC32MZ_TIMER5_OFFSET 0x0800
# define PIC32MZ_TIMER6_OFFSET 0x0a00
# define PIC32MZ_TIMER7_OFFSET 0x0c00
# define PIC32MZ_TIMER8_OFFSET 0x0e00
# define PIC32MZ_TIMER9_OFFSET 0x1000
/* Register Offsets *****************************************************************/
#define PIC32MZ_TIMER_CON_OFFSET 0x0000 /* Timer control register */
#define PIC32MZ_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
#define PIC32MZ_TIMER_CONSET_OFFSET 0x0008 /* Timer control set register */
#define PIC32MZ_TIMER_CONINV_OFFSET 0x000c /* Timer control invert register */
#define PIC32MZ_TIMER_CNT_OFFSET 0x0010 /* Timer count register */
#define PIC32MZ_TIMER_CNTCLR_OFFSET 0x0014 /* Timer count clear register */
#define PIC32MZ_TIMER_CNTSET_OFFSET 0x0018 /* Timer count set register */
#define PIC32MZ_TIMER_CNTINV_OFFSET 0x001c /* Timer count invert register */
#define PIC32MZ_TIMER_PR_OFFSET 0x0020 /* Timer period register */
#define PIC32MZ_TIMER_PRCLR_OFFSET 0x0024 /* Timer period clear register */
#define PIC32MZ_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
#define PIC32MZ_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
/* Timer Peripheral Addresses *******************************************************/
#define PIC32MZ_TIMERn_K1BASE(n) (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER_OFFSET(n))
#define PIC32MZ_TIMER1_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER1_OFFSET)
#define PIC32MZ_TIMER2_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER2_OFFSET)
#define PIC32MZ_TIMER3_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER3_OFFSET)
#define PIC32MZ_TIMER4_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER4_OFFSET)
#define PIC32MZ_TIMER5_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER5_OFFSET)
#define PIC32MZ_TIMER6_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER6_OFFSET)
#define PIC32MZ_TIMER7_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER7_OFFSET)
#define PIC32MZ_TIMER8_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER8_OFFSET)
#define PIC32MZ_TIMER9_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER9_OFFSET)
/* Register Addresses ***************************************************************/
#define PIC32MZ_TIMER_CON(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER_CONCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONCLR_OFFSET)
#define PIC32MZ_TIMER_CONSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONSET_OFFSET)
#define PIC32MZ_TIMER_CONINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONINV_OFFSET)
#define PIC32MZ_TIMER_CNT(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNT_OFFSET)
#define PIC32MZ_TIMER_CNTCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTCLR_OFFSET)
#define PIC32MZ_TIMER_CNTSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTSET_OFFSET)
#define PIC32MZ_TIMER_CNTINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTINV_OFFSET)
#define PIC32MZ_TIMER_PR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PR_OFFSET)
#define PIC32MZ_TIMER_PRCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRCLR_OFFSET)
#define PIC32MZ_TIMER_PRSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRSET_OFFSET)
#define PIC32MZ_TIMER_PRINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRINV_OFFSET)
#define PIC32MZ_TIMER1_CON (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER1_CONCLR (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
#define PIC32MZ_TIMER1_CONSET (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
#define PIC32MZ_TIMER1_CONINV (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
#define PIC32MZ_TIMER1_CNT (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
#define PIC32MZ_TIMER1_CNTCLR (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
#define PIC32MZ_TIMER1_CNTSET (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
#define PIC32MZ_TIMER1_CNTINV (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
#define PIC32MZ_TIMER1_PR (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
#define PIC32MZ_TIMER1_PRCLR (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
#define PIC32MZ_TIMER1_PRSET (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
#define PIC32MZ_TIMER1_PRINV (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#if CHIP_NTIMERS > 1
# define PIC32MZ_TIMER2_CON (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER2_CONCLR (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER2_CONSET (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER2_CONINV (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER2_CNT (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER2_CNTCLR (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER2_CNTSET (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER2_CNTINV (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER2_PR (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER2_PRCLR (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER2_PRSET (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER2_PRINV (PIC32MZ_TIMER2_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 2
# define PIC32MZ_TIMER3_CON (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER3_CONCLR (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER3_CONSET (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER3_CONINV (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER3_CNT (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER3_CNTCLR (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER3_CNTSET (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER3_CNTINV (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER3_PR (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER3_PRCLR (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER3_PRSET (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER3_PRINV (PIC32MZ_TIMER3_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 3
# define PIC32MZ_TIMER4_CON (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER4_CONCLR (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER4_CONSET (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER4_CONINV (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER4_CNT (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER4_CNTCLR (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER4_CNTSET (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER4_CNTINV (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER4_PR (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER4_PRCLR (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER4_PRSET (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER4_PRINV (PIC32MZ_TIMER4_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 4
# define PIC32MZ_TIMER5_CON (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER5_CONCLR (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER5_CONSET (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER5_CONINV (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER5_CNT (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER5_CNTCLR (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER5_CNTSET (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER5_CNTINV (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER5_PR (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER5_PRCLR (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER5_PRSET (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER5_PRINV (PIC32MZ_TIMER5_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 5
# define PIC32MZ_TIMER6_CON (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER6_CONCLR (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER6_CONSET (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER6_CONINV (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER6_CNT (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER6_CNTCLR (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER6_CNTSET (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER6_CNTINV (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER6_PR (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER6_PRCLR (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER6_PRSET (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER6_PRINV (PIC32MZ_TIMER6_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 6
# define PIC32MZ_TIMER7_CON (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER7_CONCLR (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER7_CONSET (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER7_CONINV (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER7_CNT (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER7_CNTCLR (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER7_CNTSET (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER7_CNTINV (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER7_PR (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER7_PRCLR (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER7_PRSET (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER7_PRINV (PIC32MZ_TIMER7_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 7
# define PIC32MZ_TIMER8_CON (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER8_CONCLR (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER8_CONSET (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER8_CONINV (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER8_CNT (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER8_CNTCLR (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER8_CNTSET (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER8_CNTINV (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER8_PR (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER8_PRCLR (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER8_PRSET (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER8_PRINV (PIC32MZ_TIMER8_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 8
# define PIC32MZ_TIMER9_CON (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
# define PIC32MZ_TIMER9_CONCLR (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)
# define PIC32MZ_TIMER9_CONSET (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CONSET_OFFSET)
# define PIC32MZ_TIMER9_CONINV (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CONINV_OFFSET)
# define PIC32MZ_TIMER9_CNT (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CNT_OFFSET)
# define PIC32MZ_TIMER9_CNTCLR (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CNTCLR_OFFSET)
# define PIC32MZ_TIMER9_CNTSET (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CNTSET_OFFSET)
# define PIC32MZ_TIMER9_CNTINV (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_CNTINV_OFFSET)
# define PIC32MZ_TIMER9_PR (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_PR_OFFSET)
# define PIC32MZ_TIMER9_PRCLR (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_PRCLR_OFFSET)
# define PIC32MZ_TIMER9_PRSET (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_PRSET_OFFSET)
# define PIC32MZ_TIMER9_PRINV (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Timer control register */
#define TIMER_CON_TCS (1 << 1) /* Bit 1: Timer clock source select (all) */
#define TIMER1_CON_TSYNC (1 << 2) /* Bit 2: Timer external clock input synchronization selection (timer 1 only) */
#define TIMER_CON_T32 (1 << 3) /* Bit 3: 32-bit timer mode select (even timers only) */
#define TIMER_CON_TCKPS_SHIFT (4) /* Bits 4-6: Timer input clock prescale select (all except timer 1) */
#define TIMER_CON_TCKPS_MASK (7 << TIMER_CON_TCKPS_SHIFT)
# define TIMER_CON_TCKPS_1 (0 << TIMER_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER_CON_TCKPS_2 (1 << TIMER_CON_TCKPS_SHIFT) /* 1:2 prescale value */
# define TIMER_CON_TCKPS_4 (2 << TIMER_CON_TCKPS_SHIFT) /* 1:4 prescale value */
# define TIMER_CON_TCKPS_8 (3 << TIMER_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER_CON_TCKPS_16 (4 << TIMER_CON_TCKPS_SHIFT) /* 1:16 prescale value */
# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
#define TIMER_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode (all) */
#define TIMER_CON_ON (1 << 15) /* Bit 15: Timer on (all) */
/* Timer count register */
#define TIMER_CNT_MASK 0xffff /* 16-bit timer counter value */
/* Timer period register */
#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NTIMERS > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H */

191
nuttx/arch/mips/src/pic32mz/pic32mz-timerisr.c Normal file
View File

@ -0,0 +1,191 @@
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_timerisr.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
#include "pic32mz-config.h"
#include "chip/pic32mz-timer.h"
#include "chip/pic32mz-int.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Timer Setup **************************************************************/
/* Timer 1 is a type A timer. Setting the TCS bit in the timer control
* register will select the SOSC as the clock source. Otherwise, PBCLK3
* is the clock source.
*/
#ifdef CONFIG_PIC32MZ_T1_SOSC
# define TIMER1_SRC_FREQ BOARD_SOSC_FREQ
# define TIMER1_CON_TCS TIMER_CON_TCS
#else
# define TIMER1_SRC_FREQ BOARD_PBCLK3
# define TIMER1_CON_TCS (0)
#endif
/* Select a timer 1 prescale value. Our goal is to select the timer MATCH
* register value given the timer 1 input clock frequency and the desired
* system timer frequency:
*
* TIMER1_MATCH = TIMER1_SRC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC
*
* We want the largest possible value for MATCH that is less than 65,535, the
* maximum value for the 16-bit timer register:
*
* TIMER1_PRESCALE >= TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535
*
* Timer 1 does not have very many options for the prescaler value. So we
* can pick the best by brute force. Example:
*
* Example 1. Given:
* BOARD_TIMER1_SOSC = Defined
* BOARD_SOSC_FREQ = 32768
* CLOCKS_PER_SEC = 100
* Then:
* OPTIMAL_PRESCALE = 1
* TIMER1_PRESCALE = 1
* TIMER1_MATCH = 327 -> 100.3 ticks/sec
*
* Example 2. Given:
* BOARD_TIMER1_SOSC = Not defined
* BOARD_PBCLK3 = 60000000
* CLOCKS_PER_SEC = 100
* Then:
* OPTIMAL_PRESCALE = 9.2
* TIMER1_PRESCALE = 64
* TIMER1_MATCH = 9375 -> 100.0 ticks/sec
*/
#define OPTIMAL_PRESCALE (TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535)
#if OPTIMAL_PRESCALE <= 1
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1
# define TIMER1_PRESCALE 1
#elif OPTIMAL_PRESCALE <= 8
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_8
# define TIMER1_PRESCALE 8
#elif OPTIMAL_PRESCALE <= 64
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_64
# define TIMER1_PRESCALE 64
#elif OPTIMAL_PRESCALE <= 256
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_256
# define TIMER1_PRESCALE 256
#else
# error "This timer frequency cannot be represented"
#endif
#define TIMER1_MATCH (TIMER1_SRC_FREQ / TIMER1_PRESCALE / CLOCKS_PER_SEC)
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Global Functions
****************************************************************************/
/****************************************************************************
* Function: up_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
int up_timerisr(int irq, uint32_t *regs)
{
/* Clear the pending timer interrupt */
up_clrpend_irq(PIC32MZ_IRQ_T1);
/* Process timer interrupt */
sched_process_timer();
return 0;
}
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
/* Configure and enable TIMER1. Used the computed TCKPS divider and timer
* match value. The source will be either the internal PBCLOCK (TCS=0) or
* the external SOSC (TCS=1)
*/
putreg32((TIMER1_CON_TCKPS|TIMER1_CON_TCS), PIC32MZ_TIMER1_CON);
putreg32(0, PIC32MZ_TIMER1_CNT);
putreg32(TIMER1_MATCH-1, PIC32MZ_TIMER1_PR);
putreg32(TIMER_CON_ON, PIC32MZ_TIMER1_CONSET);
/* Configure the timer interrupt */
up_clrpend_irq(PIC32MZ_IRQ_T1);
/* Attach the timer interrupt vector */
(void)irq_attach(PIC32MZ_IRQ_T1, (xcpt_t)up_timerisr);
/* And enable the timer interrupt */
up_enable_irq(PIC32MZ_IRQ_T1);
}

4
nuttx/configs/pic32mz-starterkit/include/board.h
View File

@ -101,7 +101,9 @@
* - Timer 1 uses SOSC
*/
#undef BOARD_PBCLK3_ENABLE
#define BOARD_PBCLK3_ENABLE 1 /* Enable PBCLK3 */
#define BOARD_PB3DIV 4 /* Divider = 4 */
#define BOARD_PBCLK3 50000000 /* PBCLK3 frequency = 200MHz/4 = 50MHz */
/* PBCLK4
* Peripherals: Ports

5
nuttx/configs/pic32mz-starterkit/nsh/defconfig
View File

@ -103,6 +103,10 @@ CONFIG_PIC32MZ_T1=y
# CONFIG_PIC32MZ_T3 is not set
# CONFIG_PIC32MZ_T4 is not set
# CONFIG_PIC32MZ_T5 is not set
# CONFIG_PIC32MZ_T6 is not set
# CONFIG_PIC32MZ_T7 is not set
# CONFIG_PIC32MZ_T8 is not set
# CONFIG_PIC32MZ_T9 is not set
# CONFIG_PIC32MZ_IC1 is not set
# CONFIG_PIC32MZ_IC2 is not set
# CONFIG_PIC32MZ_IC3 is not set
@ -142,6 +146,7 @@ CONFIG_PIC32MZ_UART1=y
# CONFIG_PIC32MZ_CAN2 is not set
# CONFIG_PIC32MZ_ETHERNET is not set
# CONFIG_PIC32MZ_CTMU is not set
# CONFIG_PIC32MZ_T1_SOSC is not set
#
# Device Configuration 0 (DEVCFG0)