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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2946 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2010-09-13 15:57:14 +00:00
parent 1960d3cfd3
commit a7fcfe312c
2 changed files with 63 additions and 35 deletions
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21
nuttx/TODO
View File

@ -1,5 +1,5 @@
NuttX TODO List (Last updated September 6, 2010)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
NuttX TODO List (Last updated September 13, 2010)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(5) Task/Scheduler (sched/)
(1) On-demand paging (sched/)
@ -26,6 +26,7 @@ NuttX TODO List (Last updated September 6, 2010)
(2) ARM/i.MX (arch/arm/src/imx/)
(4) ARM/LPC17xx (arch/arm/src/lpc17xx/)
(7) ARM/LPC214x (arch/arm/src/lpc214x/)
(1) ARM/LPC313x (arch/arm/src/lpc313x/)
(3) ARM/STR71x (arch/arm/src/str71x/)
(4) ARM/LM3S6918 (arch/arm/src/lm3s/)
(5) ARM/STM32 (arch/arm/src/stm32/)
@ -789,6 +790,22 @@ o ARM/LPC214x (arch/arm/src/lpc214x/)
Status: Open
Priority: Medium
o ARM/LPC313x (arch/arm/src/lpc313x/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Description: arch/arm/src/lpc313x/lpc313x_spi.c contains logic that is specific to the
Embedded Artist's ea3131 board. We need to abstract the assignmen of SPI
chip selects and logic SPI functions (like SPIDEV_FLASH). My thoughts are:
- Remove lpc313x_spiselect and lpc313x_spistatus from lpc313x_internal.h
- Remove configs/ea3131/src/up_spi.c
- Add configurations CONFIG_LPC3131x_CSOUT1DEV, CONFIG_LPC3131x_CSOUT2DEV,
and CONFIG_LPC3131x_CSOUT3DEV that maps the lpc313x SPI chip selects to
SPIDEV_* values.
- Change arch/arm/src/lpc313x/lpc313x_spi.c to use those configuration
settings.
Status: Open
Priority: High if you want to use SPI on any board other than the ea3131.
o ARM/STR71x (arch/arm/src/str71x/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

77
nuttx/drivers/mtd/at45db.c
View File

@ -69,6 +69,17 @@
************************************************************************************/
/* Configuration ********************************************************************/
/* CONFIG_AT45DB_PREWAIT enables higher performance write logic: We leave the chip
* busy after write and erase operations. This improves write and erase performance
* because we do not have to wait as long between transactions (other processing can
* occur while the chip is busy) but means that the chip must stay powered:
*/
#if defined(CONFIG_AT45DB_PWRSAVE) && defined(CONFIG_AT45DB_PREWAIT)
# error "Both CONFIG_AT45DB_PWRSAVE and CONFIG_AT45DB_PREWAIT are defined"
#endif
/* If the user has provided no frequency, use 1MHz */
#ifndef CONFIG_AT45DB_FREQUENCY
# define CONFIG_AT45DB_FREQUENCY 1000000
@ -460,14 +471,14 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
fvdbg("sector: %08lx\n", (long)sector);
/* If we not trying to conserve power, then we implement some higher performance
* logic: We leave the chip busy after write and erase operations. This improves
* performance because we do not have to wait as long being transactions (other
* processing can occur while the chip is busy) but means that the chip must stay
* powered.
/* Higher performance write logic: We leave the chip busy after write and erase
* operations. This improves write and erase performance because we do not have
* to wait as long between transactions (other processing can occur while the chip
* is busy) but means that the chip must stay powered and that we must check if
* the chip is still busy on each entry point.
*/
#ifndef CONFIG_AT45DB_PWRSAVE
#ifdef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
@ -491,11 +502,11 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
SPI_SNDBLOCK(priv->spi, erasecmd, 4);
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
/* Wait for any erase to complete if we are not trying to conserve power. (see
* comments above).
/* Wait for any erase to complete if we are not trying to improve write
* performance. (see comments above).
*/
#ifdef CONFIG_AT45DB_PWRSAVE
#ifndef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
fvdbg("Erased\n");
@ -509,14 +520,14 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
{
fvdbg("priv: %p\n", priv);
/* If we not trying to conserve power, then we implement some higher performance
* logic: We leave the chip busy after write and erase operations. This improves
* performance because we do not have to wait as long being transactions (other
* processing can occur while the chip is busy) but means that the chip must stay
* powered.
/* Higher performance write logic: We leave the chip busy after write and erase
* operations. This improves write and erase performance because we do not have
* to wait as long between transactions (other processing can occur while the chip
* is busy) but means that the chip must stay powered and that we must check if
* the chip is still busy on each entry point.
*/
#ifndef CONFIG_AT45DB_PWRSAVE
#ifdef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
@ -532,11 +543,11 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
SPI_SNDBLOCK(priv->spi, g_chiperase, CHIP_ERASE_SIZE);
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
/* Wait for any erase to complete if we are not trying to conserve power. (see
* comments above).
/* Wait for any erase to complete if we are not trying to improve write
* performance. (see comments above).
*/
#ifdef CONFIG_AT45DB_PWRSAVE
#ifndef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
return OK;
@ -561,14 +572,14 @@ static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *
wrcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */
wrcmd[3] = offset & 0xff; /* 24-bit address LS byte */
/* If we not trying to conserve power, then we implement some higher performance
* logic: We leave the chip busy after write and erase operations. This improves
* performance because we do not have to wait as long being transactions (other
* processing can occur while the chip is busy) but means that the chip must stay
* powered.
/* Higher performance write logic: We leave the chip busy after write and erase
* operations. This improves write and erase performance because we do not have
* to wait as long between transactions (other processing can occur while the chip
* is busy) but means that the chip must stay powered and that we must check if
* the chip is still busy on each entry point.
*/
#ifndef CONFIG_AT45DB_PWRSAVE
#ifdef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
@ -577,11 +588,11 @@ static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *
SPI_SNDBLOCK(priv->spi, buffer, 1 << priv->pageshift);
SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
/* Wait for any erase to complete if we are not trying to conserve power. (see
* comments above).
/* Wait for any erase to complete if we are not trying to improve write
* performance. (see comments above).
*/
#ifdef CONFIG_AT45DB_PWRSAVE
#ifndef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif
fvdbg("Written\n");
@ -699,14 +710,14 @@ static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbyte
at45db_lock(priv);
/* If we not trying to conserve power, then we implement some higher performance
* logic: We leave the chip busy after write and erase operations. This improves
* performance because we do not have to wait as long being transactions (other
* processing can occur while the chip is busy) but means that the chip must stay
* powered and that we have to add waits at all entry points.
/* Higher performance write logic: We leave the chip busy after write and erase
* operations. This improves write and erase performance because we do not have
* to wait as long between transactions (other processing can occur while the chip
* is busy) but means that the chip must stay powered and that we must check if
* the chip is still busy on each entry point.
*/
#ifndef CONFIG_AT45DB_PWRSAVE
#ifdef CONFIG_AT45DB_PREWAIT
at45db_waitbusy(priv);
#endif