Add an ADC-based touchscreen driver for the PIC32MX7 MMB board
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4804 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
5dcce4572a
commit
9c344d9036
|
|
@ -2888,3 +2888,5 @@
|
|||
support for the MIO283QT2 LCD.
|
||||
* configs/pic32mx7mmb/src/up_mio283qt2.c: Add support for the MIO283QT2
|
||||
LCD on the PIC32MX7 MMB board.
|
||||
* configs/pic32mx7mmb/src/up_touchscreen.c: Add an ACD-based touchscreen
|
||||
driver for the PIC32MX7 MMB board.
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
||||
<p>Last Updated: May 19, 2012</p>
|
||||
<p>Last Updated: June 4, 2012</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -2269,14 +2269,19 @@
|
|||
Stay tuned for updates.
|
||||
</p>
|
||||
<li><b>Mikroelektronika PIC32MX7 Mulitmedia Board (MMB)</b>.
|
||||
A port has begun for the Mikroelektronika PIC32MX7 Multimedia Board (MMB).
|
||||
See http://www.mikroe.com/ for further information.
|
||||
A port has been completed for the Mikroelektronika PIC32MX7 Multimedia Board (MMB).
|
||||
See http://www.mikroe.com/ for further information about this board.
|
||||
</li>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
A basic OS test configuration is in place, but the board does not boot.
|
||||
It looks like I will need an ICD3 in order to debug the code (PICkit3
|
||||
doesn't work for debugging with this board). This effort is temporarily stalled.
|
||||
Two verified configurations are available:
|
||||
(1) The basic OS test configuration that verfies the correctnexx port of Nuttx, and (2) an extensive <a href="NuttShell.html">NuttShell (NSH)</a> configuration.
|
||||
The NSH configuration includes:
|
||||
(1) Full network support,
|
||||
(2) Verified SPI driver,
|
||||
(3) SPI-based SD Card support,
|
||||
(4) USB device support (including configuration options for the USB mass storage device and the CDC/ACM serial class), and
|
||||
(4) Support for the MIO873QT2 LCD on the PIC32MX7 MMB.
|
||||
</p>
|
||||
</ul>
|
||||
</td>
|
||||
|
|
|
|||
|
|
@ -1,243 +1,243 @@
|
|||
/************************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-adc.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
************************************************************************************/
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define PIC32MX_ADC_CON1_OFFSET 0x0000 /* ADC control register 1 */
|
||||
#define PIC32MX_ADC_CON1CLR_OFFSET 0x0004 /* ADC control clear register 1 */
|
||||
#define PIC32MX_ADC_CON1SET_OFFSET 0x0008 /* ADC control set register 1 */
|
||||
#define PIC32MX_ADC_CON1INV_OFFSET 0x000c /* ADC control invert register 1 */
|
||||
#define PIC32MX_ADC_CON2_OFFSET 0x0010 /* ADC control register 2 */
|
||||
#define PIC32MX_ADC_CON2CLR_OFFSET 0x0014 /* ADC control clear register 2 */
|
||||
#define PIC32MX_ADC_CON2SET_OFFSET 0x0018 /* ADC control set register 2 */
|
||||
#define PIC32MX_ADC_CON2INV_OFFSET 0x001c /* ADC control invert register 2 */
|
||||
#define PIC32MX_ADC_CON3_OFFSET 0x0020 /* ADC control register 3 */
|
||||
#define PIC32MX_ADC_CON3CLR_OFFSET 0x0024 /* ADC control clear register 3 */
|
||||
#define PIC32MX_ADC_CON3SET_OFFSET 0x0028 /* ADC control set register 3 */
|
||||
#define PIC32MX_ADC_CON3INV_OFFSET 0x002c /* ADC control invert register 3 */
|
||||
#define PIC32MX_ADC_CHS_OFFSET 0x0040 /* ADC input pin selection register */
|
||||
#define PIC32MX_ADC_CHSCLR_OFFSET 0x0044 /* ADC input pin selection clear register */
|
||||
#define PIC32MX_ADC_CHSSET_OFFSET 0x0048 /* ADC input pin selection set register */
|
||||
#define PIC32MX_ADC_CHSINV_OFFSET 0x004c /* ADC input pin selection invert register */
|
||||
#define PIC32MX_ADC_CSSL_OFFSET 0x0050 /* ADC sequentially scanned input register */
|
||||
#define PIC32MX_ADC_CSSLCLR_OFFSET 0x0054 /* ADC sequentially scanned input clear register */
|
||||
#define PIC32MX_ADC_CSSLSET_OFFSET 0x0058 /* ADC sequentially scanned input set register */
|
||||
#define PIC32MX_ADC_CSSLINV_OFFSET 0x005c /* ADC sequentially scanned input invert register */
|
||||
#define PIC32MX_ADC_CFG_OFFSET 0x0060 /* ADC input pin configuration register */
|
||||
#define PIC32MX_ADC_CFGCLR_OFFSET 0x0064 /* ADC input pin configuration clear register */
|
||||
#define PIC32MX_ADC_CFGSET_OFFSET 0x0068 /* ADC input pin configuration set register */
|
||||
#define PIC32MX_ADC_CFGINV_OFFSET 0x006c /* ADC input pin configuration invert register */
|
||||
|
||||
#define PIC32MX_ADC_BUF_OFFSET(n) (0x0070 + ((n) << 4))
|
||||
#define PIC32MX_ADC_BUF0_OFFSET 0x0070 /* ADC result word 0 */
|
||||
#define PIC32MX_ADC_BUF1_OFFSET 0x0080 /* ADC result word 1 */
|
||||
#define PIC32MX_ADC_BUF2_OFFSET 0x0090 /* ADC result word 2 */
|
||||
#define PIC32MX_ADC_BUF3_OFFSET 0x00a0 /* ADC result word 3 */
|
||||
#define PIC32MX_ADC_BUF4_OFFSET 0x00b0 /* ADC result word 4 */
|
||||
#define PIC32MX_ADC_BUF5_OFFSET 0x00c0 /* ADC result word 5 */
|
||||
#define PIC32MX_ADC_BUF6_OFFSET 0x00d0 /* ADC result word 6 */
|
||||
#define PIC32MX_ADC_BUF7_OFFSET 0x00e0 /* ADC result word 7 */
|
||||
#define PIC32MX_ADC_BUF8_OFFSET 0x00f0 /* ADC result word 8 */
|
||||
#define PIC32MX_ADC_BUF9_OFFSET 0x0100 /* ADC result word 9 */
|
||||
#define PIC32MX_ADC_BUF10_OFFSET 0x0110 /* ADC result word 10 */
|
||||
#define PIC32MX_ADC_BUF11_OFFSET 0x0120 /* ADC result word 11 */
|
||||
#define PIC32MX_ADC_BUF12_OFFSET 0x0130 /* ADC result word 12 */
|
||||
#define PIC32MX_ADC_BUF13_OFFSET 0x0140 /* ADC result word 13 */
|
||||
#define PIC32MX_ADC_BUF14_OFFSET 0x0150 /* ADC result word 14 */
|
||||
#define PIC32MX_ADC_BUF15_OFFSET 0x0160 /* ADC result word 15 */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define PIC32MX_ADC_CON1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1_OFFSET)
|
||||
#define PIC32MX_ADC_CON1CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON1SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON1INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1INV_OFFSET)
|
||||
#define PIC32MX_ADC_CON2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2_OFFSET)
|
||||
#define PIC32MX_ADC_CON2CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON2SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON2INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2INV_OFFSET)
|
||||
#define PIC32MX_ADC_CON3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3_OFFSET)
|
||||
#define PIC32MX_ADC_CON3CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON3SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON3INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3INV_OFFSET)
|
||||
#define PIC32MX_ADC_CHS (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHS_OFFSET)
|
||||
#define PIC32MX_ADC_CHSCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CHSSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSSET_OFFSET)
|
||||
#define PIC32MX_ADC_CHSINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSINV_OFFSET)
|
||||
#define PIC32MX_ADC_CSSL (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSL_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLSET_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLINV_OFFSET)
|
||||
#define PIC32MX_ADC_CFG (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFG_OFFSET)
|
||||
#define PIC32MX_ADC_CFGCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CFGSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGSET_OFFSET)
|
||||
#define PIC32MX_ADC_CFGINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGINV_OFFSET)
|
||||
|
||||
#define PIC32MX_ADC_BUF(n) (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF_OFFSET(n))
|
||||
#define PIC32MX_ADC_BUF0 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF0_OFFSET)
|
||||
#define PIC32MX_ADC_BUF1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF1_OFFSET)
|
||||
#define PIC32MX_ADC_BUF2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF2_OFFSET)
|
||||
#define PIC32MX_ADC_BUF3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF3_OFFSET)
|
||||
#define PIC32MX_ADC_BUF4 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF4_OFFSET)
|
||||
#define PIC32MX_ADC_BUF5 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF5_OFFSET)
|
||||
#define PIC32MX_ADC_BUF6 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF6_OFFSET)
|
||||
#define PIC32MX_ADC_BUF7 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF7_OFFSET)
|
||||
#define PIC32MX_ADC_BUF8 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF8_OFFSET)
|
||||
#define PIC32MX_ADC_BUF9 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF9_OFFSET)
|
||||
#define PIC32MX_ADC_BUF10 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF10_OFFSET)
|
||||
#define PIC32MX_ADC_BUF11 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF11_OFFSET)
|
||||
#define PIC32MX_ADC_BUF12 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF12_OFFSET)
|
||||
#define PIC32MX_ADC_BUF13 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF13_OFFSET)
|
||||
#define PIC32MX_ADC_BUF14 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF14_OFFSET)
|
||||
#define PIC32MX_ADC_BUF15 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF15_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***************************************************/
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CON1_DONE (1 << 0) /* Bit 0: A/D conversion status */
|
||||
#define ADC_CON1_SAMP (1 << 1) /* Bit 1: ADC sample enable */
|
||||
#define ADC_CON1_ASAM (1 << 2) /* Bit 2: ADC sample auto start */
|
||||
#define ADC_CON1_CLRASAM (1 << 4) /* Bit 4: Stop conversion sequence */
|
||||
#define ADC_CON1_SSRC_SHIFT (5) /* Bits 5-7: Conversion trigger source select */
|
||||
#define ADC_CON1_SSRC_MASK (7 << ADC_CON1_SSRC_SHIFT)
|
||||
# define ADC_CON1_SSRC_SAMP (0 << ADC_CON1_SSRC_SHIFT) /* Clearing SAMP starts */
|
||||
# define ADC_CON1_SSRC_INT0 (1 << ADC_CON1_SSRC_SHIFT) /* INT0 transition starts */
|
||||
# define ADC_CON1_SSRC_TIMER3 (2 << ADC_CON1_SSRC_SHIFT) /* Timer3 match starts */
|
||||
# define ADC_CON1_SSRC_COUNT (7 << ADC_CON1_SSRC_SHIFT) /* Internal counter starts */
|
||||
#define ADC_CON1_FORM_SHIFT (8) /* Bits 8-10: Data output format */
|
||||
#define ADC_CON1_FORM_MASK (7 << ADC_CON1_FORM_SHIFT)
|
||||
# define ADC_CON1_FORM_UINT16 (0 << ADC_CON1_FORM_SHIFT) /* Integer 16-bit */
|
||||
# define ADC_CON1_FORM_SINT16 (1 << ADC_CON1_FORM_SHIFT) /* Signed integer 16-bit */
|
||||
# define ADC_CON1_FORM_FRAC16 (2 << ADC_CON1_FORM_SHIFT) /* Fractional 16-bit */
|
||||
# define ADC_CON1_FORM_SFRAC16 (3 << ADC_CON1_FORM_SHIFT) /* Signed fractional 16-bit */
|
||||
# define ADC_CON1_FORM_UINT32 (4 << ADC_CON1_FORM_SHIFT) /* Integer 32-bit */
|
||||
# define ADC_CON1_FORM_SINT32 (5 << ADC_CON1_FORM_SHIFT) /* Signed integer 32-bit */
|
||||
# define ADC_CON1_FORM_FRAC32 (6 << ADC_CON1_FORM_SHIFT) /* Fractional 32-bit */
|
||||
# define ADC_CON1_FORM_SFRAC32 (7 << ADC_CON1_FORM_SHIFT) /* Signed fractional 32-bit */
|
||||
#define ADC_CON1_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define ADC_CON1_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
|
||||
#define ADC_CON1_ON (1 << 15) /* Bit 14: ADC operating mode */
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CON2_ALTS (1 << 0) /* Bit 0: Alternate input sample mode select */
|
||||
#define ADC_CON2_BUFM (1 << 1) /* Bit 1: ADC result buffer mode select */
|
||||
#define ADC_CON2_SMPI_SHIFT (2) /* Bits 2-5: Sample/sequences per interrupt */
|
||||
#define ADC_CON2_SMPI_MASK (15 << ADC_CON2_SMPI_SHIFT)
|
||||
# define ADC_CON2_SMPI(n) ((n-1) << ADC_CON2_SMPI_SHIFT) /* Interrupt after nth conversion */
|
||||
#define ADC_CON2_BUFS (1 << 7) /* Bit 7: Buffer fill status */
|
||||
#define ADC_CON2_CSCNA (1 << 10) /* Bit 10: Scan input selections */
|
||||
#define ADC_CON2_OFFCAL (1 << 12) /* Bit 12: Input offset calibration mode select */
|
||||
#define ADC_CON2_VCFG_SHIFT (13) /* Bits 13-15: Voltage reference configuation */
|
||||
#define ADC_CON2_VCFG_MASK (15 << ADC_CON2_VCFG_SHIFT)
|
||||
# define ADC_CON2_VCFG_AVDDAVSS (0 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=AVss */
|
||||
# define ADC_CON2_VCFG_VREFAVSS (1 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=AVss */
|
||||
# define ADC_CON2_VCFG_AVDDVREF (2 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=VREF- */
|
||||
# define ADC_CON2_VCFG_VREFVREF (3 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=VREF- */
|
||||
|
||||
/* ADC control register 3 */
|
||||
|
||||
#define ADC_CON3_ADCS_SHIFT (0) /* Bits 0-7: ADC conversion clock select */
|
||||
#define ADC_CON3_ADCS_MASK (0xff << ADC_CON3_ADCS_SHIFT)
|
||||
# define ADC_CON3_ADCS(n) ((((n)>>1)-1) << ADC_CON3_ADCS_SHIFT) /* n*Tpb = Tad, n=2,4,..,512 */
|
||||
#define ADC_CON3_SAMC_SHIFT (8) /* Bits 8-12: Auto-sample time bits */
|
||||
#define ADC_CON3_SAMC_MASK (31 << ADC_CON3_SAMC_SHIFT)
|
||||
# define ADC_CON3_SAMC(n) ((n) << ADC_CON3_SAMC_SHIFT) /* Tad = n, n=1..15 */
|
||||
#define ADC_CON3_ADRC (1 << 15) /* Bit 15: ADC conversion clock source */
|
||||
|
||||
/* ADC input pin selection register */
|
||||
|
||||
#define ADC_CHS_CH0SA_SHIFT (16) /* Bits 16-19: MUX A positive input select */
|
||||
#define ADC_CHS_CH0SA_MASK (15 << ADC_CHS_CH0SA_SHIFT)
|
||||
# define ADC_CHS_CH0SA(n) ((n) << ADC_CHS_CH0SA_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
|
||||
#define ADC_CHS_CH0NA (1 << 23) /* Bit 23: MUX A negative input select */
|
||||
#define ADC_CHS_CH0SB_SHIFT (24) /* Bits 24-27: MUX B positive input select */
|
||||
#define ADC_CHS_CH0SB_MASK (15 << ADC_CHS_CH0SB_SHIFT)
|
||||
# define ADC_CHS_CH0SB(n) ((n) << ADC_CHS_CH0SB_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
|
||||
#define ADC_CHS_CH0NB (1 << 31) /* Bit 31: MUX B negative input select */
|
||||
|
||||
/* ADC sequentially scanned input register */
|
||||
|
||||
#define ADC_CSSL(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
|
||||
|
||||
/* ADC input pin configuration register */
|
||||
|
||||
#define ADC_CFG(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
|
||||
|
||||
/* ADC result word 0-15 -- 32-bits of ADC result data */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H */
|
||||
/************************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-adc.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
************************************************************************************/
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define PIC32MX_ADC_CON1_OFFSET 0x0000 /* ADC control register 1 */
|
||||
#define PIC32MX_ADC_CON1CLR_OFFSET 0x0004 /* ADC control clear register 1 */
|
||||
#define PIC32MX_ADC_CON1SET_OFFSET 0x0008 /* ADC control set register 1 */
|
||||
#define PIC32MX_ADC_CON1INV_OFFSET 0x000c /* ADC control invert register 1 */
|
||||
#define PIC32MX_ADC_CON2_OFFSET 0x0010 /* ADC control register 2 */
|
||||
#define PIC32MX_ADC_CON2CLR_OFFSET 0x0014 /* ADC control clear register 2 */
|
||||
#define PIC32MX_ADC_CON2SET_OFFSET 0x0018 /* ADC control set register 2 */
|
||||
#define PIC32MX_ADC_CON2INV_OFFSET 0x001c /* ADC control invert register 2 */
|
||||
#define PIC32MX_ADC_CON3_OFFSET 0x0020 /* ADC control register 3 */
|
||||
#define PIC32MX_ADC_CON3CLR_OFFSET 0x0024 /* ADC control clear register 3 */
|
||||
#define PIC32MX_ADC_CON3SET_OFFSET 0x0028 /* ADC control set register 3 */
|
||||
#define PIC32MX_ADC_CON3INV_OFFSET 0x002c /* ADC control invert register 3 */
|
||||
#define PIC32MX_ADC_CHS_OFFSET 0x0040 /* ADC input pin selection register */
|
||||
#define PIC32MX_ADC_CHSCLR_OFFSET 0x0044 /* ADC input pin selection clear register */
|
||||
#define PIC32MX_ADC_CHSSET_OFFSET 0x0048 /* ADC input pin selection set register */
|
||||
#define PIC32MX_ADC_CHSINV_OFFSET 0x004c /* ADC input pin selection invert register */
|
||||
#define PIC32MX_ADC_CSSL_OFFSET 0x0050 /* ADC sequentially scanned input register */
|
||||
#define PIC32MX_ADC_CSSLCLR_OFFSET 0x0054 /* ADC sequentially scanned input clear register */
|
||||
#define PIC32MX_ADC_CSSLSET_OFFSET 0x0058 /* ADC sequentially scanned input set register */
|
||||
#define PIC32MX_ADC_CSSLINV_OFFSET 0x005c /* ADC sequentially scanned input invert register */
|
||||
#define PIC32MX_ADC_CFG_OFFSET 0x0060 /* ADC input pin configuration register */
|
||||
#define PIC32MX_ADC_CFGCLR_OFFSET 0x0064 /* ADC input pin configuration clear register */
|
||||
#define PIC32MX_ADC_CFGSET_OFFSET 0x0068 /* ADC input pin configuration set register */
|
||||
#define PIC32MX_ADC_CFGINV_OFFSET 0x006c /* ADC input pin configuration invert register */
|
||||
|
||||
#define PIC32MX_ADC_BUF_OFFSET(n) (0x0070 + ((n) << 4))
|
||||
#define PIC32MX_ADC_BUF0_OFFSET 0x0070 /* ADC result word 0 */
|
||||
#define PIC32MX_ADC_BUF1_OFFSET 0x0080 /* ADC result word 1 */
|
||||
#define PIC32MX_ADC_BUF2_OFFSET 0x0090 /* ADC result word 2 */
|
||||
#define PIC32MX_ADC_BUF3_OFFSET 0x00a0 /* ADC result word 3 */
|
||||
#define PIC32MX_ADC_BUF4_OFFSET 0x00b0 /* ADC result word 4 */
|
||||
#define PIC32MX_ADC_BUF5_OFFSET 0x00c0 /* ADC result word 5 */
|
||||
#define PIC32MX_ADC_BUF6_OFFSET 0x00d0 /* ADC result word 6 */
|
||||
#define PIC32MX_ADC_BUF7_OFFSET 0x00e0 /* ADC result word 7 */
|
||||
#define PIC32MX_ADC_BUF8_OFFSET 0x00f0 /* ADC result word 8 */
|
||||
#define PIC32MX_ADC_BUF9_OFFSET 0x0100 /* ADC result word 9 */
|
||||
#define PIC32MX_ADC_BUF10_OFFSET 0x0110 /* ADC result word 10 */
|
||||
#define PIC32MX_ADC_BUF11_OFFSET 0x0120 /* ADC result word 11 */
|
||||
#define PIC32MX_ADC_BUF12_OFFSET 0x0130 /* ADC result word 12 */
|
||||
#define PIC32MX_ADC_BUF13_OFFSET 0x0140 /* ADC result word 13 */
|
||||
#define PIC32MX_ADC_BUF14_OFFSET 0x0150 /* ADC result word 14 */
|
||||
#define PIC32MX_ADC_BUF15_OFFSET 0x0160 /* ADC result word 15 */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define PIC32MX_ADC_CON1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1_OFFSET)
|
||||
#define PIC32MX_ADC_CON1CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON1SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON1INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1INV_OFFSET)
|
||||
#define PIC32MX_ADC_CON2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2_OFFSET)
|
||||
#define PIC32MX_ADC_CON2CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON2SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON2INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2INV_OFFSET)
|
||||
#define PIC32MX_ADC_CON3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3_OFFSET)
|
||||
#define PIC32MX_ADC_CON3CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3CLR_OFFSET)
|
||||
#define PIC32MX_ADC_CON3SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3SET_OFFSET)
|
||||
#define PIC32MX_ADC_CON3INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3INV_OFFSET)
|
||||
#define PIC32MX_ADC_CHS (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHS_OFFSET)
|
||||
#define PIC32MX_ADC_CHSCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CHSSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSSET_OFFSET)
|
||||
#define PIC32MX_ADC_CHSINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSINV_OFFSET)
|
||||
#define PIC32MX_ADC_CSSL (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSL_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLSET_OFFSET)
|
||||
#define PIC32MX_ADC_CSSLINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLINV_OFFSET)
|
||||
#define PIC32MX_ADC_CFG (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFG_OFFSET)
|
||||
#define PIC32MX_ADC_CFGCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGCLR_OFFSET)
|
||||
#define PIC32MX_ADC_CFGSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGSET_OFFSET)
|
||||
#define PIC32MX_ADC_CFGINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGINV_OFFSET)
|
||||
|
||||
#define PIC32MX_ADC_BUF(n) (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF_OFFSET(n))
|
||||
#define PIC32MX_ADC_BUF0 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF0_OFFSET)
|
||||
#define PIC32MX_ADC_BUF1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF1_OFFSET)
|
||||
#define PIC32MX_ADC_BUF2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF2_OFFSET)
|
||||
#define PIC32MX_ADC_BUF3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF3_OFFSET)
|
||||
#define PIC32MX_ADC_BUF4 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF4_OFFSET)
|
||||
#define PIC32MX_ADC_BUF5 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF5_OFFSET)
|
||||
#define PIC32MX_ADC_BUF6 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF6_OFFSET)
|
||||
#define PIC32MX_ADC_BUF7 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF7_OFFSET)
|
||||
#define PIC32MX_ADC_BUF8 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF8_OFFSET)
|
||||
#define PIC32MX_ADC_BUF9 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF9_OFFSET)
|
||||
#define PIC32MX_ADC_BUF10 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF10_OFFSET)
|
||||
#define PIC32MX_ADC_BUF11 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF11_OFFSET)
|
||||
#define PIC32MX_ADC_BUF12 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF12_OFFSET)
|
||||
#define PIC32MX_ADC_BUF13 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF13_OFFSET)
|
||||
#define PIC32MX_ADC_BUF14 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF14_OFFSET)
|
||||
#define PIC32MX_ADC_BUF15 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF15_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***************************************************/
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CON1_DONE (1 << 0) /* Bit 0: A/D conversion status */
|
||||
#define ADC_CON1_SAMP (1 << 1) /* Bit 1: ADC sample enable */
|
||||
#define ADC_CON1_ASAM (1 << 2) /* Bit 2: ADC sample auto start */
|
||||
#define ADC_CON1_CLRASAM (1 << 4) /* Bit 4: Stop conversion sequence */
|
||||
#define ADC_CON1_SSRC_SHIFT (5) /* Bits 5-7: Conversion trigger source select */
|
||||
#define ADC_CON1_SSRC_MASK (7 << ADC_CON1_SSRC_SHIFT)
|
||||
# define ADC_CON1_SSRC_SAMP (0 << ADC_CON1_SSRC_SHIFT) /* Clearing SAMP starts */
|
||||
# define ADC_CON1_SSRC_INT0 (1 << ADC_CON1_SSRC_SHIFT) /* INT0 transition starts */
|
||||
# define ADC_CON1_SSRC_TIMER3 (2 << ADC_CON1_SSRC_SHIFT) /* Timer3 match starts */
|
||||
# define ADC_CON1_SSRC_COUNT (7 << ADC_CON1_SSRC_SHIFT) /* Internal counter starts */
|
||||
#define ADC_CON1_FORM_SHIFT (8) /* Bits 8-10: Data output format */
|
||||
#define ADC_CON1_FORM_MASK (7 << ADC_CON1_FORM_SHIFT)
|
||||
# define ADC_CON1_FORM_UINT16 (0 << ADC_CON1_FORM_SHIFT) /* Integer 16-bit */
|
||||
# define ADC_CON1_FORM_SINT16 (1 << ADC_CON1_FORM_SHIFT) /* Signed integer 16-bit */
|
||||
# define ADC_CON1_FORM_FRAC16 (2 << ADC_CON1_FORM_SHIFT) /* Fractional 16-bit */
|
||||
# define ADC_CON1_FORM_SFRAC16 (3 << ADC_CON1_FORM_SHIFT) /* Signed fractional 16-bit */
|
||||
# define ADC_CON1_FORM_UINT32 (4 << ADC_CON1_FORM_SHIFT) /* Integer 32-bit */
|
||||
# define ADC_CON1_FORM_SINT32 (5 << ADC_CON1_FORM_SHIFT) /* Signed integer 32-bit */
|
||||
# define ADC_CON1_FORM_FRAC32 (6 << ADC_CON1_FORM_SHIFT) /* Fractional 32-bit */
|
||||
# define ADC_CON1_FORM_SFRAC32 (7 << ADC_CON1_FORM_SHIFT) /* Signed fractional 32-bit */
|
||||
#define ADC_CON1_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define ADC_CON1_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
|
||||
#define ADC_CON1_ON (1 << 15) /* Bit 14: ADC operating mode */
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CON2_ALTS (1 << 0) /* Bit 0: Alternate input sample mode select */
|
||||
#define ADC_CON2_BUFM (1 << 1) /* Bit 1: ADC result buffer mode select */
|
||||
#define ADC_CON2_SMPI_SHIFT (2) /* Bits 2-5: Sample/sequences per interrupt */
|
||||
#define ADC_CON2_SMPI_MASK (15 << ADC_CON2_SMPI_SHIFT)
|
||||
# define ADC_CON2_SMPI(n) ((n-1) << ADC_CON2_SMPI_SHIFT) /* Interrupt after nth conversion */
|
||||
#define ADC_CON2_BUFS (1 << 7) /* Bit 7: Buffer fill status */
|
||||
#define ADC_CON2_CSCNA (1 << 10) /* Bit 10: Scan input selections */
|
||||
#define ADC_CON2_OFFCAL (1 << 12) /* Bit 12: Input offset calibration mode select */
|
||||
#define ADC_CON2_VCFG_SHIFT (13) /* Bits 13-15: Voltage reference configuation */
|
||||
#define ADC_CON2_VCFG_MASK (15 << ADC_CON2_VCFG_SHIFT)
|
||||
# define ADC_CON2_VCFG_AVDDAVSS (0 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=AVss */
|
||||
# define ADC_CON2_VCFG_VREFAVSS (1 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=AVss */
|
||||
# define ADC_CON2_VCFG_AVDDVREF (2 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=VREF- */
|
||||
# define ADC_CON2_VCFG_VREFVREF (3 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=VREF- */
|
||||
|
||||
/* ADC control register 3 */
|
||||
|
||||
#define ADC_CON3_ADCS_SHIFT (0) /* Bits 0-7: ADC conversion clock select */
|
||||
#define ADC_CON3_ADCS_MASK (0xff << ADC_CON3_ADCS_SHIFT)
|
||||
# define ADC_CON3_ADCS(n) ((((n)>>1)-1) << ADC_CON3_ADCS_SHIFT) /* n*Tpb = Tad, n=2,4,..,512 */
|
||||
#define ADC_CON3_SAMC_SHIFT (8) /* Bits 8-12: Auto-sample time bits */
|
||||
#define ADC_CON3_SAMC_MASK (31 << ADC_CON3_SAMC_SHIFT)
|
||||
# define ADC_CON3_SAMC(n) ((n) << ADC_CON3_SAMC_SHIFT) /* Tad = n, n=1..15 */
|
||||
#define ADC_CON3_ADRC (1 << 15) /* Bit 15: ADC conversion clock source */
|
||||
|
||||
/* ADC input pin selection register */
|
||||
|
||||
#define ADC_CHS_CH0SA_SHIFT (16) /* Bits 16-19: MUX A positive input select */
|
||||
#define ADC_CHS_CH0SA_MASK (15 << ADC_CHS_CH0SA_SHIFT)
|
||||
# define ADC_CHS_CH0SA(n) ((n) << ADC_CHS_CH0SA_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
|
||||
#define ADC_CHS_CH0NA (1 << 23) /* Bit 23: MUX A negative input select */
|
||||
#define ADC_CHS_CH0SB_SHIFT (24) /* Bits 24-27: MUX B positive input select */
|
||||
#define ADC_CHS_CH0SB_MASK (15 << ADC_CHS_CH0SB_SHIFT)
|
||||
# define ADC_CHS_CH0SB(n) ((n) << ADC_CHS_CH0SB_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
|
||||
#define ADC_CHS_CH0NB (1 << 31) /* Bit 31: MUX B negative input select */
|
||||
|
||||
/* ADC sequentially scanned input register */
|
||||
|
||||
#define ADC_CSSL(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
|
||||
|
||||
/* ADC input pin configuration register */
|
||||
|
||||
#define ADC_CFG(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
|
||||
|
||||
/* ADC result word 0-15 -- 32-bits of ADC result data */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H */
|
||||
|
|
|
|||
|
|
@ -1,304 +1,304 @@
|
|||
/********************************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-ioport.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
********************************************************************************************/
|
||||
/* Register Offsets *************************************************************************/
|
||||
/* Offsets relative to PIC32MX_IOPORTn_K1BASE */
|
||||
|
||||
#define PIC32MX_IOPORT_TRIS_OFFSET 0x0000 /* Tri-state register */
|
||||
#define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0004 /* Tri-state clear register */
|
||||
#define PIC32MX_IOPORT_TRISSET_OFFSET 0x0008 /* Tri-state set register */
|
||||
#define PIC32MX_IOPORT_TRISINV_OFFSET 0x000c /* Tri-state invert register */
|
||||
#define PIC32MX_IOPORT_PORT_OFFSET 0x0010 /* Port register */
|
||||
#define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0014 /* Port clear register */
|
||||
#define PIC32MX_IOPORT_PORTSET_OFFSET 0x0018 /* Port set register */
|
||||
#define PIC32MX_IOPORT_PORTINV_OFFSET 0x001c /* Port invert register */
|
||||
#define PIC32MX_IOPORT_LAT_OFFSET 0x0020 /* Port data latch register */
|
||||
#define PIC32MX_IOPORT_LATCLR_OFFSET 0x0024 /* Port data latch clear register */
|
||||
#define PIC32MX_IOPORT_LATSET_OFFSET 0x0028 /* Port data latch set register */
|
||||
#define PIC32MX_IOPORT_LATINV_OFFSET 0x002c /* Port data latch invert register */
|
||||
#define PIC32MX_IOPORT_ODC_OFFSET 0x0030 /* Open drain control register */
|
||||
#define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0034 /* Open drain control clear register */
|
||||
#define PIC32MX_IOPORT_ODCSET_OFFSET 0x0038 /* Open drain control set register */
|
||||
#define PIC32MX_IOPORT_ODCINV_OFFSET 0x003c /* Open drain control invert register */
|
||||
|
||||
/* Offsets relative to PIC32MX_IOPORTCN_K1BASE */
|
||||
|
||||
#define PIC32MX_IOPORT_CNCON_OFFSET 0x0000 /* Interrupt-on-change control register */
|
||||
#define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0004 /* Interrupt-on-change control clear register */
|
||||
#define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0008 /* Interrupt-on-change control set register */
|
||||
#define PIC32MX_IOPORT_CNCONINV_OFFSET 0x000c /* Interrupt-on-change control invert register */
|
||||
#define PIC32MX_IOPORT_CNEN_OFFSET 0x0010 /* Input change notification interrupt enable */
|
||||
#define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0014 /* Input change notification interrupt enable clear */
|
||||
#define PIC32MX_IOPORT_CNENSET_OFFSET 0x0018 /* Input change notification interrupt enable set */
|
||||
#define PIC32MX_IOPORT_CNENINV_OFFSET 0x001c /* Input change notification interrupt enable invert */
|
||||
#define PIC32MX_IOPORT_CNPUE_OFFSET 0x0020 /* Input change notification pull-up enable */
|
||||
#define PIC32MX_IOPORT_CNPUECLR_OFFSET 0x0024 /* Input change notification pull-up enable clear */
|
||||
#define PIC32MX_IOPORT_CNPUESET_OFFSET 0x0028 /* Input change notification pull-up enable set */
|
||||
#define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define PIC32MX_IOPORT_TRIS(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_LAT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODC(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTA_TRIS (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LAT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODC (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTB_TRIS (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LAT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODC (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTC_TRIS (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LAT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODC (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTD_TRIS (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LAT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODC (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTE_TRIS (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LAT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODC (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTF_TRIS (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LAT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODC (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTG_TRIS (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LAT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODC (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORT_CNCON (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNEN (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUE (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUE_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUECLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUECLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUESET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUESET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***********************************************************/
|
||||
|
||||
/* Tri-state register */
|
||||
|
||||
#define IOPORT_TRIS(n) (1 << (n)) /* Bits 0-15: 1: Input 0: Output */
|
||||
|
||||
/* Port register */
|
||||
|
||||
#define IOPORT_PORT(n) (1 << (n)) /* Bits 0-15: Pin value */
|
||||
|
||||
/* Port data latch register */
|
||||
|
||||
#define IOPORT_LAT(n) (1 << (n)) /* Bits 0-15: Port latch value */
|
||||
|
||||
/* Open drain control register */
|
||||
|
||||
#define IOPORT_ODC(n) (1 << (n)) /* Bits 0-15: 1: OD output enabled, 0: Disabled */
|
||||
|
||||
/* Interrupt-on-change control register */
|
||||
|
||||
#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define IOPORT_CNCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
|
||||
#define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */
|
||||
|
||||
/* Input change notification interrupt enable */
|
||||
|
||||
#define IOPORT_CNEN(n) (1 << (n)) /* Bits 0-18/21: Port pin input change notice enabled */
|
||||
|
||||
/* Input change notification pull-up enable */
|
||||
|
||||
#define IOPORT_CNPUE(n) (1 << (n)) /* Bits 0-18/21: Port pin pull-up enabled */
|
||||
|
||||
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
|
||||
# define IOPORT_CN_ALL 0x0007ffff /* Bits 0-18 */
|
||||
# define IOPORT_NUMCN 19
|
||||
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
|
||||
# define IOPORT_CN_ALL 0x003fffff /* Bits 0-21 */
|
||||
# define IOPORT_NUMCN 22
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/********************************************************************************************
|
||||
* Inline Functions
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Function Prototypes
|
||||
********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H */
|
||||
/********************************************************************************************
|
||||
* arch/mips/src/pic32mx/pic32mx-ioport.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "pic32mx-memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
********************************************************************************************/
|
||||
/* Register Offsets *************************************************************************/
|
||||
/* Offsets relative to PIC32MX_IOPORTn_K1BASE */
|
||||
|
||||
#define PIC32MX_IOPORT_TRIS_OFFSET 0x0000 /* Tri-state register */
|
||||
#define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0004 /* Tri-state clear register */
|
||||
#define PIC32MX_IOPORT_TRISSET_OFFSET 0x0008 /* Tri-state set register */
|
||||
#define PIC32MX_IOPORT_TRISINV_OFFSET 0x000c /* Tri-state invert register */
|
||||
#define PIC32MX_IOPORT_PORT_OFFSET 0x0010 /* Port register */
|
||||
#define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0014 /* Port clear register */
|
||||
#define PIC32MX_IOPORT_PORTSET_OFFSET 0x0018 /* Port set register */
|
||||
#define PIC32MX_IOPORT_PORTINV_OFFSET 0x001c /* Port invert register */
|
||||
#define PIC32MX_IOPORT_LAT_OFFSET 0x0020 /* Port data latch register */
|
||||
#define PIC32MX_IOPORT_LATCLR_OFFSET 0x0024 /* Port data latch clear register */
|
||||
#define PIC32MX_IOPORT_LATSET_OFFSET 0x0028 /* Port data latch set register */
|
||||
#define PIC32MX_IOPORT_LATINV_OFFSET 0x002c /* Port data latch invert register */
|
||||
#define PIC32MX_IOPORT_ODC_OFFSET 0x0030 /* Open drain control register */
|
||||
#define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0034 /* Open drain control clear register */
|
||||
#define PIC32MX_IOPORT_ODCSET_OFFSET 0x0038 /* Open drain control set register */
|
||||
#define PIC32MX_IOPORT_ODCINV_OFFSET 0x003c /* Open drain control invert register */
|
||||
|
||||
/* Offsets relative to PIC32MX_IOPORTCN_K1BASE */
|
||||
|
||||
#define PIC32MX_IOPORT_CNCON_OFFSET 0x0000 /* Interrupt-on-change control register */
|
||||
#define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0004 /* Interrupt-on-change control clear register */
|
||||
#define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0008 /* Interrupt-on-change control set register */
|
||||
#define PIC32MX_IOPORT_CNCONINV_OFFSET 0x000c /* Interrupt-on-change control invert register */
|
||||
#define PIC32MX_IOPORT_CNEN_OFFSET 0x0010 /* Input change notification interrupt enable */
|
||||
#define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0014 /* Input change notification interrupt enable clear */
|
||||
#define PIC32MX_IOPORT_CNENSET_OFFSET 0x0018 /* Input change notification interrupt enable set */
|
||||
#define PIC32MX_IOPORT_CNENINV_OFFSET 0x001c /* Input change notification interrupt enable invert */
|
||||
#define PIC32MX_IOPORT_CNPUE_OFFSET 0x0020 /* Input change notification pull-up enable */
|
||||
#define PIC32MX_IOPORT_CNPUECLR_OFFSET 0x0024 /* Input change notification pull-up enable clear */
|
||||
#define PIC32MX_IOPORT_CNPUESET_OFFSET 0x0028 /* Input change notification pull-up enable set */
|
||||
#define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define PIC32MX_IOPORT_TRIS(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_TRISINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_PORTINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_LAT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_LATINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODC(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_ODCINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTA_TRIS (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_TRISINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_PORTINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LAT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_LATINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODC (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTA_ODCINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTB_TRIS (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_TRISINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_PORTINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LAT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_LATINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODC (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTB_ODCINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTC_TRIS (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_TRISINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_PORTINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LAT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_LATINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODC (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTC_ODCINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTD_TRIS (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_TRISINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_PORTINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LAT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_LATINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODC (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTD_ODCINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTE_TRIS (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_TRISINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_PORTINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LAT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_LATINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODC (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTE_ODCINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTF_TRIS (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_TRISINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_PORTINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LAT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_LATINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODC (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTF_ODCINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORTG_TRIS (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_TRISINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORT_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_PORTINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LAT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LAT_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_LATINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODC (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODC_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET)
|
||||
#define PIC32MX_IOPORTG_ODCINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET)
|
||||
|
||||
#define PIC32MX_IOPORT_CNCON (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNCONINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNEN (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNENINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUE (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUE_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUECLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUECLR_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUESET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUESET_OFFSET)
|
||||
#define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***********************************************************/
|
||||
|
||||
/* Tri-state register */
|
||||
|
||||
#define IOPORT_TRIS(n) (1 << (n)) /* Bits 0-15: 1: Input 0: Output */
|
||||
|
||||
/* Port register */
|
||||
|
||||
#define IOPORT_PORT(n) (1 << (n)) /* Bits 0-15: Pin value */
|
||||
|
||||
/* Port data latch register */
|
||||
|
||||
#define IOPORT_LAT(n) (1 << (n)) /* Bits 0-15: Port latch value */
|
||||
|
||||
/* Open drain control register */
|
||||
|
||||
#define IOPORT_ODC(n) (1 << (n)) /* Bits 0-15: 1: OD output enabled, 0: Disabled */
|
||||
|
||||
/* Interrupt-on-change control register */
|
||||
|
||||
#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
|
||||
#define IOPORT_CNCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
|
||||
#define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */
|
||||
|
||||
/* Input change notification interrupt enable */
|
||||
|
||||
#define IOPORT_CNEN(n) (1 << (n)) /* Bits 0-18/21: Port pin input change notice enabled */
|
||||
|
||||
/* Input change notification pull-up enable */
|
||||
|
||||
#define IOPORT_CNPUE(n) (1 << (n)) /* Bits 0-18/21: Port pin pull-up enabled */
|
||||
|
||||
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
|
||||
# define IOPORT_CN_ALL 0x0007ffff /* Bits 0-18 */
|
||||
# define IOPORT_NUMCN 19
|
||||
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
|
||||
# define IOPORT_CN_ALL 0x003fffff /* Bits 0-21 */
|
||||
# define IOPORT_NUMCN 22
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/********************************************************************************************
|
||||
* Inline Functions
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Function Prototypes
|
||||
********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H */
|
||||
|
|
|
|||
|
|
@ -762,3 +762,13 @@ Where <subdir> is one of the following:
|
|||
CONFIGURED_APPS += examples/nximage :
|
||||
CONFIGURED_APPS += examples/nxlines :
|
||||
|
||||
Enabling touch screen support in the nsh configuaration
|
||||
-------------------------------------------------------
|
||||
|
||||
In defconfig (or nuttx/.config), set:
|
||||
|
||||
CONFIG_INPUT=y
|
||||
|
||||
In appconfig (or apps/.config), uncomment:
|
||||
|
||||
CONFIGURED_APPS += examples/touchscreen
|
||||
|
|
|
|||
|
|
@ -124,3 +124,9 @@ ifeq ($(CONFIG_NX),y)
|
|||
#CONFIGURED_APPS += examples/nximage
|
||||
#CONFIGURED_APPS += examples/nxlines
|
||||
endif
|
||||
|
||||
# Uncomment to enable the touchscreen test
|
||||
|
||||
ifeq ($(CONFIG_INPUT),y)
|
||||
#CONFIGURED_APPS += examples/touchscreen
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1567,6 +1567,28 @@ CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb
|
|||
CONFIG_EXAMPLES_NXLINES_BPP=16
|
||||
CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n
|
||||
|
||||
#
|
||||
# Settings for examples/touchscreen
|
||||
#
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN - Build the touchscreen test as
|
||||
# an NSH built-in function. Default: Built as a standalone problem
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN_MINOR - The minor device number. Minor=N
|
||||
# correspnds to touchscreen device /dev/input0. Note this value must
|
||||
# with CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH. Default 0.
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH - The path to the touchscreen
|
||||
# device. This must be consistent with CONFIG_EXAMPLES_TOUCHSCREEN_MINOR.
|
||||
# Default: "/dev/input0"
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES - If CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN
|
||||
# is defined, then the number of samples is provided on the command line
|
||||
# and this value is ignored. Otherwise, this number of samples is
|
||||
# collected and the program terminates. Default: Samples are collected
|
||||
# indefinitely.
|
||||
#
|
||||
CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y
|
||||
CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0
|
||||
CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0"
|
||||
CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25
|
||||
|
||||
#
|
||||
# Settings for examples/usbserial
|
||||
#
|
||||
|
|
|
|||
|
|
@ -55,6 +55,10 @@ ifeq ($(CONFIG_USBMSC),y)
|
|||
CSRCS += up_usbmsc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_INPUT),y)
|
||||
CSRCS += up_touchscreen.c
|
||||
endif
|
||||
|
||||
AOBJS = $(ASRCS:.S=$(OBJEXT))
|
||||
COBJS = $(CSRCS:.c=$(OBJEXT))
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue