From 982ae4f2a098c7c219f76d7d1c3ab28d6a34bdb5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 6 Dec 2011 19:31:28 +0000 Subject: [PATCH] Basic bring-up of the STM3240G-EVAL board is complete git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4138 7fd9a85b-ad96-42d3-883c-3090e2eb8679 --- nuttx/ChangeLog | 4 +++- nuttx/arch/arm/src/stm32/stm32_gpio.c | 4 ++-- nuttx/configs/stm3240g-eval/include/board.h | 12 ++++++------ 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 51acad5a4..916c9a6c2 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -2237,4 +2237,6 @@ * arch/arm/src/stm32: Fixes to several STM32F40xxx files (contributed by Mikhail Bychek). * configs/stm3210e-eval/src/up_lcd.c: Fix banding problem on the R61580 - LCD \ No newline at end of file + LCD + * configs/stm3240g-eval/ostest: The basic STM32F40xx bringup is functional + (11/12/06) and passes the OS test. diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c index a22d20883..309df3520 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c @@ -515,8 +515,8 @@ int stm32_configgpio(uint32_t cfgset) } regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); - regval &= ~GPIO_OSPEED_MASK(pos); - regval |= (setting << GPIO_OSPEED_SHIFT(pos)); + regval &= ~GPIO_OSPEED_MASK(pin); + regval |= (setting << GPIO_OSPEED_SHIFT(pin)); putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ diff --git a/nuttx/configs/stm3240g-eval/include/board.h b/nuttx/configs/stm3240g-eval/include/board.h index b66997235..8ed766343 100755 --- a/nuttx/configs/stm3240g-eval/include/board.h +++ b/nuttx/configs/stm3240g-eval/include/board.h @@ -124,16 +124,16 @@ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1