Add SPI buffer read/write logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2629 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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21541f4944
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97642a3d3d
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@ -163,6 +163,9 @@ static inline uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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static uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
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static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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#endif
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/* SPI control register access */
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static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd);
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static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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@ -173,6 +176,13 @@ static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg);
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/* SPI buffer transfers */
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static void enc28j60_rdbuffer(FAR struct enc28j60_driver_s *priv,
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FAR uint8_t *buffer, size_t buflen);
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static void enc28j60_wrbuffer(FAR struct enc28j60_driver_s *priv,
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FAR const uint8_t *buffer, size_t buflen);
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/* Common TX logic */
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static int enc28j60_transmit(FAR struct enc28j60_driver_s *priv);
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@ -240,7 +250,7 @@ static inline uint8_t enc28j60_select(FAR struct spi_dev_s *spi)
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#else
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static uint8_t enc28j60_select(FAR struct spi_dev_s *spi)
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{
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/* Select ENC2J60 chip (locking the SPI bus in case there are multiple
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/* Select ENC28J60 chip (locking the SPI bus in case there are multiple
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* devices competing for the SPI bus
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*/
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@ -302,7 +312,7 @@ static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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@ -333,7 +343,7 @@ static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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@ -350,6 +360,72 @@ static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_rdbuffer
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*
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* Description:
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* Read a buffer of data.
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*
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****************************************************************************/
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static void enc28j60_rdbuffer(FAR struct enc28j60_driver_s *priv,
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FAR uint8_t *buffer, size_t buflen)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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/* Send the read buffer memory command (ignoring the response) */
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(void)SPI_SEND(spi, ENC28J60_RBM);
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/* Then read the buffer data */
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SPI_RECVBLOCK(spi, buffer, buflen);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_wrbuffer
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*
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* Description:
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* Write a buffer of data.
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*
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****************************************************************************/
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static void enc28j60_wrbuffer(FAR struct enc28j60_driver_s *priv,
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FAR const uint8_t *buffer, size_t buflen)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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/* Send the write buffer memory command (ignoring the response) */
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(void)SPI_SEND(spi, ENC28J60_WBM);
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/* Then send the buffer */
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SPI_SNDBLOCK(spi, buffer, buflen);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_setbank
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*
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@ -401,7 +477,7 @@ static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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@ -438,7 +514,7 @@ static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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@ -476,7 +552,7 @@ static void enc28j60_wrbank(FAR struct enc28j60_driver_s *priv,
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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/* Select ENC28J60 chip */
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enc28j60_select(spi);
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@ -101,6 +101,111 @@
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#define GETADDR(a) ((a) & ENC28J60_ADDR_MASK)
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#define GETBANK(a) (((a) >> ENC28J60_BANK_SHIFT) & 3)
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/* Bank 0 Control Register Addresses */
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#define ERDPTL REGADDR(0x00, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
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#define ERDPTH REGADDR(0x01, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
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#define EWRPTL REGADDR(0x02, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
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#define EWRPTH REGADDR(0x03, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
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#define ETXSTL REGADDR(0x04, 0) /* TX Start Low Byte (ETXST<7:0>) */
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#define ETXSTH REGADDR(0x05, 0) /* TX Start High Byte (ETXST<12:8>) */
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#define ETXNDL REGADDR(0x06, 0) /* TX End Low Byte (ETXND<7:0>) */
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#define ETXNDH REGADDR(0x07, 0) /* TX End High Byte (ETXND<12:8>) */
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#define ERXSTL REGADDR(0x08, 0) /* RX Start Low Byte (ERXST<7:0>) */
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#define ERXSTH REGADDR(0x09, 0) /* RX Start High Byte (ERXST<12:8>) */
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#define ERXNDL REGADDR(0x0a, 0) /* RX End Low Byte (ERXND<7:0>) */
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#define ERXNDH REGADDR(0x0b, 0) /* RX End High Byte (ERXND<12:8>) */
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#define ERXRDPTL REGADDR(0x0c, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
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#define ERXRDPTH REGADDR(0x0d, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
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#define ERXWRPTL REGADDR(0x0e, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
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#define ERXWRPTH REGADDR(0x0f, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
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#define EDMASTL REGADDR(0x10, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
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#define EDMASTH REGADDR(0x11, 0) /* DMA Start High Byte (EDMAST<12:8>) */
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#define EDMANDL REGADDR(0x12, 0) /* DMA End Low Byte (EDMAND<7:0>) */
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#define EDMANDH REGADDR(0x13, 0) /* DMA End High Byte (EDMAND<12:8>) */
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#define EDMADSTL REGADDR(0x14, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
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#define EDMADSTH REGADDR(0x15, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
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#define EDMACSL REGADDR(0x16, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
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#define EDMACSH REGADDR(0x17, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
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/* 0x18-0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Bank 1 Control Register Addresses */
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#define EHT0 REGADDR(0x00, 1) /* Hash Table Byte 0 (EHT<7:0>) */
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#define EHT1 REGADDR(0x01, 1) /* Hash Table Byte 1 (EHT<15:8>) */
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#define EHT2 REGADDR(0x02, 1) /* Hash Table Byte 2 (EHT<23:16>) */
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#define EHT3 REGADDR(0x03, 1) /* Hash Table Byte 3 (EHT<31:24>) */
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#define EHT4 REGADDR(0x04, 1) /* Hash Table Byte 4 (EHT<39:32>) */
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#define EHT5 REGADDR(0x05, 1) /* Hash Table Byte 5 (EHT<47:40>) */
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#define EHT6 REGADDR(0x06, 1) /* Hash Table Byte 6 (EHT<55:48>) */
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#define EHT7 REGADDR(0x07, 1) /* Hash Table Byte 7 (EHT<63:56>) */
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#define EPMM0 REGADDR(0x08, 1) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
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#define EPMM1 REGADDR(0x09, 1) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
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#define EPMM2 REGADDR(0x0a, 1) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
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#define EPMM3 REGADDR(0x0b, 1) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
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#define EPMM4 REGADDR(0x0c, 1) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
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#define EPMM5 REGADDR(0x0d, 1) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
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#define EPMM6 REGADDR(0x0e, 1) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
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#define EPMM7 REGADDR(0x0f, 1) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
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#define EPMCSL REGADDR(0x10, 1) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
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#define EPMCSH REGADDR(0x11, 1) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
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/* 0x12-0x13: Reserved */
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#define EPMOL REGADDR(0x14, 1) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
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#define EPMOH REGADDR(0x15, 1) /* Pattern Match Offset High Byte (EPMO<12:8>) */
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/* 0x16-0x17: Reserved */
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#define ERXFCON REGADDR(0x18, 1) /* Receive Filter Configuration */
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#define EPKTCNT REGADDR(0x19, 1) /* Ethernet Packet Count */
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Bank 2 Control Register Addresses */
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#define MACON1 REGADDR(0x00, 2) /* MAC control 1 */
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#define MACON2 REGADDR(0x01, 2) /* MAC control 2 */
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#define MACON3 REGADDR(0x02, 2) /* MAC control 3 */
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#define MACON4 REGADDR(0x03, 2) /* MAC control 4 */
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#define MABBIPG REGADDR(0x04, 2) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
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/* 0x05: Reserved */
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#define MAIPGL REGADDR(0x06, 2) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
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#define MAIPGH REGADDR(0x07, 2) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
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#define MACLCON1 REGADDR(0x08, 2) /* MAC Collision Control 1 */
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#define MACLCON2 REGADDR(0x09, 2) /* MAC Collision Control 2 */
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#define MAMXFLL REGADDR(0x0a, 2) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
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#define MAMXFLH REGADDR(0x0b, 2) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
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/* 0x0c-0x11: Reserved */
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#define MICMD REGADDR(0x12, 2) /* MII Command Register */
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/* 0x13: Reserved */
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#define MIREGADR REGADDR(0x14, 2) /* MII Register Address */
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/* 0x15: Reserved */
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#define MIWRL REGADDR(0x16, 2) /* MII Write Data Low Byte (MIWR<7:0>) */
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#define MIWRH REGADDR(0x17, 2) /* MII Write Data High Byte (MIWR<15:8>) */
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#define MIRDL REGADDR(0x18, 2) /* MII Read Data Low Byte (MIRD<7:0>) */
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#define MIRDH REGADDR(0x19, 2) /* MII Read Data High Byte(MIRD<15:8>) */
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Bank 3 Control Register Addresses */
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#define MAADR5 REGADDR(0x00, 3) /* MAC Address Byte 5 (MAADR<15:8>) */
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#define MAADR6 REGADDR(0x01, 3) /* MAC Address Byte 6 (MAADR<7:0>) */
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#define MAADR3 REGADDR(0x02, 3) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
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#define MAADR4 REGADDR(0x03, 3) /* MAC Address Byte 4 (MAADR<23:16>) */
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#define MAADR1 REGADDR(0x04, 3) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
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#define MAADR2 REGADDR(0x05, 3) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */
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#define EBSTSD REGADDR(0x06, 3) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
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#define EBSTCON REGADDR(0x07, 3) /* Built-in Self-Test Control */
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#define EBSTCSL REGADDR(0x08, 3) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
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#define EBSTCSH REGADDR(0x09, 3) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
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#define MISTAT REGADDR(0x0a, 3) /* MII Status Register */
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/* 0x0b-0x11: Reserved */
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#define EREVID REGADDR(0x12, 3) /* Ethernet Revision ID */
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/* 0x13-0x14: Reserved */
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#define ECOCON REGADDR(0x15, 3) /* Clock Output Control */
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/* 0x16: Reserved */
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#define EFLOCON REGADDR(0x17, 3) /* Ethernet Flow Control */
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#define EPAUSL REGADDR(0x18, 3) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
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#define EPAUSH REGADDR(0x19, 3) /* Pause Timer Value High Byte (EPAUS<15:8>) */
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Ethernet Interrupt Enable Register Bit Definitions */
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
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