First cut at ez80 boot logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@736 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
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946bb5a6d5
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@ -143,8 +143,9 @@
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#ifdef CONFIG_EZ80_Z80MODE
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/* Byte offsets */
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# define XCPT_I16_OFFSET (2*XCPT_I) /* Offset 0: 16-bit interrupt vector register */
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# define XCPT_I_OFFSET (2*XCPT_I+1) /* Offset 1: 8-bit interrupt vector register */
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# define XCPT_I_OFFSET (2*XCPT_I) /* Offset 0: 16-bit interrupt vector register */
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# define XCPT_IF_OFFSET (2*XCPT_I+0) /* Offset 1: Saved flags. P set if interrupts enabled */
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# define XCPT_IA_OFFSET (2*XCPT_I+1) /* Offset 2: Saved lower 8-bits of interrupt vector register */
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# define XCPT_BC_OFFSET (2*XCPT_BC) /* Offset 2: Saved 16-bit BC register */
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# define XCPT_C_OFFSET (2*XCPT_BC+0) /* Offset 2: Saved 8-bit C register */
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# define XCPT_B_OFFSET (2*XCPT_BC+1) /* Offset 3: Saved 8-bit D register */
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@ -165,8 +166,9 @@
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#else
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/* Byte offsets */
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# define XCPT_I24_OFFSET (3*XCPT_I) /* Offset 0: Saved 24-bit interrupt vector register */
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# define XCPT_I_OFFSET (3*XCPT_I+2) /* Offset 2: Saved 8-bit interrupt vector register */
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# define XCPT_I_OFFSET (3*XCPT_I) /* Offset 0: Saved 24-bit interrupt vector register */
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# define XCPT_IF_OFFSET (2*XCPT_I+1) /* Offset 1: Saved flags. P set if interrupts enabled */
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# define XCPT_IA_OFFSET (2*XCPT_I+2) /* Offset 2: Saved lower 8-bits of interrupt vector register */
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# define XCPT_BC_OFFSET (3*XCPT_BC) /* Offset 3: Saved 24-bit BC register */
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# define XCPT_C_OFFSET (3*XCPT_BC+1) /* Offset 4: Saved 8-bit C register */
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# define XCPT_B_OFFSET (3*XCPT_BC+2) /* Offset 5: Saved 8-bit D register */
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@ -33,7 +33,8 @@
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#
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############################################################################
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HEAD_SSRC = ez80_head.S
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HEAD_ASRC = ez80_vectors.asm
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HEAD_SSRC =
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CMN_SSRCS =
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CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \
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@ -42,8 +43,11 @@ CMN_CSRCS = up_initialize.c up_allocateheap.c up_createstack.c \
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up_reprioritizertr.c up_idle.c up_assert.c up_doirq.c \
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up_mdelay.c up_udelay.c up_usestack.c
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CHIP_SSRCS = ez80_vector.S ez80_saveusercontext.S ez80_restorecontext.S
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CHIP_ASRCS = ez80_startup.asm ez80_saveusercontext.asm ez80_restorecontext.asm
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ifeq ($(_EZ80F91),y)
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CHIP_ASRCS += ez80f91_init.asm
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endif
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CHIP_SSRCS =
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CHIP_CSRCS = ez80_initialstate.c ez80_irq.c ez80_saveirqcontext.c \
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ez80_schedulesigaction.c ez80_sigdeliver.c ez80_timerisr.c \
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ez80_lowuart.c ez80_serial.c ez80_registerdump.c
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@ -45,13 +45,14 @@
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* Definitions
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************************************************************************************/
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/* Hexadecimal Representation *******************************************************/
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/* Bits in the Z80 FLAGS register ***************************************************/
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#ifdef __ASSEMBLY__
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# define _HX(h) %##h
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#else
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# define _HX(h) 0x##h
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#endif
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#define EZ80_C_FLAG 0x01 /* Bit 0: Carry flag */
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#define EZ80_N_FLAG 0x02 /* Bit 1: Add/Subtract flag */
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#define EZ80_PV_FLAG 0x04 /* Bit 2: Parity/Overflow flag */
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#define EZ80_H_FLAG 0x10 /* Bit 4: Half carry flag */
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#define EZ80_Z_FLAG 0x40 /* Bit 5: Zero flag */
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#define EZ80_S_FLAG 0x80 /* Bit 7: Sign flag */
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/* Memory Map */
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/* Special Function Registers *******************************************************
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@ -0,0 +1,93 @@
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/****************************************************************************
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* arch/z80/src/ez80/ez80_initialstate.c
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <string.h>
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#include <nuttx/arch.h>
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#include "chip/chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_initial_state
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*
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* Description:
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* A new thread is being started and a new TCB
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* has been created. This function is called to initialize
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* the processor specific portions of the new TCB.
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*
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* This function must setup the intial architecture registers
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* and/or stack so that execution will begin at tcb->start
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* on the next context switch.
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*
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****************************************************************************/
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void up_initial_state(_TCB *tcb)
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{
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struct xcptcontext *xcp = &tcb->xcp;
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chireg_t *regs = xcp->regs;
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/* Initialize the initial exception register context structure */
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memset(xcp, 0, sizeof(struct xcptcontext));
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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((ubyte*)regs)[XCPT_IF_OFFSET] = EZ80_PV_FLAG; /* Parity/Overflow flag will enable interrupts */
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#endif
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regs[XCPT_SP] = (chipreg_t)tcb->adj_stack_ptr;
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regs[XCPT_PC] = (chipreg_t)tcb->start;
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}
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@ -0,0 +1,155 @@
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;**************************************************************************
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; arch/z80/src/ez80/ez80_startup.asm
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;
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; Copyright (C) 2008 Gregory Nutt. All rights reserved.
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; Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; 1. Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
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||||
; 2. Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
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; distribution.
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; 3. Neither the name NuttX nor the names of its contributors may be
|
||||
; used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
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||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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; POSSIBILITY OF SUCH DAMAGE.
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;
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;**************************************************************************
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;**************************************************************************
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; Included Files
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;**************************************************************************
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;**************************************************************************
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; Constants
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;**************************************************************************
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;**************************************************************************
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; Global symbols used
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;**************************************************************************
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xref __stack
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xref _ez80_init
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xref _ez80_initvectors
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xref _ez80_initsysclk
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xref _up_lowinit
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xref __low_bss ; Low address of bss segment
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xref __len_bss ; Length of bss segment
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xref __low_data ; Address of initialized data section
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xref __low_romdata ; Addr of initialized data section in ROM
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xref __len_data ; Length of initialized data section
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xref __copy_code_to_ram
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xref __len_code
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xref __low_code
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xref __low_romcode
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xref __open_periphdevice
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xref __close_periphdevice
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xref _os_start
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xdef _ez80_startup
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xdef _ez80_halt
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;**************************************************************************
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; System reset start logic
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;**************************************************************************
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_ez80_startup:
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; Set up the stack pointer at the location determined the lincmd
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; file
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ld sp, __stack
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; Peform chip-specific initialization
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call _ez80_init
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; initialize the interrupt vector table
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call _ez80_initvectors
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; Initialize the system clock
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call _ez80_initsysclk
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; Perform C initializations
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; Clear the uninitialized data section
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ld bc, __len_bss ; Check for non-zero length
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ld a, __len_bss >> 16
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or a, c
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or a, b
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jr z, _ez80_bssdone ; BSS is zero-length ...
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xor a, a
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ld (__low_bss), a
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sbc hl, hl ; hl = 0
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dec bc ; 1st byte's taken care of
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sbc hl, bc
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jr z, _ez80_bssdone ; Just 1 byte ...
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ld hl, __low_bss ; reset hl
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ld de, __low_bss + 1 ; [de] = bss + 1
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ldir
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_ez80_bssdone:
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; Copy the initialized data section
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ld bc, __len_data ; [bc] = data length
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ld a, __len_data >> 16 ; Check for non-zero length
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or a, c
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or a, b
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jr z, _ez80_datadone ; __len_data is zero-length ...
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ld hl, __low_romdata ; [hl] = data_copy
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ld de, __low_data ; [de] = data
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ldir ; Copy the data section
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_ez80_datadone:
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; Copy CODE (which may be in FLASH) to RAM if the
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; copy_code_to_ram symbol is set in the link control file
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ld a, __copy_code_to_ram
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or a, a
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jr z, _ez80_codedone
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ld bc, __len_code ; [bc] = code length
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ld a, __len_code >> 16 ; Check for non-zero length
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or a, c
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or a, b
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jr z, _ez80_codedone ; __len_code is zero-length
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ld hl, __low_romcode ; [hl] = code_copy
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ld de, __low_code ; [de] = code
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ldir ; Copy the code section
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_ez80_codedone:
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; Initialize the peripheral devices
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call __open_periphdevice
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; Perform board-specific intialization
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call _up_lowinit
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; Then start NuttX
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call _os_start ; jump to the OS entry point
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; NuttX will never return, but just in case...
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call __close_periphdevice
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_ez80_halt::
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halt ; We should never get here
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jp _ez80_halt
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@ -0,0 +1,314 @@
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;**************************************************************************
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; arch/z80/src/ez80/ez80_vectors.asm
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;
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; Copyright (C) 2008 Gregory Nutt. All rights reserved.
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; Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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;
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; Redistribution and use in source and binary forms, with or without
|
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; modification, are permitted provided that the following conditions
|
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; are met:
|
||||
;
|
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; 1. Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
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; distribution.
|
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; 3. Neither the name NuttX nor the names of its contributors may be
|
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; used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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; POSSIBILITY OF SUCH DAMAGE.
|
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;
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;**************************************************************************
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;**************************************************************************
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; Constants
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;**************************************************************************
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NVECTORS EQU 64 ; max possible interrupt vectors
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;**************************************************************************
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; Global symbols used
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;**************************************************************************
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xref _ez80_startup
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xdef _ez80_reset
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xdef _ez80_initvectors
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xdef _ez80_handlers
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xdef _ez80_rstcommon
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xdef _ez80_initvectors
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xdef _ez80_vectable
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;**************************************************************************
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; Macros
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;**************************************************************************
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; Define one reset handler
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; 1. Disable interrupts
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; 2. Dlear mixed memory mode (MADL) flag
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; 3. jump to initialization procedure with jp.lil to set ADL
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rstvector: macro
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di
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rsmix
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jp.lil _ez80_startup
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endmac rstvector
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; Define one interrupt handler
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irqhandler: macro vectno
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #vectno ; A = vector number
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jr _ez80_rstcommon ; Remaining RST handling is common
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endmac irqhandler
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; Save Interrupt State
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irqsave: macro
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ld a, i ; sets parity bit to value of IEF2
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push af
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di ; disable interrupts while loading table
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endmac irqsave
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; Restore Interrupt State
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irqrestore: macro
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pop af
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jp po, $+5 ; parity bit is IEF2
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ei
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endmac irqrestore
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;**************************************************************************
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; Reset entry points
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;**************************************************************************
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define .RESET, space = ROM
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segment .RESET
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_ez80_reset:
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_rst0:
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rstvector
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_rst8:
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rstvector
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_rst10:
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rstvector
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_rst18:
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rstvector
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_rst20:
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rstvector
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_rst28:
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rstvector
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_rst30:
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rstvector
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_rst38:
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rstvector
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ds %26
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_nmi:
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retn
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;**************************************************************************
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; Startup logic
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;**************************************************************************
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define .STARTUP, space = ROM
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segment .STARTUP
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.assume ADL=1
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;**************************************************************************
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; Interrupt Vector Handling
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;**************************************************************************
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_ez80_handlers:
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irqhandler 0
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handlersize equ . - _ez80handlers
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irqhandler 1
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irqhandler 2
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irqhandler 3
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irqhandler 4
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irqhandler 5
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irqhandler 6
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irqhandler 7
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irqhandler 8
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irqhandler 9
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irqhandler 10
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irqhandler 11
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irqhandler 12
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irqhandler 13
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irqhandler 14
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irqhandler 15
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irqhandler 16
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irqhandler 17
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irqhandler 18
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irqhandler 19
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irqhandler 20
|
||||
irqhandler 21
|
||||
irqhandler 22
|
||||
irqhandler 23
|
||||
irqhandler 24
|
||||
irqhandler 25
|
||||
irqhandler 26
|
||||
irqhandler 27
|
||||
irqhandler 28
|
||||
irqhandler 29
|
||||
irqhandler 30
|
||||
irqhandler 31
|
||||
irqhandler 32
|
||||
irqhandler 33
|
||||
irqhandler 34
|
||||
irqhandler 35
|
||||
irqhandler 36
|
||||
irqhandler 37
|
||||
irqhandler 38
|
||||
irqhandler 39
|
||||
irqhandler 40
|
||||
irqhandler 41
|
||||
irqhandler 42
|
||||
irqhandler 43
|
||||
irqhandler 44
|
||||
irqhandler 45
|
||||
irqhandler 46
|
||||
irqhandler 47
|
||||
irqhandler 48
|
||||
irqhandler 49
|
||||
irqhandler 50
|
||||
irqhandler 51
|
||||
irqhandler 52
|
||||
irqhandler 53
|
||||
irqhandler 54
|
||||
irqhandler 55
|
||||
irqhandler 56
|
||||
irqhandler 57
|
||||
irqhandler 58
|
||||
irqhandler 59
|
||||
irqhandler 60
|
||||
irqhandler 61
|
||||
irqhandler 62
|
||||
irqhandler 63
|
||||
|
||||
;**************************************************************************
|
||||
; Common Interrupt handler
|
||||
;**************************************************************************
|
||||
|
||||
_ez80_rstcommon::
|
||||
; Create a register frame. SP points to top of frame + 4, pushes
|
||||
; decrement the stack pointer. Already have
|
||||
;
|
||||
; Offset 8: Return PC is already on the stack
|
||||
; Offset 7: AF (retaining flags)
|
||||
;
|
||||
; IRQ number is in A
|
||||
|
||||
push hl ; Offset 6: HL
|
||||
ld hl, #(3*2) ; HL is the value of the stack pointer before
|
||||
add hl, sp ; the interrupt occurred
|
||||
push hl ; Offset 5: Stack pointer
|
||||
push iy ; Offset 4: IY
|
||||
push ix ; Offset 3: IX
|
||||
push de ; Offset 2: DE
|
||||
push bc ; Offset 1: BC
|
||||
|
||||
ld b, a ; Save the reset number in B
|
||||
ld a, i ; Carry bit holds interrupt state
|
||||
push af ; Offset 0: I with interrupt state in carry
|
||||
di
|
||||
|
||||
; Call the interrupt decode logic. SP points to the beggining of the reg structure
|
||||
|
||||
ld hl, #0 ; Argument #2 is the beginning of the reg structure
|
||||
add hl, sp ;
|
||||
push hl ; Place argument #2 at the top of stack
|
||||
push bc ; Argument #1 is the Reset number
|
||||
inc sp ; (make byte sized)
|
||||
call _up_doirq ; Decode the IRQ
|
||||
|
||||
; On return, HL points to the beginning of the reg structure to restore
|
||||
; Note that (1) the arguments pushed on the stack are not popped, and (2) the
|
||||
; original stack pointer is lost. In the normal case (no context switch),
|
||||
; HL will contain the value of the SP before the arguments wer pushed.
|
||||
|
||||
ld sp, hl ; Use the new stack pointer
|
||||
|
||||
; Restore registers. HL points to the beginning of the reg structure to restore
|
||||
|
||||
ex af, af' ; Select alternate AF
|
||||
pop af ; Offset 0: AF' = I with interrupt state in carry
|
||||
ex af, af' ; Restore original AF
|
||||
pop bc ; Offset 1: BC
|
||||
pop de ; Offset 2: DE
|
||||
pop ix ; Offset 3: IX
|
||||
pop iy ; Offset 4: IY
|
||||
exx ; Use alternate BC/DE/HL
|
||||
ld hl, #-2 ; Offset of SP to account for ret addr on stack
|
||||
pop de ; Offset 5: HL' = Stack pointer after return
|
||||
add hl, de ; HL = Stack pointer value before return
|
||||
exx ; Restore original BC/DE/HL
|
||||
pop hl ; Offset 6: HL
|
||||
pop af ; Offset 7: AF
|
||||
|
||||
; Restore the stack pointer
|
||||
|
||||
exx ; Use alternate BC/DE/HL
|
||||
ld sp, hl ; Set SP = saved stack pointer value before return
|
||||
exx ; Restore original BC/DE/HL
|
||||
|
||||
; Restore interrupt state
|
||||
|
||||
ex af, af' ; Recover interrupt state
|
||||
jr nc, nointenable ; No carry, IFF2=0, means disabled
|
||||
ex af, af' ; Restore AF (before enabling interrupts)
|
||||
ei ; yes
|
||||
reti
|
||||
nointenable::
|
||||
ex af, af' ; Restore AF
|
||||
reti
|
||||
|
||||
;**************************************************************************
|
||||
; Vector Setup Logic
|
||||
;**************************************************************************
|
||||
|
||||
_ez80_initvectors:
|
||||
; Initialize the vector table
|
||||
|
||||
ld hl, _vector_table
|
||||
ld b, NVECTORS
|
||||
ld iy, _ez80_handlers
|
||||
ld a, 0
|
||||
$1:
|
||||
ld (iy), hl ; Store IRQ handler
|
||||
ld (iy+3), a ; Pad to 4 bytes
|
||||
add hl, handlersize ; Point to next handler
|
||||
add iy, 4 ; Point to next entry in vector table
|
||||
djnz $2 ; Loop until all vectors have been written
|
||||
|
||||
; Select interrupt mode 2
|
||||
|
||||
im 2 ; Interrupt mode 2
|
||||
|
||||
; Write the address of the vector table into the interrupt vector base
|
||||
|
||||
ld hl, _ez80_vectable >> 8
|
||||
ld i, hl
|
||||
ret
|
||||
|
||||
;**************************************************************************
|
||||
; Vector Table
|
||||
;**************************************************************************
|
||||
; This segment must be aligned on a 512 byte boundary anywhere in RAM
|
||||
; Each entry will be a 3-byte address in a 4-byte space
|
||||
|
||||
define .IVECTS, space = RAM, align = 200h
|
||||
segment .IVECTS
|
||||
|
||||
_ez80_vectable:
|
||||
ds NVECTORS * 4
|
||||
|
|
@ -0,0 +1,253 @@
|
|||
;**************************************************************************
|
||||
; arch/z80/src/ez80/ez80f91_init.asm
|
||||
;
|
||||
; Copyright (C) 2008 Gregory Nutt. All rights reserved.
|
||||
; Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions
|
||||
; are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in
|
||||
; the documentation and/or other materials provided with the
|
||||
; distribution.
|
||||
; 3. Neither the name NuttX nor the names of its contributors may be
|
||||
; used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;**************************************************************************
|
||||
|
||||
;**************************************************************************
|
||||
; Included Files
|
||||
;**************************************************************************
|
||||
|
||||
include "ez80f91.inc"
|
||||
|
||||
;**************************************************************************
|
||||
; Constants
|
||||
;**************************************************************************
|
||||
|
||||
;PLL_DIV_L EQU %5C
|
||||
;PLL_DIV_H EQU %5D
|
||||
;PLL_CTL0 EQU %5E
|
||||
;PLL_CTL1 EQU %5F
|
||||
|
||||
OSC EQU 0
|
||||
PLL EQU 1
|
||||
RTC EQU 2
|
||||
|
||||
CLK_MUX_OSC EQU %00
|
||||
CLK_MUX_PLL EQU %01
|
||||
CLK_MUX_RTC EQU %02
|
||||
|
||||
CHRP_CTL_0 EQU %00
|
||||
CHRP_CTL_1 EQU %40
|
||||
CHRP_CTL_2 EQU %80
|
||||
CHRP_CTL_3 EQU %C0
|
||||
|
||||
LDS_CTL_0 EQU %00
|
||||
LDS_CTL_1 EQU %04
|
||||
LDS_CTL_2 EQU %08
|
||||
LDS_CTL_3 EQU %0C
|
||||
|
||||
LCK_STATUS EQU %20
|
||||
INT_LOCK EQU %10
|
||||
INT_UNLOCK EQU %08
|
||||
INT_LOCK_EN EQU %04
|
||||
INT_UNLOCK_EN EQU %02
|
||||
PLL_ENABLE EQU %01
|
||||
|
||||
;**************************************************************************
|
||||
; Global symbols used
|
||||
;**************************************************************************
|
||||
|
||||
xdef _ez80_init
|
||||
xref __CS0_LBR_INIT_PARAM
|
||||
xref __CS0_UBR_INIT_PARAM
|
||||
xref __CS0_CTL_INIT_PARAM
|
||||
xref __CS1_LBR_INIT_PARAM
|
||||
xref __CS1_UBR_INIT_PARAM
|
||||
xref __CS1_CTL_INIT_PARAM
|
||||
xref __CS2_LBR_INIT_PARAM
|
||||
xref __CS2_UBR_INIT_PARAM
|
||||
xref __CS2_CTL_INIT_PARAM
|
||||
xref __CS3_LBR_INIT_PARAM
|
||||
xref __CS3_UBR_INIT_PARAM
|
||||
xref __CS3_CTL_INIT_PARAM
|
||||
xref __CS0_BMC_INIT_PARAM
|
||||
xref __CS1_BMC_INIT_PARAM
|
||||
xref __CS2_BMC_INIT_PARAM
|
||||
xref __CS3_BMC_INIT_PARAM
|
||||
xref __FLASH_CTL_INIT_PARAM
|
||||
xref __FLASH_ADDR_U_INIT_PARAM
|
||||
xref __RAM_CTL_INIT_PARAM
|
||||
xref __RAM_ADDR_U_INIT_PARAM
|
||||
xref _SYS_CLK_SRC
|
||||
xref _SYS_CLK_FREQ
|
||||
xref _OSC_FREQ
|
||||
xref _OSC_FREQ_MULT
|
||||
xref __PLL_CTL0_INIT_PARAM
|
||||
|
||||
;**************************************************************************
|
||||
; Chip-specific initialization logic
|
||||
;**************************************************************************
|
||||
; Minimum default initialization for eZ80F91
|
||||
|
||||
define .STARTUP, space = ROM
|
||||
segment .STARTUP
|
||||
.assume ADL = 1
|
||||
|
||||
_ez80_init:
|
||||
; Disable internal peripheral interrupt sources
|
||||
|
||||
ld a, %ff
|
||||
out0 (PA_DDR), a ; GPIO
|
||||
out0 (PB_DDR), a
|
||||
out0 (PC_DDR), a
|
||||
out0 (PD_DDR), a
|
||||
ld a, %00
|
||||
out0 (PA_ALT1), a
|
||||
out0 (PB_ALT1), a
|
||||
out0 (PC_ALT1), a
|
||||
out0 (PD_ALT1), a
|
||||
out0 (PA_ALT2), a
|
||||
out0 (PB_ALT2), a
|
||||
out0 (PC_ALT2), a
|
||||
out0 (PD_ALT2), a
|
||||
out0 (PLL_CTL1), a ; PLL
|
||||
out0 (TMR0_IER), a ; timers
|
||||
out0 (TMR1_IER), a
|
||||
out0 (TMR2_IER), a
|
||||
out0 (TMR3_IER), a
|
||||
out0 (UART0_IER), a ; UARTs
|
||||
out0 (UART1_IER), a
|
||||
out0 (I2C_CTL), a ; I2C
|
||||
out0 (EMAC_IEN), a ; EMAC
|
||||
out0 (FLASH_IRQ), a ; Flash
|
||||
ld a, %04
|
||||
out0 (SPI_CTL), a ; SPI
|
||||
in0 a, (RTC_CTRL) ; RTC,
|
||||
and a, %be
|
||||
out0 (RTC_CTRL), a
|
||||
|
||||
; Configure external memory/io
|
||||
|
||||
ld a, __CS0_LBR_INIT_PARAM
|
||||
out0 (CS0_LBR), a
|
||||
ld a, __CS0_UBR_INIT_PARAM
|
||||
out0 (CS0_UBR), a
|
||||
ld a, __CS0_BMC_INIT_PARAM
|
||||
out0 (CS0_BMC), a
|
||||
ld a, __CS0_CTL_INIT_PARAM
|
||||
out0 (CS0_CTL), a
|
||||
|
||||
ld a, __CS1_LBR_INIT_PARAM
|
||||
out0 (CS1_LBR), a
|
||||
ld a, __CS1_UBR_INIT_PARAM
|
||||
out0 (CS1_UBR), a
|
||||
ld a, __CS1_BMC_INIT_PARAM
|
||||
out0 (CS1_BMC), a
|
||||
ld a, __CS1_CTL_INIT_PARAM
|
||||
out0 (CS1_CTL), a
|
||||
|
||||
ld a, __CS2_LBR_INIT_PARAM
|
||||
out0 (CS2_LBR), a
|
||||
ld a, __CS2_UBR_INIT_PARAM
|
||||
out0 (CS2_UBR), a
|
||||
ld a, __CS2_BMC_INIT_PARAM
|
||||
out0 (CS2_BMC), a
|
||||
ld a, __CS2_CTL_INIT_PARAM
|
||||
out0 (CS2_CTL), a
|
||||
|
||||
ld a, __CS3_LBR_INIT_PARAM
|
||||
out0 (CS3_LBR), a
|
||||
ld a, __CS3_UBR_INIT_PARAM
|
||||
out0 (CS3_UBR), a
|
||||
ld a, __CS3_BMC_INIT_PARAM
|
||||
out0 (CS3_BMC), a
|
||||
ld a, __CS3_CTL_INIT_PARAM
|
||||
out0 (CS3_CTL), a
|
||||
|
||||
; Enable internal memory
|
||||
|
||||
ld a, __FLASH_ADDR_U_INIT_PARAM
|
||||
out0 (FLASH_ADDR_U), a
|
||||
ld a, __FLASH_CTL_INIT_PARAM
|
||||
out0 (FLASH_CTRL), a
|
||||
|
||||
ld a, __RAM_ADDR_U_INIT_PARAM
|
||||
out0 (RAM_ADDR_U), a
|
||||
ld a, __RAM_CTL_INIT_PARAM
|
||||
out0 (RAM_CTL), a
|
||||
ret
|
||||
|
||||
;*****************************************************************************
|
||||
; eZ80F91 System Clock Initialization
|
||||
;*****************************************************************************
|
||||
|
||||
_ez80_initsysclk:
|
||||
; check if the PLL should be used
|
||||
ld a, (_ez80_sysclksrc)
|
||||
cp a, PLL
|
||||
jr nz, _ez80_initsysclkdone
|
||||
|
||||
; Load PLL divider
|
||||
|
||||
ld a, (_ez80_oscfreqmult) ;CR 6202
|
||||
out0 (PLL_DIV_L), a
|
||||
ld a, (_ez80_oscfreqmult+1)
|
||||
out0 (PLL_DIV_H), a
|
||||
|
||||
; Set charge pump and lock criteria
|
||||
|
||||
ld a, __PLL_CTL0_INIT_PARAM
|
||||
and a, %CC ; mask off reserved and clock source bits
|
||||
out0 (PLL_CTL0), a
|
||||
|
||||
; Enable PLL
|
||||
|
||||
in0 a, (PLL_CTL1)
|
||||
set 0, a
|
||||
out0 (PLL_CTL1), a
|
||||
|
||||
; Wait for PLL to lock
|
||||
_ez80_initsysclkwait:
|
||||
in0 a, (PLL_CTL1)
|
||||
and a, LCK_STATUS
|
||||
cp a, LCK_STATUS
|
||||
jr nz, _ez80_initsysclkwait
|
||||
|
||||
; Select PLL as system clock source
|
||||
|
||||
ld a, __PLL_CTL0_INIT_PARAM
|
||||
set 0, a
|
||||
out0 (PLL_CTL0), a
|
||||
|
||||
_ez80_initsysclkdone:
|
||||
ret
|
||||
|
||||
;_ez80_oscfreq:
|
||||
; dl _OSC_FREQ
|
||||
_ez80_oscfreqmult:
|
||||
dw _OSC_FREQ_MULT
|
||||
;_ez80_sysclkfreq:
|
||||
; dl _SYS_CLK_FREQ
|
||||
_ez80_sysclksrc:
|
||||
db _SYS_CLK_SRC
|
||||
end
|
||||
|
|
@ -37,7 +37,7 @@ include ${TOPDIR}/.config
|
|||
|
||||
# These are the directories where the ZDS-II toolchain is installed
|
||||
|
||||
ZDSINSTALLDIR := C:/Program\ Files/ZiLOG/ZDSII_eZ8Acclaim!_4.11.0
|
||||
ZDSINSTALLDIR := C:/Program\ Files/ZiLOG/ZDSII_eZ80Acclaim!_4.11.0
|
||||
ZDSBINDIR := $(ZDSINSTALLDIR)/bin
|
||||
ZDSSTDINCDIR := $(ZDSINSTALLDIR)/include/std
|
||||
ZDSZILOGINCDIR := $(ZDSINSTALLDIR)/include/zilog
|
||||
|
|
|
|||
Loading…
Reference in New Issue