SAMV71: Add GPIO library support
This commit is contained in:
Gregory Nutt
parent
f6ba7bff56
commit
930f9738b0
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
HEAD_ASRC =
|
||||
|
||||
# Common ARM and Cortex-M3 files
|
||||
# Common ARM and Cortex-M7 files
|
||||
|
||||
CMN_UASRCS =
|
||||
CMN_UCSRCS =
|
||||
|
|
@ -88,13 +88,13 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
|
|||
CMN_CSRCS += up_checkstack.c
|
||||
endif
|
||||
|
||||
# Required SAM3/4 files
|
||||
# Required SAMV7 files
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = sam_start.c sam_clockconfig.c sam_irq.c sam_allocateheap.c
|
||||
CHIP_CSRCS += sam_lowputc.c sam_serial.c
|
||||
CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_gpio.c
|
||||
|
||||
# Configuration-dependent SAM3/4 files
|
||||
# Configuration-dependent SAMV7 files
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += sam_timerisr.c
|
||||
|
|
|
|||
|
|
@ -51,7 +51,17 @@
|
|||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************************/
|
||||
|
||||
#define GPIO_HAVE_PULLDOWN 1
|
||||
#define GPIO_HAVE_PERIPHCD 1
|
||||
#define GPIO_HAVE_SCHMITT 1
|
||||
#undef GPIO_HAVE_DELAYR
|
||||
#define GPIO_HAVE_DRIVER 1
|
||||
#define GPIO_HAVE_KEYPAD 1
|
||||
|
||||
/* Misc Helper Definitions **************************************************************/
|
||||
|
||||
#define PIOA (0)
|
||||
#define PIOB (1)
|
||||
#define PIOC (2)
|
||||
|
|
@ -508,7 +518,7 @@
|
|||
|
||||
#define PIO_KRCR_NBC_SHIFT (0) /* Bis 0-2: Number of Rows of the Keypad Matrix */
|
||||
#define PIO_KRCR_NBC_MASK (7 << PIO_KRCR_NBC_SHIFT)
|
||||
# define PIO_KRCR_NBC_MASK ((uint32_t)(n) << PIO_KRCR_NBC_SHIFT)
|
||||
# define PIO_KRCR_NBC(n) ((uint32_t)(n) << PIO_KRCR_NBC_SHIFT)
|
||||
#define PIO_KRCR_NBR_SHIFT (8) /* Bis 8-10: Number of Columns of the Keypad Matrix */
|
||||
#define PIO_KRCR_NBR_MASK (7 << PIO_KRCR_NBR_SHIFT)
|
||||
# define PIO_KRCR_NBR(n) ((uint32_t)(n) << PIO_KRCR_NBR_SHIFT)
|
||||
|
|
|
|||
|
|
@ -226,8 +226,8 @@
|
|||
/* Programmable Clock Output */
|
||||
|
||||
#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN6)
|
||||
#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
|
||||
#define GPIO_PCK0_2 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12)
|
||||
#define GPIO_PCK0_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN13)
|
||||
#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
|
||||
#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21)
|
||||
#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18)
|
||||
|
|
@ -308,7 +308,7 @@
|
|||
#define GPIO_PWMC1_L2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN4)
|
||||
#define GPIO_PWMC1_L2_2 (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
|
||||
#define GPIO_PWMC1_L3_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN5)
|
||||
#define GPIO_PWMC1_L3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)
|
||||
#define GPIO_PWMC1_L3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)
|
||||
|
||||
/* Quad IO SPI (QSPI) */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,575 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/samv7/sam_gpio.c
|
||||
* General Purpose Input/Output (GPIO) logic for the SAMV71
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "sam_gpio.h"
|
||||
#include "chip/sam_pio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
static const char g_portchar[SAMV7_NPIO] =
|
||||
{
|
||||
'A'
|
||||
#if SAMV7_NPIO > 1
|
||||
, 'B'
|
||||
#endif
|
||||
#if SAMV7_NPIO > 2
|
||||
, 'C'
|
||||
#endif
|
||||
#if SAMV7_NPIO > 3
|
||||
, 'D'
|
||||
#endif
|
||||
#if SAMV7_NPIO > 4
|
||||
, 'E'
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
const uintptr_t g_portchar[SAMV7_NPIO] =
|
||||
{
|
||||
SAM_PIOA_BASE
|
||||
#if SAMV7_NPIO > 1
|
||||
, SAM_PIOB_BASE
|
||||
#endif
|
||||
#if SAMV7_NPIO > 2
|
||||
, SAM_PIOC_BASE
|
||||
#endif
|
||||
#if SAMV7_NPIO > 3
|
||||
, SAM_PIOD_BASE
|
||||
#endif
|
||||
#if SAMV7_NPIO > 4
|
||||
, SAM_PIOE_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
/****************************************************************************
|
||||
* Name: sam_configinput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO input pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_configinput(uintptr_t base, uint32_t pin,
|
||||
gpio_pinset_t cfgset)
|
||||
{
|
||||
#ifdef GPIO_HAVE_SCHMITT
|
||||
uint32_t regval;
|
||||
#endif
|
||||
|
||||
/* Disable interrupts on the pin */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
|
||||
|
||||
/* Enable/disable the pull-up as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLUP) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef GPIO_HAVE_PULLDOWN
|
||||
/* Enable/disable the pull-down as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check if filtering should be enabled */
|
||||
|
||||
if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_IFER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef GPIO_HAVE_SCHMITT
|
||||
/* Enable/disable the Schmitt trigger */
|
||||
|
||||
regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
|
||||
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
|
||||
{
|
||||
regval |= pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~pin;
|
||||
}
|
||||
|
||||
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_HAVE_DRIVER
|
||||
/* Reset output drive strength (PIO outputs only) */
|
||||
|
||||
regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Configure the pin as an input and enable the GPIO function */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
|
||||
putreg32(pin, base + SAM_PIO_PER_OFFSET);
|
||||
|
||||
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
|
||||
* IFDGSR registers. This would probably best be done with
|
||||
* another, new API... perhaps sam_configfilter()
|
||||
*/
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_configoutput
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO output pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_configoutput(uintptr_t base, uint32_t pin,
|
||||
gpio_pinset_t cfgset)
|
||||
{
|
||||
#ifdef GPIO_HAVE_DRIVER
|
||||
uint32_t regval;
|
||||
#endif
|
||||
|
||||
/* Disable interrupts on the pin */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
|
||||
|
||||
/* Enable/disable the pull-up as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLUP) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef GPIO_HAVE_PULLDOWN
|
||||
/* Enable/disable the pull-down as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable the open drain driver if requrested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_MDER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
|
||||
}
|
||||
|
||||
/* Set default value */
|
||||
|
||||
if ((cfgset & GPIO_OUTPUT_SET) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef GPIO_HAVE_DRIVER
|
||||
/* Select the pin output drive strength */
|
||||
|
||||
regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
|
||||
if ((cfgset & GPIO_OUTPUT_DRIVE) != GPIO_OUTPUT_LOW_DRIVE)
|
||||
{
|
||||
regval |= pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~pin;
|
||||
}
|
||||
|
||||
putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Configure the pin as an output and enable the GPIO function */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_OER_OFFSET);
|
||||
putreg32(pin, base + SAM_PIO_PER_OFFSET);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_configperiph
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin driven by a peripheral A or B signal based on
|
||||
* bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_configperiph(uintptr_t base, uint32_t pin,
|
||||
gpio_pinset_t cfgset)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Disable interrupts on the pin */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
|
||||
|
||||
/* Enable/disable the pull-up as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLUP) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
|
||||
}
|
||||
|
||||
#ifdef GPIO_HAVE_PULLDOWN
|
||||
/* Enable/disable the pull-down as requested */
|
||||
|
||||
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_HAVE_DRIVER
|
||||
/* Reset output drive strength (PIO outputs only) */
|
||||
|
||||
regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_HAVE_PERIPHCD
|
||||
/* Configure pin, depending upon the peripheral A, B, C or D
|
||||
*
|
||||
* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
|
||||
* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
|
||||
* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
|
||||
* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
|
||||
*/
|
||||
|
||||
regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
|
||||
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
|
||||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
|
||||
{
|
||||
regval &= ~pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= pin;
|
||||
}
|
||||
putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
|
||||
|
||||
regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
|
||||
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
|
||||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
|
||||
{
|
||||
regval &= ~pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= pin;
|
||||
}
|
||||
putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
|
||||
|
||||
#else
|
||||
/* Configure pin, depending upon the peripheral A or B:
|
||||
*
|
||||
* PERIPHA: ABSR[n] = 0
|
||||
* PERIPHB: ABSR[n] = 1
|
||||
*/
|
||||
|
||||
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
|
||||
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
|
||||
{
|
||||
regval &= ~pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= pin;
|
||||
}
|
||||
|
||||
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Disable PIO functionality */
|
||||
|
||||
putreg32(pin, base + SAM_PIO_PDR_OFFSET);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_configgpio(gpio_pinset_t cfgset)
|
||||
{
|
||||
uintptr_t base = sam_gpio_base(cfgset);
|
||||
uint32_t pin = sam_gpio_pinmask(cfgset);
|
||||
irqstate_t flags;
|
||||
int ret;
|
||||
|
||||
/* Disable interrupts to prohibit re-entrance. */
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Enable writing to GPIO registers */
|
||||
|
||||
putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
|
||||
|
||||
/* Handle the pin configuration according to pin type */
|
||||
|
||||
switch (cfgset & GPIO_MODE_MASK)
|
||||
{
|
||||
case GPIO_ALTERNATE:
|
||||
case GPIO_INPUT:
|
||||
ret = sam_configinput(base, pin, cfgset);
|
||||
break;
|
||||
|
||||
case GPIO_OUTPUT:
|
||||
ret = sam_configoutput(base, pin, cfgset);
|
||||
break;
|
||||
|
||||
case GPIO_PERIPHA:
|
||||
case GPIO_PERIPHB:
|
||||
#ifdef GPIO_HAVE_PERIPHCD
|
||||
case GPIO_PERIPHC:
|
||||
case GPIO_PERIPHD:
|
||||
#endif
|
||||
ret = sam_configperiph(base, pin, cfgset);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable writing to GPIO registers */
|
||||
|
||||
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
|
||||
irqrestore(flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_gpiowrite(gpio_pinset_t pinset, bool value)
|
||||
{
|
||||
uintptr_t base = sam_gpio_base(pinset);
|
||||
uint32_t pin = sam_gpio_pinmask(pinset);
|
||||
|
||||
if (value)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool sam_gpioread(gpio_pinset_t pinset)
|
||||
{
|
||||
uintptr_t base = sam_gpio_base(pinset);
|
||||
uint32_t pin = sam_gpio_pinmask(pinset);
|
||||
uint32_t regval;
|
||||
|
||||
if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
|
||||
}
|
||||
|
||||
return (regval & pin) != 0;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Function: sam_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the base address of the provided pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
int sam_dumpgpio(uint32_t pinset, const char *msg)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uintptr_t base;
|
||||
unsigned int port;
|
||||
|
||||
/* Get the base address associated with the PIO port */
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
base = SAM_PION_BASE(port);
|
||||
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = irqsave();
|
||||
lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
|
||||
g_portchar[port], pinset, base, msg);
|
||||
lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
|
||||
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
|
||||
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
|
||||
#endif
|
||||
lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
|
||||
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
|
||||
lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
|
||||
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4E
|
||||
lldbg("SCHMITT: %08x DELAYR:%08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
|
||||
#else
|
||||
lldbg("SCHMITT: %08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
|
||||
#endif
|
||||
#endif
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -49,15 +49,6 @@
|
|||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#define GPIO_HAVE_PULLDOWN 1
|
||||
#define GPIO_HAVE_PERIPHCD 1
|
||||
#define GPIO_HAVE_SCHMITT 1
|
||||
#undef GPIO_HAVE_DELAYR 1
|
||||
#define GPIO_HAVE_DRIVER 1
|
||||
#define GPIO_HAVE_KEYPAD 1
|
||||
|
||||
/* Bit-encoded input to sam_configgpio() ********************************************/
|
||||
|
||||
/* 32-bit Encoding:
|
||||
|
|
@ -67,7 +58,7 @@
|
|||
|
||||
/* Input/Output mode:
|
||||
*
|
||||
* .... .... MMM. .... .... .... .... ....
|
||||
* .... .... MMM. .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (21) /* Bits 21-23: GPIO mode */
|
||||
|
|
@ -127,8 +118,9 @@
|
|||
* .... .... .... .... .... D... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 11) /* Bit 11: Initial value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
#define GPIO_OUTPUT_DRIVE (1 << 11) /* Bit 11: Initial value of output */
|
||||
# define GPIO_OUTPUT_HIGH_DRIVE (1 << 11)
|
||||
#define GPIO_OUTPUT_LOW_DRIVE (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
|
|
@ -187,24 +179,12 @@
|
|||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Must be big enough to hold the 32-bit encoding */
|
||||
|
||||
typedef uint32_t gpio_pinset_t;
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_DEBUG_GPIO
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
|
@ -218,6 +198,66 @@ extern "C"
|
|||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
EXTERN const uintptr_t g_portchar[SAMV7_NPIO];
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpio_base
|
||||
*
|
||||
* Description:
|
||||
* Return the base address of the GPIO register set
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uintptr_t sam_gpio_base(gpio_pinset_t cfgset)
|
||||
{
|
||||
int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
DEBUGASSERT(port <SAMV7_NPIO);
|
||||
return g_portchar[port];
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpio_port
|
||||
*
|
||||
* Description:
|
||||
* Return the PIO port number
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_gpio_port(gpio_pinset_t cfgset)
|
||||
{
|
||||
return (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpio_pin
|
||||
*
|
||||
* Description:
|
||||
* Return the PIO pin number
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_gpio_pin(gpio_pinset_t cfgset)
|
||||
{
|
||||
return (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_gpio_pinmask
|
||||
*
|
||||
* Description:
|
||||
* Return the PIO pin bit maskt
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_gpio_pinmask(gpio_pinset_t cfgset)
|
||||
{
|
||||
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
|
|
|||
|
|
@ -871,8 +871,8 @@ static int sam_setup(struct uart_dev_s *dev)
|
|||
*/
|
||||
|
||||
divb3 = ((FAST_USART_CLOCK + (priv->baud << 3)) << 3) / (priv->baud << 4);
|
||||
intpart = (divb3 >> 3);
|
||||
fracpart = (divb3 & 7)
|
||||
intpart = divb3 >> 3;
|
||||
fracpart = divb3 & 7;
|
||||
|
||||
/* Retain the fast MR peripheral clock UNLESS unless using that clock
|
||||
* would result in an excessively large divider.
|
||||
|
|
@ -885,8 +885,8 @@ static int sam_setup(struct uart_dev_s *dev)
|
|||
/* Use the divided USART clock */
|
||||
|
||||
divb3 = ((FAST_USART_CLOCK + (priv->baud << 3)) << 3) / (priv->baud << 4);
|
||||
intpart = (divb3 >> 3);
|
||||
fracpart = (divb3 & 7)
|
||||
intpart = divb3 >> 3;
|
||||
fracpart = divb3 & 7;
|
||||
|
||||
/* Re-select the clock source */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue