Fix workaround logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1124 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -528,5 +528,7 @@
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0.3.18 2008-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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* Added port for the STMicro STR71x processor and configuration for the Olimex STR-P711
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board (untested as of the initial checkin).
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* Fix race condition workaround delay in LPC214X SPI logic. It the cause of the very
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bad MMC/SD performance.
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@ -8,7 +8,7 @@
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<tr align="center" bgcolor="#e4e4e4">
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<td>
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<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
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<p>Last Updated: November 1, 2008</p>
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<p>Last Updated: November 2, 2008</p>
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</td>
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</tr>
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</table>
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@ -1114,6 +1114,8 @@ buildroot-0.1.0 2007-03-09 <spudmonkey@racsa.co.cr>
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nuttx-0.3.18 2008-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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* Added port for the STMicro STR71x processor and configuration for the Olimex STR-P711
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board (untested as of the initial checkin).
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* Fix race condition workaround delay in LPC214X SPI logic. It the cause of the very
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bad MMC/SD performance.
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pascal-0.1.3 2008-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -154,11 +154,16 @@ static void spi_select(FAR struct spi_dev_s *dev, boolean selected)
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while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF));
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putreg16(0xff, LPC214X_SPI1_DR);
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/* Then wait until TX FIFO and TX shift buffer are empty */
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/* Wait until TX FIFO and TX shift buffer are empty */
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while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY);
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/* Wait until RX FIFO is not empty */
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while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE));
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/* Then read and discard bytes until the RX FIFO is empty */
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do
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{
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(void)getreg16(LPC214X_SPI1_DR);
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@ -290,7 +295,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const ubyte *buffer, siz
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}
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}
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/* Then discard all card responses until the TX FIFO is emptied. */
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/* Then discard all card responses until the RX & TX FIFOs are emptied. */
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do
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{
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@ -304,12 +309,13 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const ubyte *buffer, siz
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(void)getreg16(LPC214X_SPI1_DR);
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}
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/* There is a race condition where TFE may go FALSE just before
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* RNE goes true. The nasty little delay in the following solves
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* that (it could probably be tuned to improve performance).
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/* There is a race condition where TFE may go TRUE just before
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* RNE goes true and this loop terminates prematurely. The nasty little
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* delay in the following solves that (it could probably be tuned
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* to improve performance).
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*/
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else if ((sr & LPC214X_SPI1SR_TFE) == 0)
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else if ((sr & LPC214X_SPI1SR_TFE) != 0)
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{
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up_udelay(100);
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sr = getreg8(LPC214X_SPI1_SR);
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