Add SPI header file
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2693 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_spi.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */
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#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */
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#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */
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#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
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#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
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#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
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#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
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/* Register addresses ***************************************************************/
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#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET)
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#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET)
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#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET)
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#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET)
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#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET)
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#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET)
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#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Control Register */
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/* Bits 0-1: Reserved */
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#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
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#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
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#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
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#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
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#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
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#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
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#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
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#define SPI_CR_BITS_MASK (15 << BITSSPI_CR_BITS_SHIFT)
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# define SPI_CR_BITS_8BITS (8 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_9BITS (9 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_10BITS (10 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_11BITS (11 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_12BITS (12 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_13BITS (13 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_14BITS (14 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_15BITS (15 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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# define SPI_CR_BITS_16BITS (0 << BITSSPI_CR_BITS_SHIFT) /* xx bits per transfer */
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/* Bits 12-31: Reserved */
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/* SPI Status Register */
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/* Bits 0-2: Reserved */
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#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
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#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
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#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
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#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
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#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
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/* Bits 8-31: Reserved */
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/* SPI Data Register */
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#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
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#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
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/* Bits 8-31: Reserved */
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/* SPI Clock Counter Register */
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#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
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/* Bits 8-31: Reserved */
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/* SPI Test Control Register */
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/* Bit 0: Reserved */
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#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
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#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
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/* Bits 8-31: Reserved */
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/* SPI Test Status Register */
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/* Bits 0-2: Reserved */
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#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
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#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
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#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
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#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
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#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
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/* Bits 8-31: Reserved */
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/* SPI Interrupt Register */
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#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
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/* Bits 1-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */
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