DM90x0 driver hooked into DM320
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@367 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
f42ab1377f
commit
86df4dbac9
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@ -48,7 +48,7 @@ BOARD_DIR = configs/$(CONFIG_ARCH_BOARD)
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# (except for parts of FSDIRS). We will exclude FSDIRS
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# from the build if file descriptor support is disabled
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NONFSDIRS = sched lib $(ARCH_SRC) mm examples/$(CONFIG_EXAMPLE) $(BOARD_DIR)/src
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NONFSDIRS = sched lib $(ARCH_SRC) mm examples/$(CONFIG_EXAMPLE)
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FSDIRS = fs drivers
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ifeq ($(CONFIG_NET),y)
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@ -54,6 +54,7 @@ o Build system
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- Some names under arch are still incorrect. These should be processor architecture
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names: pjrc-8051 should be 805x
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- configs/pjrc-8051 should be configs/pjrc-87c52
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- Dependencies do not work correctly under configs/<board>/src (same as arch/<arch>/src/board).
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o Applications & Tests
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@ -0,0 +1,112 @@
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/************************************************************************************
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* dm320/dm320_emif.h
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __DM320_DM320_EMIF_H
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#define __DM320_DM320_EMIF_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#ifndef __ASSEMBLY__
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# include <sys/types.h>
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#endif
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* External Memory Interface (EMIF) Registers */
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#define DM320_EMIF_CS0CTRL1 (DM320_PERIPHERALS_VADDR + 0x0A00) /* CS0 Control Register #1 */
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#define DM320_EMIF_CS0CTRL2 (DM320_PERIPHERALS_VADDR + 0x0A02) /* CS0 Control Register #2 */
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#define DM320_EMIF_CS0CTRL3 (DM320_PERIPHERALS_VADDR + 0x0A04) /* CS0 Control Register #3 */
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#define DM320_EMIF_CS1CTRL1A (DM320_PERIPHERALS_VADDR + 0x0A06) /* CS1 Control Register #1A */
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#define DM320_EMIF_CS1CTRL1B (DM320_PERIPHERALS_VADDR + 0x0A08) /* CS1 Control Register #1B */
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#define DM320_EMIF_CS2CTRL2 (DM320_PERIPHERALS_VADDR + 0x0A0A) /* CS1 Control Register #2 */
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#define DM320_EMIF_CS2CTRL1 (DM320_PERIPHERALS_VADDR + 0x0A0C) /* CS2 Control Register #1 */
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#define DM320_EMIF_CS1CTRL2 (DM320_PERIPHERALS_VADDR + 0x0A0E) /* CS2 Control Register #2 */
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#define DM320_EMIF_CS3CTRL1 (DM320_PERIPHERALS_VADDR + 0x0A10) /* CS3 Control Register #1 */
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#define DM320_EMIF_CS3CTRL2 (DM320_PERIPHERALS_VADDR + 0x0A12) /* CS3 Control Register #2 */
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#define DM320_EMIF_CS4CTRL1 (DM320_PERIPHERALS_VADDR + 0x0A14) /* CS4 Control Register #1 */
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#define DM320_EMIF_CS4CTRL2 (DM320_PERIPHERALS_VADDR + 0x0A16) /* CS4 Control Register #2 */
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#define DM320_EMIF_BUSCTRL (DM320_PERIPHERALS_VADDR + 0x0A18) /* Bus Control Register */
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#define DM320_EMIF_BUSRLS (DM320_PERIPHERALS_VADDR + 0x0A1A) /* Bus Release Control Register */
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#define DM320_EMIF_CFCTRL1 (DM320_PERIPHERALS_VADDR + 0x0A1C) /* CFC ControlRegister #1 */
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#define DM320_EMIF_CFCTRL2 (DM320_PERIPHERALS_VADDR + 0x0A1E) /* CFC ControlRegister#2 */
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#define DM320_EMIF_SMCTRL (DM320_PERIPHERALS_VADDR + 0x0A20) /* SmartMedia Control Register */
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#define DM320_EMIF_BUSINTEN (DM320_PERIPHERALS_VADDR + 0x0A22) /* Bus Interrupt Enable Register */
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#define DM320_EMIF_BUSSTS (DM320_PERIPHERALS_VADDR + 0x0A24) /* Bus Status Register */
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#define DM320_EMIF_BUSWAITMD (DM320_PERIPHERALS_VADDR + 0x0A26) /* Bus Wait Mode Register */
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#define DM320_EMIF_ECC1CP (DM320_PERIPHERALS_VADDR + 0x0A28) /* ECC Area 1 CP Register */
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#define DM320_EMIF_ECC1LP (DM320_PERIPHERALS_VADDR + 0x0A2A) /* ECC Area 1 LP Register */
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#define DM320_EMIF_ECC2CP (DM320_PERIPHERALS_VADDR + 0x0A2C) /* ECC Area 2 CP Register */
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#define DM320_EMIF_ECC2LP (DM320_PERIPHERALS_VADDR + 0x0A2E) /* ECC Area 2 LP Register */
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#define DM320_EMIF_ECC3CP (DM320_PERIPHERALS_VADDR + 0x0A30) /* ECC Area 3 CP Register */
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#define DM320_EMIF_ECC3LP (DM320_PERIPHERALS_VADDR + 0x0A32) /* ECC Area 3 LP Register */
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#define DM320_EMIF_ECC4CP (DM320_PERIPHERALS_VADDR + 0x0A34) /* ECC Area 4 CP Register */
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#define DM320_EMIF_ECC4LP (DM320_PERIPHERALS_VADDR + 0x0A36) /* ECC Area 4 LP Register */
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#define DM320_EMIF_ECC5CP (DM320_PERIPHERALS_VADDR + 0x0A38) /* ECC Area 5 CP Register */
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#define DM320_EMIF_ECC5LP (DM320_PERIPHERALS_VADDR + 0x0A3A) /* ECC Area 5 LP Register */
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#define DM320_EMIF_ECC6CP (DM320_PERIPHERALS_VADDR + 0x0A3C) /* ECC Area 6 CP Register */
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#define DM320_EMIF_ECC6LP (DM320_PERIPHERALS_VADDR + 0x0A3E) /* ECC Area 6 LP Register */
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#define DM320_EMIF_ECC7CP (DM320_PERIPHERALS_VADDR + 0x0A40) /* ECC Area 7 CP Register */
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#define DM320_EMIF_ECC7LP (DM320_PERIPHERALS_VADDR + 0x0A42) /* ECC Area 7 LP Register */
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#define DM320_EMIF_ECC8CP (DM320_PERIPHERALS_VADDR + 0x0A44) /* ECC Area 8 CP Register */
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#define DM320_EMIF_ECC8LP (DM320_PERIPHERALS_VADDR + 0x0A46) /* ECC Area 8 LP Register */
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#define DM320_EMIF_ECCCLR (DM320_PERIPHERALS_VADDR + 0x0A48) /* ECC Clear Register */
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#define DM320_EMIF_PAGESZ (DM320_PERIPHERALS_VADDR + 0x0A4A) /* SmartMedia Page Size Register */
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#define DM320_EMIF_PRIORCTL (DM320_PERIPHERALS_VADDR + 0x0A4C) /* Priority control for DMA */
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#define DM320_EMIF_IMGDSPDEST (DM320_PERIPHERALS_VADDR + 0x0A4E) /* DSP/IMGBUF DMA destination */
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#define DM320_EMIF_IMGDSPADDH (DM320_PERIPHERALS_VADDR + 0x0A50) /* DSP/IMGBUF high address */
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#define DM320_EMIF_IMGDSPADDL (DM320_PERIPHERALS_VADDR + 0x0A52) /* DSP/IMGBUG low address */
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#define DM320_EMIF_AHBADDH (DM320_PERIPHERALS_VADDR + 0x0A54) /* AHB high address */
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#define DM320_EMIF_AHBADDL (DM320_PERIPHERALS_VADDR + 0x0A56) /* AHB low address */
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#define DM320_EMIF_MTCADDH (DM320_PERIPHERALS_VADDR + 0x0A58) /* MTC high address */
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#define DM320_EMIF_MTCADDL (DM320_PERIPHERALS_VADDR + 0x0A5A) /* MTC low address */
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#define DM320_EMIF_DMASIZE (DM320_PERIPHERALS_VADDR + 0x0A5C) /* DMA Transfer Size Register */
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#define DM320_EMIF_DMAMTCSEL (DM320_PERIPHERALS_VADDR + 0x0A5E) /* DMA Device Select Register */
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#define DM320_EMIF_DMACTL (DM320_PERIPHERALS_VADDR + 0x0A60) /* DMA Control Register */
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#define DM320_EMIF_TEST (DM320_PERIPHERALS_VADDR + 0x0A62) /* Test Register.Do not use */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#endif
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#endif /* __DM320_DM320_EMIF_H */
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@ -298,7 +298,7 @@ CONFIG_NET_RESOLV_ENTRIES=4
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CONFIG_NET_DM90x0=n
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CONFIG_DM9X_NINTERFACES=1
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CONFIG_DM9X_STATS=1
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CONFIG_DM9X_BASE=0x60000300
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CONFIG_DM9X_BASE=0xd0000300
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CONFIG_DM9X_IRQ=27
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CONFIG_DM9X_BUSWIDTH8=n
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CONFIG_DM9X_BUSWIDTH16=y
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@ -41,12 +41,14 @@
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#if defined(CONFIG_NET) && defined(CONFIG_NET_DM90x0)
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#include <sys/types.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "dm320_memorymap.h"
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#include "dm320_emif.h"
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#include "dm320_gio.h"
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extern void dm9x_initialize(void);
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@ -78,6 +80,9 @@ void up_netinitialize(void)
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* width is 16-bits.
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*/
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lldbg("CS4CTRL1=%04x CS4CTRL2=%04x\n",
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getreg16(DM320_EMIF_CS4CTRL1), getreg16(DM320_EMIF_CS4CTRL2));
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/* It is assumed that bootloader has already configured CS4. Here,
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* we will only make certain that the GIO is properly configured
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*/
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@ -87,6 +92,10 @@ void up_netinitialize(void)
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GIO_INTERRUPT(GIO_DM9000A_INT);
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GIO_RISINGEDGE(GIO_DM9000A_INT);
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lldbg("GIO DIR0=%04x INV0=%04x IRQPORT=%04x IRQEDGE=%04x\n",
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getreg16(DM320_GIO_DIR0), getreg16(DM320_GIO_INV0),
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getreg16(DM320_GIO_IRQPORT), getreg16(DM320_GIO_IRQEDGE));
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/* Then initialize the driver */
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dm9x_initialize();
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@ -267,7 +267,7 @@
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# define CONFIG_DM9X_MODE DM9X_MODE_AUTO
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#endif
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// /* TX poll deley = 5 seconds. CLK_TCK is the number of clock ticks per second */
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/* TX poll deley = 5 seconds. CLK_TCK is the number of clock ticks per second */
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#define DM6X_WDDELAY (5*CLK_TCK)
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@ -434,8 +434,8 @@ static uint8 getreg(int reg)
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static void putreg(int reg, uint8 value)
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{
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DM9X_INDEX = reg;
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DM9X_DATA = value & 0xff;
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DM9X_INDEX = reg;
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DM9X_DATA = value & 0xff;
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}
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/****************************************************************************
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@ -677,8 +677,6 @@ static void dm9x_resetstatistics(struct dm9x_driver_s *dm9x)
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dm9x->nresets = 0; /* Counts number of resets */
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dm9x->ntxtimeouts = 0; /* Counts resets caused by TX timeouts */
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}
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#else
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# define dm9x_resetstatistics(dev)
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#endif
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/****************************************************************************
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@ -1647,7 +1645,7 @@ int dm9x_initialize(void)
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vid = (((uint16)getreg(DM9X_VIDH)) << 8) | (uint16)getreg(DM9X_VIDL);
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pid = (((uint16)getreg(DM9X_PIDH)) << 8) | (uint16)getreg(DM9X_PIDL);
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dbg("I/O base: %08x VID: %04x PID: %04x\n", CONFIG_DM9X_BASE, vid, pid);
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lldbg("I/O base: %08x VID: %04x PID: %04x\n", CONFIG_DM9X_BASE, vid, pid);
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/* Check if a DM90x0 chip is recognized at this I/O base */
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@ -1662,20 +1660,21 @@ int dm9x_initialize(void)
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if (irq_attach(CONFIG_DM9X_IRQ, dm9x_interrupt))
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{
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/* We could not attach the ISR to the ISR */
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dbg("irq_attach() failed\n");
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lldbg("irq_attach() failed\n");
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return -EAGAIN;
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}
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/* Initialize the driver structure */
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memset(g_dm9x, 0, CONFIG_DM9X_NINTERFACES*sizeof(struct dm9x_driver_s));
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g_dm9x[0].dev.ifup = dm9x_ifup;
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g_dm9x[0].dev.ifdown = dm9x_ifdown;
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g_dm9x[0].dev.ifup = dm9x_ifup; /* I/F down callback */
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g_dm9x[0].dev.ifdown = dm9x_ifdown; /* I/F up (new IP address) callback */
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g_dm9x[0].dev.d_private = (void*)g_dm9x; /* Used to recover private state from dev */
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/* Create a watchdog for timing polling for and timing of transmisstions */
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g_dm9x[0].txpoll = wd_create();
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g_dm9x[0].txtimeout = wd_create();
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g_dm9x[0].txpoll = wd_create(); /* Create periodic poll timer */
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g_dm9x[0].txtimeout = wd_create(); /* Create TX timeout timer */
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/* Read the MAC address */
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@ -1685,10 +1684,13 @@ int dm9x_initialize(void)
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mptr[i] = getreg(j);
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}
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dbg("MAC: %0x:%0x:%0x:%0x:%0x:%0x",
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mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
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lldbg("MAC: %0x:%0x:%0x:%0x:%0x:%0x",
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mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
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return 0;
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/* Register the device with the OS so that socket IOCTLs can be performed */
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(void)netdev_register(&g_dm9x[0].dev);
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return OK;
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}
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#endif /* CONFIG_NET && CONFIG_NET_DM90x0 */
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#include "nettest.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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void uip_log(char *m)
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{
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printf("uIP log message: %s\n", m);
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/* Since uip_log is called from interrupt handling logic, it cannot use
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* or other standard I/O. This should work from an interrupt handler:
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*/
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lib_rawprintf("uIP log message: %s\n", m);
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}
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# error "No network application specified"
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#endif
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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void uip_log(char *m)
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{
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printf("uIP log message: %s\n", m);
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/* Since uip_log is called from interrupt handling logic, it cannot use
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* or other standard I/O. This should work from an interrupt handler:
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*/
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lib_rawprintf("uIP log message: %s\n", m);
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}
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#if defined(CONFIG_EXAMPLE_UIP_WEBCLIENT)
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