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Back out the last STM32 DMA priority change. It is not necessary; just dropping the SD frequency was sufficient 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5021 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2012-08-10 23:16:01 +00:00
parent 1d75c0d705
commit 84b540ddad
3 changed files with 7 additions and 4 deletions
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3
nuttx/ChangeLog
View File

@ -3151,3 +3151,6 @@
frequency from 24 to 16 MHz. Apparently 24 MHz is too fast for the board. frequency from 24 to 16 MHz. Apparently 24 MHz is too fast for the board.
This (plus the change to the STM32 DMA (above) fixes SDIO DMA on the This (plus the change to the STM32 DMA (above) fixes SDIO DMA on the
STM3240G-EVAL (and probably STM3220G-EVAL -- untested). STM3240G-EVAL (and probably STM3220G-EVAL -- untested).
* arch/arm/src/stm32/stm32f2xx_dma.c and stm32f4xx_dma.c: Backed out the
DMA priority change just above. The reduced SD card frequency was
necessary and sufficient to resolve the problem.

4
nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c
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@ -721,11 +721,11 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC| regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS| DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|DMA_SCR_PL_MASK| DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC| scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS| DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_DBM|DMA_SCR_CIRC|DMA_SCR_PL_MASK| DMA_SCR_DBM|DMA_SCR_CIRC|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
regval |= scr; regval |= scr;
dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0; dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;

4
nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
View File

@ -721,11 +721,11 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC| regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS| DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|DMA_SCR_PL_MASK| DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC| scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS| DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_DBM|DMA_SCR_CIRC|DMA_SCR_PL_MASK| DMA_SCR_DBM|DMA_SCR_CIRC|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
regval |= scr; regval |= scr;
dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0; dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;