PIC32MZ: Add memorymap and devcfg header files
This commit is contained in:
Gregory Nutt
parent
b34469d6c9
commit
7de6c3660e
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@ -47,7 +47,7 @@
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#include <nuttx/config.h>
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#include <arch/pic32mz/chip.h>
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#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
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#if defined(CHIP_PIC32MZEC)
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# include <arch/pic32mz/irq_pic32mzxxxec.h>
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#else
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# error "Unknown PIC32MZ family
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@ -0,0 +1,51 @@
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/************************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mz-features.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
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#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
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# include <chip/pic32mzec-features.h>
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#else
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# error "Unknown PIC32MZ family
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#endif
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#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H */
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@ -0,0 +1,51 @@
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/************************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
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#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#if defined(CHIP_PIC32MZEC) || defined(CHIP_PIC32MZ2)
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# include <chip/pic32mzec-memorymap.h>
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#else
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# error "Unknown PIC32MZ family
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#endif
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#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H */
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@ -0,0 +1,255 @@
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/************************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mzec-features.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
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#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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mips32-memorymap.h:#define KSEG1_BASE
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#define PIC32MZ_LOWERBOOT_K1BASE (0xbfc00000)
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#define PIC32MZ_BOOTCFG_K1BASE (0xbfc0ff40)
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#define PIC32MZ_UPPERBOOT_K1BASE (0xbfc20000)
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#define PIC32MZ_BOOT1_K1BASE (0xbfc40000)
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#define PIC32MZ_SEQCFG1_K1BASE (0xbfc4ff40)
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#define PIC32MZ_ADCCALIB_K1BASE (0xbfc54000)
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#define PIC32MZ_DEVSN_K1BASE (0xbfc54020)
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#define PIC32MZ_BOOT2_K1BASE (0xbfc60000)
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#define PIC32MZ_SEQCFG2_K1BASE (0xbfc6ff40)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register/Flash Offsets ***********************************************************/
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/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
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#define PIC32MZ_CFGCON_OFFSET 0x0000 /* Configuration control register */
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#define PIC32MZ_DEVID_OFFSET 0x0020 /* Device ID and revision register */
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#define PIC32MZ_SYSKEY_OFFSET 0x0030 /* System key register */
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#define PIC32MZ_CFGEBIA_OFFSET 0x00c0 /* External bus interface address pin configuration register */
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#define PIC32MZ_CFGEBIC_OFFSET 0x00d0 /* External bus interface address pin control register */
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#define PIC32MZ_CFGPG_OFFSET 0x00e0 /* Permission group configuration register */
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/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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#define PIC32MZ_ADEVCFG3_OFFSET 0x0000 /* Alternate device configuration word 3 */
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#define PIC32MZ_ADEVCFG2_OFFSET 0x0004 /* Alternate device configuration word 2 */
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#define PIC32MZ_ADEVCFG1_OFFSET 0x0008 /* Alternate device configuration word 1 */
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#define PIC32MZ_ADEVCFG0_OFFSET 0x000c /* Alternate device configuration word 0 */
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#define PIC32MZ_ADEVCP3_OFFSET 0x0010 /* Alternate device code protect word 3 */
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#define PIC32MZ_ADEVCP2_OFFSET 0x0014 /* Alternate device code protect word 2 */
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#define PIC32MZ_ADEVCP1_OFFSET 0x0018 /* Alternate device code protect word 1 */
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#define PIC32MZ_ADEVCP0_OFFSET 0x001c /* Alternate device code protect word 0 */
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#define PIC32MZ_ADEVSIGN3_OFFSET 0x0020 /* Alternate evice signature word 3 */
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#define PIC32MZ_ADEVSIGN2_OFFSET 0x0024 /* Alternate evice signature word 2 */
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#define PIC32MZ_ADEVSIGN1_OFFSET 0x0028 /* Alternate evice signature word 1 */
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#define PIC32MZ_ADEVSIGN0_OFFSET 0x002c /* Alternate evice signature word 0 */
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/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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#define PIC32MZ_DEVCFG3_OFFSET 0x0080 /* Device configuration word 3 */
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#define PIC32MZ_DEVCFG2_OFFSET 0x0084 /* Device configuration word 2 */
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#define PIC32MZ_DEVCFG1_OFFSET 0x0088 /* Device configuration word 1 */
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#define PIC32MZ_DEVCFG0_OFFSET 0x008c /* Device configuration word 0 */
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#define PIC32MZ_DEVCP3_OFFSET 0x0090 /* Device code protect word 3 */
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#define PIC32MZ_DEVCP2_OFFSET 0x0094 /* Device code protect word 2 */
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#define PIC32MZ_DEVCP1_OFFSET 0x0098 /* Device code protect word 1 */
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#define PIC32MZ_DEVCP0_OFFSET 0x009c /* Device code protect word 0 */
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#define PIC32MZ_DEVSIGN3_OFFSET 0x00a0 /* Device signature word 3 */
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#define PIC32MZ_DEVSIGN2_OFFSET 0x00a4 /* Device signature word 2 */
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#define PIC32MZ_DEVSIGN1_OFFSET 0x00a8 /* Device signature word 1 */
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#define PIC32MZ_DEVSIGN0_OFFSET 0x00ac /* Device signature word 0 */
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/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
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#define PIC32MZ_DEVADC1_OFFSET 0x0000 /* ADC1 Calibration */
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#define PIC32MZ_DEVADC2_OFFSET 0x0004 /* ADC2 Calibration */
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#define PIC32MZ_DEVADC3_OFFSET 0x0008 /* ADC3 Calibration */
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#define PIC32MZ_DEVADC4_OFFSET 0x000c /* ADC4 Calibration */
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#define PIC32MZ_DEVADC5_OFFSET 0x0010 /* ADC5 Calibration */
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/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
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#define PIC32MZ_DEVSN0_OFFSET 0x0000 /* Device serial number 0 */
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#define PIC32MZ_DEVSN1_OFFSET 0x0004 /* Device serial number 1 */
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/* Register/Flash Addresses *********************************************************/
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/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
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#define PIC32MZ_CFGCON (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGCON_OFFSET)
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#define PIC32MZ_DEVID (PIC32MZ_CONFIG_K1BASE+PIC32MZ_DEVID_OFFSET)
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#define PIC32MZ_SYSKEY (PIC32MZ_CONFIG_K1BASE+PIC32MZ_SYSKEY_OFFSET)
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#define PIC32MZ_CFGEBIA (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIA_OFFSET)
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#define PIC32MZ_CFGEBIC (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIC_OFFSET)
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#define PIC32MZ_CFGPG (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGPG_OFFSET)
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/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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#define PIC32MZ_ADEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG3_OFFSET)
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#define PIC32MZ_ADEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG2_OFFSET)
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#define PIC32MZ_ADEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG1_OFFSET)
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#define PIC32MZ_ADEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG0_OFFSET)
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#define PIC32MZ_ADEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP3_OFFSET)
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#define PIC32MZ_ADEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP2_OFFSET)
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#define PIC32MZ_ADEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP1_OFFSET)
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#define PIC32MZ_ADEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP0_OFFSET)
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#define PIC32MZ_ADEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN3_OFFSET)
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#define PIC32MZ_ADEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN2_OFFSET)
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#define PIC32MZ_ADEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN1_OFFSET)
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#define PIC32MZ_ADEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN0_OFFSET)
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/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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#define PIC32MZ_DEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG3_OFFSET)
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#define PIC32MZ_DEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG2_OFFSET)
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#define PIC32MZ_DEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG1_OFFSET)
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#define PIC32MZ_DEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG0_OFFSET)
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#define PIC32MZ_DEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP3_OFFSET)
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#define PIC32MZ_DEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP2_OFFSET)
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#define PIC32MZ_DEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP1_OFFSET)
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#define PIC32MZ_DEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP0_OFFSET)
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#define PIC32MZ_DEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN3_OFFSET)
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#define PIC32MZ_DEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN2_OFFSET)
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#define PIC32MZ_DEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN1_OFFSET)
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#define PIC32MZ_DEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN0_OFFSET)
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/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
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#define PIC32MZ_DEVADC1 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC1_OFFSET)
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#define PIC32MZ_DEVADC2 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC2_OFFSET)
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#define PIC32MZ_DEVADC3 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC3_OFFSET)
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#define PIC32MZ_DEVADC4 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC4_OFFSET)
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#define PIC32MZ_DEVADC5 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC5_OFFSET)
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/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */
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#define PIC32MZ_DEVSN0 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN0_OFFSET)
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#define PIC32MZ_DEVSN1 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN1_OFFSET)
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/* Register/Flash Bit Field Definitions *********************************************/
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/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
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/* Configuration control register */
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#define CFGCON_
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/* Device ID and revision register */
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#define DEVID_
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/* System key register */
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#define SYSKEY_
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/* External bus interface address pin configuration register */
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#define CFGEBIA_
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/* External bus interface address pin control register */
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#define CFGEBIC_
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/* Permission group configuration register */
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#define CFGPG_
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/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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/* Alternate device configuration word 3 */
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#define ADEVCFG3_
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/* Alternate device configuration word 2 */
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#define ADEVCFG2_
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/* Alternate device configuration word 1 */
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#define ADEVCFG1_
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/* Alternate device configuration word 0 */
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#define ADEVCFG0_
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/* Alternate device code protect word 3 */
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#define ADEVCP3_
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/* Alternate device code protect word 2 */
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#define ADEVCP2_
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/* Alternate device code protect word 1 */
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#define ADEVCP1_
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/* Alternate device code protect word 0 */
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#define ADEVCP0_
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/* Alternate evice signature word 3 */
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#define ADEVSIGN3_
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/* Alternate evice signature word 2 */
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#define ADEVSIGN2_
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/* Alternate evice signature word 1 */
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#define ADEVSIGN1_
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/* Alternate evice signature word 0 */
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#define ADEVSIGN0_
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/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
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/* Device configuration word 3 */
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#define DEVCFG3_
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/* Device configuration word 2 */
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#define DEVCFG2_
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/* Device configuration word 1 */
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#define DEVCFG1_
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/* Device configuration word 0 */
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#define DEVCFG0_
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/* Device code protect word 3 */
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#define DEVCP3_
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/* Device code protect word 2 */
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#define DEVCP2_
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/* Device code protect word 1 */
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#define DEVCP1_
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/* Device code protect word 0 */
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#define DEVCP0_
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/* Device signature word 3 */
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#define DEVSIGN3_
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/* Device signature word 2 */
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#define DEVSIGN2_
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/* Device signature word 1 */
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#define DEVSIGN1_
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/* Device signature word 0 */
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#define DEVSIGN0_
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/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
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/* ADC1 Calibration */
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#define DEVADC1_
|
||||
/* ADC2 Calibration */
|
||||
#define DEVADC2_
|
||||
/* ADC3 Calibration */
|
||||
#define DEVADC3_
|
||||
/* ADC4 Calibration */
|
||||
#define DEVADC4_
|
||||
/* ADC5 Calibration */
|
||||
#define DEVADC5_
|
||||
|
||||
/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
|
||||
/* Device serial number 0 */
|
||||
#define DEVSN0_OFFSET 0x0000 /* Device serial number 0 */
|
||||
/* Device serial number 1 */
|
||||
#define DEVSN1_OFFSET 0x0004 /* Device serial number 1 */
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H */
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/************************************************************************************
|
||||
* arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "mips32-memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Physical Memory Map **************************************************************/
|
||||
/* Memory Regions */
|
||||
|
||||
#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
|
||||
#define PIC32MZ_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
|
||||
#define PIC32MZ_SFR_PBASE 0x1f800000 /* Special function registers */
|
||||
#define PIC32MZ_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
|
||||
#define PIC32MZ_EBIMEM_PBASE 0x20000000 /* External memory via EBI */
|
||||
#define PIC32MZ_SQIMEM_PBASE 0x30000000 /* External memory via SQI */
|
||||
|
||||
/* Boot FLASH */
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_PBASE 0x1fc00000 /* Lower boot alias */
|
||||
#define PIC32MZ_CONFIG_PBASE 0x1fc0ff40 /* Configuration space */
|
||||
#define PIC32MZ_UPPERBOOT_PBASE 0x1fc20000 /* Upper boot alias */
|
||||
#define PIC32MZ_BOOT1_PBASE 0x1fc40000 /* Boot flash 1 */
|
||||
#define PIC32MZ_SEQCFG1_PBASE 0x1fc4ff40 /* Sequence/configuration space 1 */
|
||||
#define PIC32MZ_ADCCALIB_PBASE 0x1fc54000 /* ADC calibration space */
|
||||
#define PIC32MZ_DEVSN_PBASE 0x1fc54020 /* Device serial number */
|
||||
#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */
|
||||
#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff40 /* Sequence/configuration space 2 */
|
||||
|
||||
/* Virtual Memory Map ***************************************************************/
|
||||
|
||||
#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE)
|
||||
#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE)
|
||||
#define PIC32MZ_SFR_K0BASE (KSEG0_BASE + PIC32MZ_SFR_PBASE)
|
||||
#define PIC32MZ_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MZ_BOOTFLASH_PBASE)
|
||||
#define PIC32MZ_EBIMEM_K0BASE (KSEG0_BASE + PIC32MZ_EBIMEM_PBASE)
|
||||
#define PIC32MZ_SQIMEM_K0BASE (KSEG0_BASE + PIC32MZ_SQIMEM_PBASE)
|
||||
|
||||
#define PIC32MZ_DATAMEM_K1BASE (KSEG1_BASE + PIC32MZ_DATAMEM_PBASE)
|
||||
#define PIC32MZ_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MZ_PROGFLASH_PBASE)
|
||||
#define PIC32MZ_SFR_K1BASE (KSEG1_BASE + PIC32MZ_SFR_PBASE)
|
||||
#define PIC32MZ_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MZ_BOOTFLASH_PBASE)
|
||||
#define PIC32MZ_EBIMEM_K1BASE (KSEG1_BASE + PIC32MZ_EBIMEM_PBASE)
|
||||
#define PIC32MZ_SQIMEM_K1BASE (KSEG1_BASE + PIC32MZ_SQIMEM_PBASE)
|
||||
|
||||
/* Boot FLASH */
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_LOWERBOOT_PBASE)
|
||||
#define PIC32MZ_CONFIG_K0BASE (KSEG0_BASE + PIC32MZ_CONFIG_PBASE)
|
||||
#define PIC32MZ_UPPERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_UPPERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOT1_K0BASE (KSEG0_BASE + PIC32MZ_BOOT1_PBASE)
|
||||
#define PIC32MZ_SEQCFG1_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG1_PBASE)
|
||||
#define PIC32MZ_ADCCALIB_K0BASE (KSEG0_BASE + PIC32MZ_ADCCALIB_PBASE)
|
||||
#define PIC32MZ_DEVSN_K0BASE (KSEG0_BASE + PIC32MZ_DEVSN_PBASE)
|
||||
#define PIC32MZ_BOOT2_K0BASE (KSEG0_BASE + PIC32MZ_BOOT2_PBASE)
|
||||
#define PIC32MZ_SEQCFG2_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG2_PBASE)
|
||||
|
||||
#define PIC32MZ_LOWERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_LOWERBOOT_PBASE)
|
||||
#define PIC32MZ_CONFIG_K1BASE (KSEG1_BASE + PIC32MZ_CONFIG_PBASE)
|
||||
#define PIC32MZ_UPPERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_UPPERBOOT_PBASE)
|
||||
#define PIC32MZ_BOOT1_K1BASE (KSEG1_BASE + PIC32MZ_BOOT1_PBASE)
|
||||
#define PIC32MZ_SEQCFG1_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG1_PBASE)
|
||||
#define PIC32MZ_ADCCALIB_K1BASE (KSEG1_BASE + PIC32MZ_ADCCALIB_PBASE)
|
||||
#define PIC32MZ_DEVSN_K1BASE (KSEG1_BASE + PIC32MZ_DEVSN_PBASE)
|
||||
#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE)
|
||||
#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE)
|
||||
|
||||
/* Register Base Addresses **********************************************************/
|
||||
|
||||
#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */
|
||||
#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */
|
||||
#define PIC32MZ_WDT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000800) /* Watchdog Timer */
|
||||
#define PIC32MZ_DMT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000a00) /* Deadman Timer */
|
||||
#define PIC32MZ_RTCC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000c00) /* RTCC */
|
||||
#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */
|
||||
#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */
|
||||
#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */
|
||||
#define PIC32MZ_INTC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */
|
||||
#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */
|
||||
#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */
|
||||
#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */
|
||||
#define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */
|
||||
#define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */
|
||||
#define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */
|
||||
#define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */
|
||||
#define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */
|
||||
#define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */
|
||||
#define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */
|
||||
#define PIC32MZ_PORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */
|
||||
#define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */
|
||||
#define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */
|
||||
#define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */
|
||||
#define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */
|
||||
#define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */
|
||||
#define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */
|
||||
#define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */
|
||||
#define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */
|
||||
#define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/********************************************************************************************
|
||||
* arch/mips/src/pic32mz/excptmacros.h
|
||||
* arch/mips/src/pic32mz/pic32mz-excptmacros.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
|
|
|||
Loading…
Reference in New Issue