Add phy read/write routines
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2635 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
3e234582b5
commit
79f4054bff
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@ -201,9 +201,9 @@ static void enc_wdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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uint8_t wrdata);
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static void enc_setbank(FAR struct enc_driver_s *priv, uint8_t bank);
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static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
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static uint8_t enc_wrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
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static void enc_wrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
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uint8_t wrdata);
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static uint8_t enc_rdphymac(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
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static uint8_t enc_rdmreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
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/* SPI buffer transfers */
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@ -355,9 +355,12 @@ static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd)
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enc_select(spi);
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/* Send the read command and (maybe collect the return data) */
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/* Send the read command and collect the data. The sequence requires
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* 16-clocks: 8 to clock out the cmd + 8 to clock in the data.
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*/
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rddata = SPI_SEND(spi, cmd);
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(void)SPI_SEND(spi, cmd); /* Clock out the command */
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rddata = SPI_SEND(spi, 0); /* Clock in the data */
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/* De-select ENC28J60 chip */
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@ -386,13 +389,12 @@ static void enc_wdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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enc_select(spi);
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/* Send the write command */
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/* Send the write command and data. The sequence requires 16-clocks:
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* 8 to clock out the cmd + 8 to clock out the data.
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*/
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(void)SPI_SEND(spi, cmd);
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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(void)SPI_SEND(spi, cmd); /* Clock out the command */
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(void)SPI_SEND(spi, wrdata); /* Clock out the data */
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/* De-select ENC28J60 chip. */
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@ -437,7 +439,7 @@ static void enc_setbank(FAR struct enc_driver_s *priv, uint8_t bank)
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* Function: enc_rdbreg
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*
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* Description:
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* Set the bank for these next control register access.
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* Read from a banked control register using the RCR command.
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*
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****************************************************************************/
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@ -453,13 +455,16 @@ static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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enc_select(spi);
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/* set the bank */
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/* Set the bank */
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enc_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command and collect the return data. */
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/* Send the RCR command and collect the data. The sequence requires
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* 16-clocks: 8 to clock out the cmd + 8 to clock in the data.
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*/
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rddata = SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg));
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(void)SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg)); /* Clock out the command */
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rddata = SPI_SEND(spi, 0); /* Clock in the data */
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/* De-select ENC28J60 chip */
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@ -468,7 +473,7 @@ static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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}
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/****************************************************************************
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* Function: enc_rdphymac
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* Function: enc_rdmreg
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*
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* Description:
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* Somewhat different timing is required to read from any PHY or MAC
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@ -477,7 +482,7 @@ static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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*
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****************************************************************************/
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static uint8_t enc_rdphymac(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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static uint8_t enc_rdmreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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@ -493,13 +498,14 @@ static uint8_t enc_rdphymac(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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enc_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command (discarding the return data) */
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/* Send the RCR command and collect the data. The sequence requires
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* 24-clocks: 8 to clock out the cmd, 8 dummy bits, and 8 to clock in
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the data.
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*/
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(void)SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg));
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/* Do an extra transfer to get the data from the MAC or PHY */
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rddata = SPI_SEND(spi, 0);
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(void)SPI_SEND(spi, ENC_RCR | GETADDR(ctrlreg)); /* Clock out the command */
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(void)SPI_SEND(spi,0); /* Clock in the dummy byte */
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rddata = SPI_SEND(spi, 0); /* Clock in the PHY/MAC data */
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/* De-select ENC28J60 chip */
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@ -508,15 +514,15 @@ static uint8_t enc_rdphymac(FAR struct enc_driver_s *priv, uint8_t ctrlreg)
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}
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/****************************************************************************
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* Function: enc_rwrbreg
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* Function: enc_wrbreg
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*
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* Description:
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* Set the bank for these next control register access.
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* Write to a banked control register using the WCR command.
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*
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****************************************************************************/
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static void enc_rwrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
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uint8_t wrdata)
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static void enc_wrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
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uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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@ -531,13 +537,12 @@ static void enc_rwrbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg,
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enc_setbank(priv, GETBANK(ctrlreg));
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/* Send the write command */
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/* Send the WCR command and data. The sequence requires 16-clocks:
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* 8 to clock out the cmd + 8 to clock out the data.
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*/
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(void)SPI_SEND(spi, ENC_WCR | GETADDR(ctrlreg));
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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(void)SPI_SEND(spi, ENC_WCR | GETADDR(ctrlreg)); /* Clock out the command */
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(void)SPI_SEND(spi, wrdata); /* Clock out the data */
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/* De-select ENC28J60 chip. */
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@ -610,6 +615,63 @@ static void enc_wrbuffer(FAR struct enc_driver_s *priv,
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enc_deselect(spi);
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}
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/****************************************************************************
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* Function: enc_rdphy
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*
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* Description:
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* Read 16-bits of PHY data.
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*
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****************************************************************************/
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static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
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{
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uint16_t data;
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/* Set the PHY address (and start the PHY read operation) */
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enc_wrbreg(priv, ENC_MIREGADR, phyaddr);
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enc_wrbreg(priv, ENC_MICMD, MICMD_MIIRD);
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/* Wait until the PHY read completes */
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while ((enc_rdmreg(priv, ENC_MISTAT) & MISTAT_BUSY) != 0 );
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/* Terminate reading */
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enc_wrbreg(priv, ENC_MICMD, 0x00);
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/* Get data value */
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data = (uint16_t)enc_rdmreg(priv, ENC_MIRDL);
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data |= (uint16_t)enc_rdmreg(priv, ENC_MIRDH) << 8;
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return data;
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}
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/****************************************************************************
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* Function: enc_wrphy
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*
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* Description:
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* write 16-bits of PHY data.
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*
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****************************************************************************/
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static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
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uint16_t phydata)
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{
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/* Set the PHY register address */
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enc_wrbreg(priv, ENC_MIREGADR, phyaddr);
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/* Write the PHY data */
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enc_wrbreg(priv, ENC_MIWRL, phydata);
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enc_wrbreg(priv, ENC_MIWRH, phydata >> 8);
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/* Wait until the PHY write completes */
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while ((enc_rdmreg(priv, ENC_MISTAT) & MISTAT_BUSY) != 0);
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}
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/****************************************************************************
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* Function: enc_transmit
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*
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@ -776,7 +838,8 @@ static void enc_txerif(FAR struct enc_driver_s *priv)
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enc_bfsgreg(priv, ENC_ECON1, ECON1_TXRST);
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enc_bfcgreg(priv, ENC_ECON1, ECON1_TXRST | ECON1_TXRTS);
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/* Here we really should re-transmit:
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/* Here we really should re-transmit (I fact, if we want half duplex to
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* work right, then it is necessary to do this!):
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*
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* 1. Read the TSV:
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* - Read ETXNDL to get the end pointer
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@ -225,12 +225,24 @@
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#define ENC_EPKTCNT REGADDR(0x19, 1) /* Ethernet Packet Count */
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Receive Filter Configuration Bit Definitions */
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#define ERXFCON_BCEN (1 << 0) /* Bit 0: Broadcast Filter Enable */
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#define ERXFCON_MCEN (1 << 1) /* Bit 1: Multicast Filter Enable */
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#define ERXFCON_HTEN (1 << 2) /* Bit 2: Hash Table Filter Enable */
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#define ERXFCON_MPEN (1 << 3) /* Bit 3: Magic Packet Filter Enable */
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#define ERXFCON_PMEN (1 << 4) /* Bit 4: Pattern Match Filter Enable */
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#define ERXFCON_CRCEN (1 << 5) /* Bit 5: Post-Filter CRC Check Enable */
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#define ERXFCON_ANDOR (1 << 6) /* Bit 6: AND/OR Filter Select */
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#define ERXFCON_UCEN (1 << 7) /* Bit 7: Unicast Filter Enable */
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/* Bank 2 Control Register Addresses */
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#define ENC_MACON1 REGADDR(0x00, 2) /* MAC control 1 */
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#define ENC_MACON2 REGADDR(0x01, 2) /* MAC control 2 */
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#define ENC_MACON3 REGADDR(0x02, 2) /* MAC control 3 */
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#define ENC_MACON4 REGADDR(0x03, 2) /* MAC control 4 */
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#define ENC_MACON1 REGADDR(0x00, 2) /* MAC Control 1 */
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/* 0x01: Reserved */
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#define ENC_MACON3 REGADDR(0x02, 2) /* MAC Control 3 */
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#define ENC_MACON4 REGADDR(0x03, 2) /* MAC Control 4 */
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#define ENC_MABBIPG REGADDR(0x04, 2) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
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/* 0x05: Reserved */
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#define ENC_MAIPGL REGADDR(0x06, 2) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
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@ -250,6 +262,37 @@
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#define ENC_MIRDH REGADDR(0x19, 2) /* MII Read Data High Byte(MIRD<15:8>) */
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* MAC Control 1 Register Bit Definitions */
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#define MACON1_MARXEN (1 << 0) /* Bit 0: MAC Receive Enable */
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#define MACON1_PASSALL (1 << 1) /* Bit 1: Pass All Received Frames Enable */
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#define MACON1_RXPAUS (1 << 2) /* Bit 2: Pause Control Frame Reception Enable */
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#define MACON1_TXPAUS (1 << 3) /* Bit 3: Pause Control Frame Transmission Enable */
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/* Bits 4-7: Unimplemented or reserved */
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/* MAC Control 1 Register Bit Definitions */
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#define MACON3_FULDPX (1 << 0) /* Bit 0: MAC Full-Duplex Enable */
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#define MACON3_FRMLNEN (1 << 1) /* Bit 1: Frame Length Checking Enable */
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#define MACON3_HFRMLEN (1 << 2) /* Bit 2: Huge Frame Enable */
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#define MACON3_PHDRLEN (1 << 3) /* Bit 3: Proprietary Header Enable */
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#define MACON3_TXCRCEN (1 << 4) /* Bit 4: Transmit CRC Enable */
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#define MACON3_PADCFG0 (1 << 5) /* Bit 5: Automatic Pad and CRC Configuration */
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#define MACON3_PADCFG1 (1 << 6) /* Bit 6: " " " " " " " " " " */
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#define MACON3_PADCFG2 (1 << 7) /* Bit 7: " " " " " " " " " " */
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/* MAC Control 1 Register Bit Definitions */
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#define MACON4_NOBKOFF (1 << 4) /* Bit 4: No Backoff Enable */
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#define MACON4_BPEN (1 << 5) /* Bit 5: No Backoff During Backpressure Enable */
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#define MACON4_DEFER (1 << 6) /* Bit 6: Defer Transmission Enable bit */
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/* MII Command Register Bit Definitions */
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#define MICMD_MIIRD (1 << 0) /* Bit 0: MII Read Enable */
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#define MICMD_MIISCAN (1 << 1) /* Bit 1: MII Scan Enable */
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/* Bank 3 Control Register Addresses */
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#define ENC_MAADR5 REGADDR(0x00, 3) /* MAC Address Byte 5 (MAADR<15:8>) */
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@ -274,6 +317,31 @@
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/* 0x1a: Reserved */
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/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
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/* Built-in Self-Test Control Register Bit Definitions */
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#define EBSTCON_BISTST (1 << 0) /* Bit 0: Built-in Self-Test Start/Busy */
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#define EBSTCON_TME (1 << 1) /* Bit 1: Test Mode Enable */
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#define EBSTCON_TMSEL0 (1 << 2) /* Bit 2: Test Mode Select */
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#define EBSTCON_TMSEL1 (1 << 3) /* Bit 3: " " " " " " */
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#define EBSTCON_PSEL (1 << 4) /* Bit 4: Port Select */
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#define EBSTCON_PSV0 (1 << 5) /* Bit 5: Pattern Shift Value */
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#define EBSTCON_PSV1 (1 << 6) /* Bit 6: " " " " " */
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#define EBSTCON_PSV2 (1 << 7) /* Bit 7: " " " " " */
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/* MII Status Register Register Bit Definitions */
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#define MISTAT_BUSY (1 << 0) /* Bit 0: MII Management Busy */
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#define MISTAT_SCAN (1 << 1) /* Bit 1: MII Management Scan Operation */
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#define MISTAT_NVALID (1 << 2) /* Bit 2: MII Management Read Data Not Valid */
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/* Bits 3-7: Reserved or unimplemented */
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/* Ethernet Flow Control Register Bit Definitions */
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#define EFLOCON_FCEN0 (1 << 0) /* Bit 0: Flow Control Enable */
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#define EFLOCON_FCEN1 (1 << 1) /* Bit 1: " " " " " " */
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#define EFLOCON_FULDPXS (1 << 2) /* Bit 2: Read-Only MAC Full-Duplex Shadow */
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/* Bits 3-7: Reserved or unimplemented */
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/* PHY Registers ************************************************************/
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#define ENC_PHCON1 (0x00) /* PHY Control Register 1 */
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@ -328,6 +396,7 @@
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/* PHLCON Regiser Bit Definitions */
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/* Bit 0: Reserved */
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#define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */
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#define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */
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#define PHLCON_LFRQ1 (1 << 3) /* Bit 3: " " " " " " " " " */
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@ -340,6 +409,13 @@
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#define PHLCON_LACFG2 (1 << 10) /* Bit 10: " " " " */
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#define PHLCON_LACFG3 (1 << 11) /* Bit 11: " " " " */
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/* Packet Control Bits Definitions ******************************************/
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#define PKTCTRL_POVERRIDE (1 << 0) /* Bit 0: Per Packet Override */
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#define PKTCTRL_PCRCEN (1 << 1) /* Bit 1: Per Packet CRC Enable */
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#define PKTCTRL_PPADEN (1 << 2) /* Bit 2: Per Packet Padding Enable */
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#define PKTCTRL_PHUGEEN (1 << 3) /* Bit 3: Per Packet Huge Frame Enable */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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