Add SSP driver
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2746 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
91be728e74
commit
791714ad4f
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@ -53,7 +53,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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CHIP_ASRCS =
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CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpio.c \
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lpc17_gpioint.c lpc17_irq.c lpc17_lowputc.c lpc17_serial.c \
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lpc17_start.c lpc17_timerisr.c
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lpc17_ssp.c lpc17_start.c lpc17_timerisr.c
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# Configuration-dependent LPC17xx files
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@ -205,7 +205,7 @@
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#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_MOSI1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
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#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
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@ -224,7 +224,7 @@
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#define GPIO_SPI_MISO (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
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#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_SSP0_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_SPI_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
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#define GPIO_I2C1_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
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#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20)
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@ -495,6 +495,71 @@ EXTERN int lpc17_dumpgpio(uint32_t pinset, const char *msg);
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# define lpc17_dumpgpio(p,m)
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#endif
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/************************************************************************************
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* Name: lpc17_spi/ssp0/ssp1select and lpc17_spi/ssp0/ssp1status
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*
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* Description:
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* The external functions, lpc17_spi/ssp0/ssp1select and lpc17_spi/ssp0/ssp1status
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* must be provided by board-specific logic. They are implementations of the select
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* and status methods of the SPI interface defined by struct spi_ops_s (see
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* include/nuttx/spi.h). All other methods (including up_spiinitialize())
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* are provided by common LPC17xx logic. To use this common SPI logic on your
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* board:
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*
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* 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select
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* pins.
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* 2. Provide lpc17_spi/ssp0/ssp1select() and lpc17_spi/ssp0/ssp1status() functions
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* in your board-specific logic. These functions will perform chip selection
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* and status operations using GPIOs in the way your board is configured.
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* 3. Add a calls to up_spiinitialize() in your low level application
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* initialization logic
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* 4. The handle returned by up_spiinitialize() may then be used to bind the
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* SPI driver to higher level logic (e.g., calling
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* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
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* the SPI MMC/SD driver).
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*
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************************************************************************************/
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struct spi_dev_s;
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enum spi_dev_e;
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#ifdef CONFIG_LPC17_SPI
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EXTERN void lpc17_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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EXTERN uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
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#endif
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#ifdef CONFIG_LPC17_SSP0
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EXTERN void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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EXTERN uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
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#endif
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#ifdef CONFIG_LPC17_SSP1
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EXTERN void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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EXTERN uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
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#endif
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/****************************************************************************
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* Name: ssp_flush
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*
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* Description:
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* Flush and discard any words left in the RX fifo. This can be called
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* from ssp0/1select after a device is deselected (if you worry about such
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* things).
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*
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* Input Parameters:
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* dev - Device-specific state data
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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struct spi_dev_s;
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#ifdef CONFIG_LPC17_SPI
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EXTERN void spi_flush(FAR struct spi_dev_s *dev);
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#endif
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#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
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EXTERN void ssp_flush(FAR struct spi_dev_s *dev);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@ -0,0 +1,815 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_ssp.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/spi.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "lpc17_internal.h"
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#include "lpc17_syscon.h"
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#include "lpc17_pinconn.h"
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#include "lpc17_ssp.h"
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#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Enables debug output from this file (needs CONFIG_DEBUG too) */
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#undef SSP_DEBUG /* Define to enable debug */
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#undef SSP_VERBOSE /* Define to enable verbose debug */
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#ifdef SSP_DEBUG
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# define sspdbg lldbg
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# ifdef SSP_VERBOSE
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# define spivdbg lldbg
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# else
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# define spivdbg(x...)
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# endif
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#else
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# undef SSP_VERBOSE
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# define sspdbg(x...)
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# define spivdbg(x...)
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#endif
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/* SSP Clocking.
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*
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* The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK).
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* SSP_CLOCK may be further divided by 2-254 to get the SSP clock. If we
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* want a usable range of 4KHz to 25MHz for the SSP, then:
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*
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* 1. SSPCLK must be greater than (2*25MHz) = 50MHz, and
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* 2. SSPCLK must be less than (254*40Khz) = 101.6MHz.
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*
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* If we assume that CCLK less than or equal to 100MHz, we can just
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* use the CCLK undivided to get the SSP_CLOCK.
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*/
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#define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
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#define SSP_CLOCK LPC17_CCLK
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct lpc17_sspdev_s
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{
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struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
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uint32_t sspbase; /* SPIn base address */
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#ifdef CONFIG_LPC17_SSP_INTERRUPTS
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uint8_t sspirq; /* SPI IRQ number */
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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sem_t exclsem; /* Held while chip is selected for mutual exclusion */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t nbits; /* Width of word in bits (8 or 16) */
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uint8_t mode; /* Mode 0,1,2,3 */
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Helpers */
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static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset);
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static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset,
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uint32_t value);
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/* SPI methods */
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#ifndef CONFIG_SPI_OWNBUS
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static int ssp_lock(FAR struct spi_dev_s *dev, bool lock);
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#endif
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static void ssp_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
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static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
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static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits);
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static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch);
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static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
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static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_LPC17_SSP0
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static const struct spi_ops_s g_spi0ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = ssp_lock,
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#endif
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.select = lpc17_ssp0select,
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.setfrequency = ssp_setfrequency,
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.setmode = ssp_setmode,
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.setbits = ssp_setbits,
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.status = lpc17_ssp0status,
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.send = ssp_send,
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.sndblock = ssp_sndblock,
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.recvblock = ssp_recvblock,
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.registercallback = 0, /* Not implemented */
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};
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static struct lpc17_sspdev_s g_ssp0dev =
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{
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.spidev = { &g_spi0ops },
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.sspbase = LPC17_SSP0_BASE,
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#ifdef CONFIG_LPC17_SSP_INTERRUPTS
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.sspirq = LPC17_IRQ_SSP0,
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#endif
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};
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#endif /* CONFIG_LPC17_SSP0 */
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#ifdef CONFIG_LPC17_SSP1
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static const struct spi_ops_s g_spi1ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = ssp_lock,
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#endif
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.select = lpc17_ssp1select,
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.setfrequency = ssp_setfrequency,
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.setmode = ssp_setmode,
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.setbits = ssp_setbits,
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.status = lpc17_ssp1status,
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.send = ssp_send,
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.sndblock = ssp_sndblock,
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.recvblock = ssp_recvblock,
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.registercallback = 0, /* Not implemented */
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};
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static struct lpc17_sspdev_s g_ssp1dev =
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{
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.spidev = { &g_spi1ops },
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.sspbase = LPC17_SSP1_BASE,
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#ifdef CONFIG_LPC17_SSP_INTERRUPTS
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.sspirq = LPC17_IRQ_SSP1,
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#endif
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};
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#endif /* CONFIG_LPC17_SSP1 */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/************************************************************************************
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* Name: ssp_getreg
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*
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* Description:
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* Get the contents of the SPI register at offset
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*
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* Input Parameters:
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* priv - private SPI device structure
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* offset - offset to the register of interest
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*
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* Returned Value:
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* The contents of the 32-bit register
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*
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************************************************************************************/
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static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset)
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{
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return ssp_getreg(priv, priv->sspbase + offset);
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}
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/************************************************************************************
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* Name: ssp_putreg
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*
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* Description:
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* Write a 32-bit value to the SPI register at offset
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*
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* Input Parameters:
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* priv - private SPI device structure
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* offset - offset to the register of interest
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* value - the 16-bit value to be written
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, uint32_t value)
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{
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putreg32(value, priv->sspbase + offset);
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}
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/****************************************************************************
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* Name: ssp_lock
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*
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* Description:
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* On SPI busses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the busses for a sequence of
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* transfers. The bus should be locked before the chip is selected. After
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* locking the SPI bus, the caller should then also call the setfrequency,
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* setbits, and setmode methods to make sure that the SPI is properly
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* configured for the device. If the SPI buss is being shared, then it
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* may have been left in an incompatible state.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* lock - true: Lock spi bus, false: unlock SPI bus
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifndef CONFIG_SPI_OWNBUS
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static int ssp_lock(FAR struct spi_dev_s *dev, bool lock)
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{
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FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
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if (lock)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&priv->exclsem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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else
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{
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(void)sem_post(&priv->exclsem);
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}
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: ssp_setfrequency
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*
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* Description:
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* Set the SPI frequency.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* frequency - The SPI frequency requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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*
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****************************************************************************/
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static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
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{
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FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
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uint32_t divisor;
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uint32_t actual;
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/* Check if the requested frequence is the same as the frequency selection */
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DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2);
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#ifndef CONFIG_SPI_OWNBUS
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if (priv->frequency == frequency)
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{
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/* We are already at this frequency. Return the actual. */
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return priv->actual;
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}
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#endif
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/* frequency = SSP_CLOCK / divisor, or divisor = SSP_CLOCK / frequency */
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divisor = SSP_CLOCK / frequency;
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/* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */
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if (divisor < 2)
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{
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divisor = 2;
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}
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else if (divisor > 254)
|
||||
{
|
||||
divisor = 254;
|
||||
}
|
||||
|
||||
divisor = (divisor + 1) & ~1;
|
||||
|
||||
/* Save the new divisor value */
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_CPSR_OFFSET, divisor);
|
||||
|
||||
/* Calculate the new actual */
|
||||
|
||||
actual = SSP_CLOCK / divisor;
|
||||
|
||||
/* Save the frequency setting */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->frequency = frequency;
|
||||
priv->actual = actual;
|
||||
#endif
|
||||
|
||||
sspdbg("Frequency %d->%d\n", frequency, actual);
|
||||
return actual;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: ssp_setmode
|
||||
*
|
||||
* Description:
|
||||
* Set the SPI mode. Optional. See enum spi_mode_e for mode definitions
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* mode - The SPI mode requested
|
||||
*
|
||||
* Returned Value:
|
||||
* none
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
uint32_t regval;
|
||||
|
||||
/* Has the mode changed? */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
if (mode != priv->mode)
|
||||
{
|
||||
#endif
|
||||
/* Yes... Set CR0 appropriately */
|
||||
|
||||
regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET);
|
||||
regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA);
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
|
||||
regval |= SSP_CR0_CPHA;
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
|
||||
regval |= SSP_CR0_CPOL;
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
|
||||
regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA);
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUGASSERT(FALSE);
|
||||
return;
|
||||
}
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, regval);
|
||||
|
||||
/* Save the mode so that subsequent re-configuratins will be faster */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->mode = mode;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: ssp_setbits
|
||||
*
|
||||
* Description:
|
||||
* Set the number if bits per word.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* nbits - The number of bits requests
|
||||
*
|
||||
* Returned Value:
|
||||
* none
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
uint32_t regval;
|
||||
|
||||
/* Has the number of bits changed? */
|
||||
|
||||
DEBUGASSERT(priv && nbits > 3 && nbits < 17);
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
if (nbits != priv->nbits)
|
||||
{
|
||||
#endif
|
||||
/* Yes... Set CR1 appropriately */
|
||||
|
||||
regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET);
|
||||
regval &= ~SSP_CR0_DSS_MASK;
|
||||
regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT);
|
||||
regval = ssp_getreg(priv, LPC17_SSP_CR0_OFFSET);
|
||||
|
||||
/* Save the selection so the subsequence re-configurations will be faster */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->nbits = nbits;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: ssp_send
|
||||
*
|
||||
* Description:
|
||||
* Exchange one word on SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* wd - The word to send. the size of the data is determined by the
|
||||
* number of bits selected for the SPI interface.
|
||||
*
|
||||
* Returned Value:
|
||||
* response
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
register uint16_t regval;
|
||||
|
||||
/* Wait while the TX FIFO is full */
|
||||
|
||||
while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF));
|
||||
|
||||
/* Write the byte to the TX FIFO */
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_DR_OFFSET, (uint32_t)wd);
|
||||
|
||||
/* Wait for the RX FIFO not empty */
|
||||
|
||||
while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE));
|
||||
|
||||
/* Get the value from the RX FIFO and return it */
|
||||
|
||||
regval = ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
|
||||
sspdbg("%04x->%04x\n", wd, regval);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* Name: ssp_sndblock
|
||||
*
|
||||
* Description:
|
||||
* Send a block of data on SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* buffer - A pointer to the buffer of data to be sent
|
||||
* nwords - the length of data to send from the buffer in number of words.
|
||||
* The wordsize is determined by the number of bits-per-word
|
||||
* selected for the SPI interface. If nbits <= 8, the data is
|
||||
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
FAR const uint8_t *ptr = (FAR const uint8_t *)buffer;
|
||||
uint8_t sr;
|
||||
|
||||
/* Loop while thre are bytes remaining to be sent */
|
||||
|
||||
sspdbg("nwords: %d\n", nwords);
|
||||
while (nwords > 0)
|
||||
{
|
||||
/* While the TX FIFO is not full and there are bytes left to send */
|
||||
|
||||
while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords)
|
||||
{
|
||||
/* Send the data */
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_DR_OFFSET, (uint32_t)*ptr);
|
||||
ptr++;
|
||||
nwords--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Then discard all card responses until the RX & TX FIFOs are emptied. */
|
||||
|
||||
sspdbg("discarding\n");
|
||||
do
|
||||
{
|
||||
/* Is there anything in the RX fifo? */
|
||||
|
||||
sr = ssp_getreg(priv, LPC17_SSP_SR_OFFSET);
|
||||
if ((sr & SSP_SR_RNE) != 0)
|
||||
{
|
||||
/* Yes.. Read and discard */
|
||||
|
||||
(void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
|
||||
}
|
||||
|
||||
/* There is a race condition where TFE may go true just before
|
||||
* RNE goes true and this loop terminates prematurely. The nasty little
|
||||
* delay in the following solves that (it could probably be tuned
|
||||
* to improve performance).
|
||||
*/
|
||||
|
||||
else if ((sr & SSP_SR_TFE) != 0)
|
||||
{
|
||||
up_udelay(100);
|
||||
sr = ssp_getreg(priv, LPC17_SSP_SR_OFFSET);
|
||||
}
|
||||
}
|
||||
while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: ssp_recvblock
|
||||
*
|
||||
* Description:
|
||||
* Revice a block of data from SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* buffer - A pointer to the buffer in which to recieve data
|
||||
* nwords - the length of data that can be received in the buffer in number
|
||||
* of words. The wordsize is determined by the number of bits-per-word
|
||||
* selected for the SPI interface. If nbits <= 8, the data is
|
||||
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
|
||||
uint32_t rxpending = 0;
|
||||
|
||||
/* While there is remaining to be sent (and no synchronization error has occurred) */
|
||||
|
||||
sspdbg("nwords: %d\n", nwords);
|
||||
while (nwords || rxpending)
|
||||
{
|
||||
/* Fill the transmit FIFO with 0xff...
|
||||
* Write 0xff to the data register while (1) the TX FIFO is
|
||||
* not full, (2) we have not exceeded the depth of the TX FIFO,
|
||||
* and (3) there are more bytes to be sent.
|
||||
*/
|
||||
|
||||
spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
|
||||
while ((ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF) &&
|
||||
(rxpending < LPC17_SSP_FIFOSZ) && nwords)
|
||||
{
|
||||
ssp_putreg(priv, LPC17_SSP_DR_OFFSET, 0xff);
|
||||
nwords--;
|
||||
rxpending++;
|
||||
}
|
||||
|
||||
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
|
||||
|
||||
spivdbg("RX: rxpending: %d\n", rxpending);
|
||||
while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE)
|
||||
{
|
||||
*ptr++ = (uint8_t)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
|
||||
rxpending--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_spiinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port
|
||||
*
|
||||
* Input Parameter:
|
||||
* Port number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv;
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
||||
/* Only the SSP0 and SSP1 interfaces are supported */
|
||||
|
||||
switch (port)
|
||||
{
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
case 0:
|
||||
priv = &g_ssp0dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_LPC17_SSP1
|
||||
case 1:
|
||||
priv = &g_ssp1dev;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Configure multiplexed pins as connected on the board. Chip select
|
||||
* pins must be configured by board-specific logic. All SSP0 pins and
|
||||
* one SSP1 pin (SCK) have multiple, alternative pin selection.
|
||||
* Definitions in the board.h file must be provided to resolve the
|
||||
* board-specific pin configuration like:
|
||||
*
|
||||
* #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
lpc17_configgpio(GPIO_SSP0_SCK);
|
||||
lpc17_configgpio(GPIO_SSP0_MISO);
|
||||
lpc17_configgpio(GPIO_SSP0_MOSI);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
lpc17_configgpio(GPIO_SSP1_SCK);
|
||||
lpc17_configgpio(GPIO_SSP1_MISO);
|
||||
lpc17_configgpio(GPIO_SSP1_MOSI);
|
||||
#endif
|
||||
|
||||
/* Configure clocking */
|
||||
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
|
||||
regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
|
||||
regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
|
||||
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
|
||||
regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
|
||||
regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
|
||||
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
|
||||
#endif
|
||||
|
||||
/* Enable peripheral clocking to SSP0 and SSP1 */
|
||||
|
||||
regval = getreg32(LPC17_SYSCON_PCONP);
|
||||
regval &= ~(SYSCON_PCONP_PCSSP0|SYSCON_PCONP_PCSSP1);
|
||||
#ifdef CONFIG_LPC17_SSP0
|
||||
regval |= SYSCON_PCONP_PCSSP0;
|
||||
#else
|
||||
regval |= SYSCON_PCONP_PCSSP1;
|
||||
#endif
|
||||
putreg32(regval, LPC17_SYSCON_PCONP);
|
||||
irqrestore(flags);
|
||||
|
||||
/* Configure 8-bit SPI mode */
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI);
|
||||
|
||||
/* Disable the SSP and all interrupts (we'll poll for all data) */
|
||||
|
||||
ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, 0);
|
||||
ssp_putreg(priv, LPC17_SSP_IMSC_OFFSET, 0);
|
||||
|
||||
/* Set the initial SSP configuration */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->frequency = 0;
|
||||
priv->nbits = 8;
|
||||
priv->mode = SPIDEV_MODE0;
|
||||
#endif
|
||||
|
||||
/* Select a default frequency of approx. 400KHz */
|
||||
|
||||
ssp_setfrequency((FAR struct spi_dev_s *)priv, 400000);
|
||||
|
||||
/* Initialize the SPI semaphore that enforces mutually exclusive access */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
sem_init(&priv->exclsem, 0, 1);
|
||||
#endif
|
||||
|
||||
/* Enable the SPI */
|
||||
|
||||
regval = ssp_getreg(priv, LPC17_SSP_CR1_OFFSET);
|
||||
ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, regval | SSP_CR1_SSE);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
(void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
|
||||
}
|
||||
|
||||
return &priv->spidev;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: ssp_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush and discard any words left in the RX fifo. This can be done
|
||||
* after a device is deselected if you worry about such things.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void ssp_flush(FAR struct spi_dev_s *dev)
|
||||
{
|
||||
FAR struct lpc17_sspdev_s *priv = (FAR struct lpc17_sspdev_s *)dev;
|
||||
|
||||
/* Wait for the TX FIFO not full indication */
|
||||
|
||||
while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_TNF));
|
||||
ssp_putreg(priv, LPC17_SSP_DR_OFFSET, 0xff);
|
||||
|
||||
/* Wait until TX FIFO and TX shift buffer are empty */
|
||||
|
||||
while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_BSY);
|
||||
|
||||
/* Wait until RX FIFO is not empty */
|
||||
|
||||
while (!(ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE));
|
||||
|
||||
/* Then read and discard bytes until the RX FIFO is empty */
|
||||
|
||||
do
|
||||
{
|
||||
(void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
|
||||
}
|
||||
while (ssp_getreg(priv, LPC17_SSP_SR_OFFSET) & SSP_SR_RNE);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LPC17_SSP0/1 */
|
||||
|
||||
|
|
@ -48,6 +48,9 @@
|
|||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* 8 frame FIFOs for both transmit and receive */
|
||||
|
||||
#define LPC17_SSP_FIFOSZ 8
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@
|
|||
#define LED_PANIC 7 /* RED RED NC (1Hz flashing) */
|
||||
|
||||
/* Alternate pin selections *********************************************************/
|
||||
/* UART1 -- Not connected */
|
||||
|
||||
#define GPIO_UART1_TXD GPIO_UART1_TXD_1
|
||||
#define GPIO_UART1_RXD GPIO_UART1_RXD_1
|
||||
|
|
@ -150,12 +151,29 @@
|
|||
#define GPIO_UART1_RI GPIO_UART1_RI_1
|
||||
#define GPIO_UART1_RTS GPIO_UART1_RTS_1
|
||||
|
||||
/* UART2 -- Not connected */
|
||||
|
||||
#define GPIO_UART2_TXD GPIO_UART2_TXD_1
|
||||
#define GPIO_UART2_RXD GPIO_UART2_RXD_1
|
||||
|
||||
/* UART3 -- Not connected */
|
||||
|
||||
#define GPIO_UART3_TXD GPIO_UART3_TXD_1
|
||||
#define GPIO_UART3_RXD GPIO_UART3_RXD_1
|
||||
|
||||
/* Either SPI or SSP0 can drive the MMC/SD slot (SSP0 alternate pin settings are
|
||||
* not connected)
|
||||
*/
|
||||
|
||||
#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
|
||||
#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1
|
||||
#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1
|
||||
#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1
|
||||
|
||||
/* SSP1 */
|
||||
|
||||
#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
|
|
|||
Loading…
Reference in New Issue