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STM32 SDIO DMA should only 16-bits wide when DMA-ing to/from FSMC SRAM 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5082 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2012-09-04 02:47:46 +00:00
parent 7e480a254c
commit 70e33698c5
5 changed files with 74 additions and 6 deletions
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2
nuttx/ChangeLog
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@ -3252,3 +3252,5 @@
compilation errors (reported by Diego Sanchez).
* include/nuttx/wqueue.h, sched/work*, and others: Added logic to support
a second, lower priority work queue (CONFIG_SCHED_LPWORK).
* arch/arm/src/stm32/stm32_dma.c, chip/stm32*_memorymap.h: FSMC SRAM is
only 16-bits wide and the SDIO DMA must be set up differently.

11
nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
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@ -47,6 +47,9 @@
#define STM32_SRAMBB_BASE 0x22000000
#define STM32_PERIPH_BASE 0x40000000
#define STM32_REGION_MASK 0x0fffffff
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
/* Register Base Address ************************************************************/
/* APB1 bus */
@ -123,7 +126,13 @@
/* Flexible SRAM controller (FSMC) */
#define STM32_FSMC_BASE 0xa0000000
#define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
#define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
#define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range

10
nuttx/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
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@ -46,11 +46,19 @@
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0x0fffffff
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
/* Code Base Addresses **************************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
@ -185,7 +193,7 @@
#define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */
#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */
/* Cortex-M4 Base Addresses *********************************************************/
/* Cortex-M3 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range
*/

8
nuttx/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
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@ -46,11 +46,19 @@
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0x0fffffff
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
/* Code Base Addresses **************************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */

49
nuttx/arch/arm/src/stm32/stm32_sdio.c
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@ -185,8 +185,12 @@
#if defined(CONFIG_STM32_STM32F10XX)
# define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
# define SDIO_RXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
# define SDIO_TXDMA16_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_16BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
/* STM32 F4 stream configuration register (SCR) settings. */
@ -195,10 +199,18 @@
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_RXDMA16_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_16BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
# define SDIO_TXDMA16_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_16BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
DMA_SCR_MBURST_INCR4)
#else
# error "Unknown STM32 DMA"
#endif
@ -2502,8 +2514,22 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
stm32_configxfrints(priv, SDIO_DMARECV_MASK);
putreg32(1, SDIO_DCTRL_DMAEN_BB);
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
/* On-chip SRAM is 32-bits wide. FSMC SRAM is 16-bits wide */
#ifdef CONFIG_STM32_FSMC
if (STM32_IS_EXTSRAM(buffer))
{
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 1) >> 1, SDIO_RXDMA16_CONFIG);
}
else
#endif
{
DEBUGASSERT(STM32_IS_SRAM(buffer));
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
}
/* Start the DMA */
@ -2512,6 +2538,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
stm32_sample(priv, SAMPLENDX_AFTER_SETUP);
ret = OK;
}
return ret;
}
#endif
@ -2570,8 +2597,21 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Configure the TX DMA */
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_TXDMA32_CONFIG);
/* On-chip SRAM is 32-bits wide. FSMC SRAM is 16-bits wide */
#ifdef CONFIG_STM32_FSMC
if (STM32_IS_EXTSRAM(buffer))
{
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 1) >> 1, SDIO_TXDMA16_CONFIG);
}
else
#endif
{
DEBUGASSERT(STM32_IS_SRAM(buffer));
stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
(buflen + 3) >> 2, SDIO_TXDMA32_CONFIG);
}
stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE);
putreg32(1, SDIO_DCTRL_DMAEN_BB);
@ -2587,6 +2627,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
ret = OK;
}
return ret;
}
#endif