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Need to set UART interrupt priority 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1854 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2009-06-06 01:54:11 +00:00
parent 9f0db2be27
commit 69e9eacf38
9 changed files with 61 additions and 23 deletions
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1
nuttx/arch/arm/src/str71x/str71x_eic.h
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@ -157,7 +157,6 @@
#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */
#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */
/************************************************************************************
* Public Types
************************************************************************************/

4
nuttx/arch/arm/src/str71x/str71x_head.S
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@ -319,6 +319,10 @@ eicloop:
/* Shift the IRQ number to bits 16-31 and save the shifted IRQ
* number as SIR[irqno]. This will appear as bits 0:15 in the
* IVR during IRQ processing.
*
* NOTE that the initial priority is set to zero -- the current
* interrupt priority (CIP) is always zero, so these interrupts
* are all disabled.
*/
mov \value, \irqno, lsl #16

34
nuttx/arch/arm/src/str71x/str71x_irq.c
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@ -75,19 +75,19 @@ uint32 *current_regs;
void up_irqinitialize(void)
{
/* The bulk of IRQ initialization if performed in str71x_head.S, so we
* have very little to do here:
*/
/* Enable IRQs (but not FIQs -- they aren't used) */
putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR);
/* Currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Enable interrupts */
/* The bulk of IRQ initialization if performed in str71x_head.S, so we
* have very little to do here -- basically just enabling interrupts;
*
* Enable IRQs (but not FIQs -- they aren't used)
*/
putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR);
/* Enable global ARM interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(SVC_MODE | PSR_F_BIT);
@ -130,6 +130,13 @@ void up_enable_irq(int irq)
if ((unsigned)irq < NR_IRQS)
{
/* Check the IRQs priority. the current interrupt priority (CIP) is
* always zero so the priority must be at least one for the IRQ to be
* truly enabled.
*/
DEBUGASSERT(getreg32(STR71X_EIC_SIR(irq)) & STR71X_EICSIR_SIPLMASK != 0);
/* Enable the IRQ by setting the associated bit in the IER register */
reg32 = getreg32(STR71X_EIC_IER);
@ -165,7 +172,6 @@ void up_maskack_irq(int irq)
reg32 = getreg32(STR71X_EIC_IPR);
reg32 |= (1 << irq);
putreg32(reg32, STR71X_EIC_IPR);
}
}
@ -182,11 +188,15 @@ int up_prioritize_irq(int irq, int priority)
uint32 addr;
uint32 reg32;
if ((unsigned)irq < NR_IRQS && priority < 16)
/* The current interrupt priority (CIP) is always zero, so a minimum prioriy
* of one is enforced to prevent disabling the interrupt.
*/
if ((unsigned)irq < NR_IRQS && priority > 0 && priority < 16)
{
addr = STR71X_EIC_SIR(irq);
reg32 = getreg32(addr);
reg32 &= STR71X_EICSIR_SIPLMASK;
reg32 &= ~STR71X_EICSIR_SIPLMASK;
reg32 |= priority;
putreg32(reg32, addr);
return OK;

19
nuttx/arch/arm/src/str71x/str71x_serial.c
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@ -77,6 +77,12 @@
# undef HAVE_CONSOLE
#endif
#ifndef CONFIG_UART_PRI
# define CONFIG_UART_PRI 1
#elif CONFIG_UART_PRI <= 1 && CONFIG_UART_PRI >15
# error "CONFIG_UART_PRI is out of range"
#endif
/* If we are not using the serial driver for the console, then we
* still must provide some minimal implementation of up_putc().
*/
@ -580,6 +586,10 @@ static int up_attach(struct uart_dev_s *dev)
*/
up_enable_irq(priv->irq);
/* Set the uart interrupt priority (the default value is one) */
up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
}
return ret;
}
@ -668,7 +678,8 @@ static int up_interrupt(int irq, void *context)
/* Handle incoming, receive bytes (with or without timeout) */
if ((priv->sr & STR71X_UARTSR_RNE) != 0)
if ((priv->sr & STR71X_UARTSR_RNE) != 0 && /* Rx FIFO not empty */
(priv->ier & STR71X_UARTIER_RHF) != 0) /* Rx FIFO half full int enabled */
{
/* Rx buffer not empty ... process incoming bytes */
@ -678,7 +689,8 @@ static int up_interrupt(int irq, void *context)
/* Handle outgoing, transmit bytes */
if ((priv->sr & STR71X_UARTSR_TF) == 0)
if ((priv->sr & STR71X_UARTSR_TF) == 0 && /* Tx FIFO not full */
(priv->ier & STR71X_UARTIER_THE) != 0) /* Tx Half empty interrupt enabled */
{
/* Tx FIFO not full ... process outgoing bytes */
@ -686,7 +698,8 @@ static int up_interrupt(int irq, void *context)
handled = TRUE;
}
}
return OK;
return OK;
}
/****************************************************************************

12
nuttx/arch/arm/src/str71x/str71x_timerisr.c
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@ -55,6 +55,14 @@
* Definitions
****************************************************************************/
/* Configuration */
#ifndef CONFIG_TIM_PRI
# define CONFIG_TIM_PRI 1
#elif CONFIG_TIM_PRI <= 1 && CONFIG_TIM_PRI >15
# error "CONFIG_TIM_PRI is out of range"
#endif
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
@ -189,9 +197,9 @@ void up_timerinit(void)
putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
putreg16(0xfffc, STR71X_TIMER0_CNTR);
/* Set the IRQ interrupt priority */
/* Set the timer interrupt priority */
up_prioritize_irq(STR71X_IRQ_SYSTIMER, 1);
up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI);
/* Attach the timer interrupt vector */

2
nuttx/arch/arm/src/str71x/str71x_uart.h
View File

@ -161,7 +161,7 @@
#define STR71X_UARTSR_PERR (0x0008) /* Bit 3: Parity error */
#define STR71X_UARTSR_FRERROR (0x0010) /* Bit 4: Frame error */
#define STR71X_UARTSR_OVERRUN (0x0020) /* Bit 5: Overrun error */
#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/
#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty */
#define STR71X_UARTSR_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */
#define STR71X_UARTSR_RHF (0x0100) /* Bit 8: Rx half full */
#define STR71X_UARTSR_TF (0x0200) /* Bit 9: Tx full */

2
nuttx/configs/olimex-strp711/README.txt
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@ -178,6 +178,8 @@ STR71x-Specific Configuration Settings
CONFIG_STR71X_CKOUT, CONFIG_STR71X_TIM1, CONFIG_STR71X_TIM2, CONFIG_STR71X_TIM3, and
CONFIG_STR71X_RTC
Select peripherals to initialize (Timer0 and EIC are always initialized)
CONFIG_UART_PRI, STR71X_BSPI_PRI, CONFIG_TIM_PRI
Can be defined to set the priority of NuttX managed devices. Default is 1.
CONFIG_STR71X_BANK0, CONFIG_STR71X_BANK1, CONFIG_STR71X_BANK2, and CONFIG_STR71X_BANK3
Enable initialize of external memory banks 0-3.
CONFIG_STR71X_BANK0_SIZE, CONFIG_STR71X_BANK1_SIZE, CONFIG_STR71X_BANK2_SIZE, and

8
nuttx/sched/irq_unexpectedisr.c
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@ -1,7 +1,7 @@
/****************************************************************************
* sched/irq_unexpectedisr.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -39,6 +39,7 @@
#include <sys/types.h>
#include <nuttx/irq.h>
#include <debug.h>
#include "os_internal.h"
#include "irq_internal.h"
@ -78,6 +79,7 @@
int irq_unexpected_isr(int irq, FAR void *context)
{
(void)irqsave();
PANIC(OSERR_UNEXPECTEDISR);
return 0;
lldbg("irq: %d\n", irq);
PANIC(OSERR_UNEXPECTEDISR);
return OK; /* Won't get here */
}

2
nuttx/sched/os_start.c
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@ -1,7 +1,7 @@
/****************************************************************************
* sched/os_start.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without