MAC driver development
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1809 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
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@ -42,6 +42,7 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/mii.h>
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/************************************************************************************
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* Definitions
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@ -66,8 +67,11 @@
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#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
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#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
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#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
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#ifndef CONFIG_ARCH_CHIP_LM3S6918
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# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
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#endif
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/* MII Management Registers (see include/nuttx/mii.h) */
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/* MII Management Register Offsets (see include/nuttx/mii.h) */
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/* Ethernet Controller Register Addresses *******************************************/
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@ -86,6 +90,25 @@
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#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
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#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
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#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
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#ifndef CONFIG_ARCH_CHIP_LM3S6918
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# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
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#endif
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/* Memory Mapped MII Management Registers */
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#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR)
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#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR)
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#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1)
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#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2)
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#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE)
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#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA)
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#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION)
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#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
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#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
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#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
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#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
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#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
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#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
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/* Ethernet Controller Register Bit Definitions *************************************/
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@ -115,13 +115,31 @@
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#ifndef __ASSEMBLY__
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/* All LM3S architectures must provide the following entry point. This entry point
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* is called early in the intitialization -- after all memory has been configured
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* and mapped but before any devices have been initialized.
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*/
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/************************************************************************************
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* Name: lm3s_boardinitialize
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*
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* Description:
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* All LM3S architectures must provide the following entry point. This entry point
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* is called early in the intitialization -- after all memory has been configured
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* and mapped but before any devices have been initialized.
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*
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************************************************************************************/
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extern void lm3s_boardinitialize(void);
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/************************************************************************************
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* Name: lm3s_ethernetmac
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*
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* Description:
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* For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile
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* USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function
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* will obtain the MAC address from these registers.
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*
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************************************************************************************/
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#ifdef CONFIG_LM3S_BOARDMAC
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extern void lm3s_ethernetmac(struct ether_addr *ethaddr);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_BOARD_BOARD_H */
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@ -55,177 +55,262 @@
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* detailed in Section 22.2.4 of the IEEE 802.3 specification.
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*/
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#define MII_MCR 0x00 /* MII management control */
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#define MII_MSR 0x01 /* MII management status */
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#define MII_PHYID1 0x02 /* PHY ID 1 */
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#define MII_PHYID2 0x03 /* PHY ID 2 */
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#define MII_ADVERTISE 0x04 /* Auto-negotiation advertisement */
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#define MII_LPA 0x05 /* Auto-negotiation link partner base page ability */
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#define MII_EXPANSION 0x06 /* Auto-negotiation expansion */
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#define MII_NEXTPAGE 0x07 /* Auto-negotiation next page */
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#define MII_LPANEXTPAGE 0x08 /* Auto-negotiation link partner received next page */
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#define MII_MSCONTROL 0x09 /* Master/slave control register */
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#define MII_MSSTATUS 0x0a /* Master/slave status register */
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#define MII_PSECONTROL 0x0b /* PSE control register */
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#define MII_PSESTATUS 0x0c /* PSE status register */
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#define MII_MMDCONTROL 0x0d /* MMD access control register */
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#define MII_ESTATUS 0x0f /* Extended status register */
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#define MII_MCR 0x00 /* MII management control */
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#define MII_MSR 0x01 /* MII management status */
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#define MII_PHYID1 0x02 /* PHY ID 1 */
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#define MII_PHYID2 0x03 /* PHY ID 2 */
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#define MII_ADVERTISE 0x04 /* Auto-negotiation advertisement */
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#define MII_LPA 0x05 /* Auto-negotiation link partner base page ability */
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#define MII_EXPANSION 0x06 /* Auto-negotiation expansion */
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#define MII_NEXTPAGE 0x07 /* Auto-negotiation next page */
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#define MII_LPANEXTPAGE 0x08 /* Auto-negotiation link partner received next page */
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#define MII_MSCONTROL 0x09 /* Master/slave control register */
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#define MII_MSSTATUS 0x0a /* Master/slave status register */
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#define MII_PSECONTROL 0x0b /* PSE control register */
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#define MII_PSESTATUS 0x0c /* PSE status register */
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#define MII_MMDCONTROL 0x0d /* MMD access control register */
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#define MII_ESTATUS 0x0f /* Extended status register */
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/* Registers 16-31 may be used for vendor specific abilities */
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/* DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */
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#define MII_DP83840_COUNTER 0x12 /* Disconnect counter */
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#define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */
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#define MII_DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_DP83840_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_DP83840_SREVISION 0x16 /* Silicon revision */
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#define MII_DP83840_LBRERROR 0x18 /* Loopback, bypass and receiver error */
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#define MII_DP83840_PHYADDR 0x19 /* PHY address */
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#define MII_DP83840_10BTSR 0x1b /* 10BASE-T status register */
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#define MII_DP83840_10BTCR 0x1c /* 10BASE-T configuration register */
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#define MII_DP83840_COUNTER 0x12 /* Disconnect counter */
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#define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */
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#define MII_DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_DP83840_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_DP83840_SREVISION 0x16 /* Silicon revision */
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#define MII_DP83840_LBRERROR 0x18 /* Loopback, bypass and receiver error */
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#define MII_DP83840_PHYADDR 0x19 /* PHY address */
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#define MII_DP83840_10BTSR 0x1b /* 10BASE-T status register */
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#define MII_DP83840_10BTCR 0x1c /* 10BASE-T configuration register */
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/* Am79c874: 0x08-0x0f, 0x14, 0x16, 0x19-0x1f reserved */
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#define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */
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#define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */
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#define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */
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#define MII_AM79C874_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_AM79C874_LOOPBACK 0x13 /* Power management/loopback */
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#define MII_AM79C874_MODEC 0x15 /* Mode control register */
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#define MII_AM79C874_DISCONNECT 0x17 /* Disconnect counter */
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#define MII_AM79C874_RCVERROR 0x18 /* Receive error counter */
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#define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */
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#define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */
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#define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */
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#define MII_AM79C874_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_AM79C874_LOOPBACK 0x13 /* Power management/loopback */
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#define MII_AM79C874_MODEC 0x15 /* Mode control register */
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#define MII_AM79C874_DISCONNECT 0x17 /* Disconnect counter */
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#define MII_AM79C874_RCVERROR 0x18 /* Receive error counter */
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/* Luminary LM3S6918 built-in PHY */
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/* Luminary LM3S6918 built-in PHY, 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */
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#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */
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#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */
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#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */
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#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */
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#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
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#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */
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#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */
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#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */
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#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */
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#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
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/* */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_NCONFIG 0x1c /* Network interface config */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* MII register bit settings ************************************************/
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/* MII Control register bit definitions */
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#define MII_MCR_SPEED1000 0x0040 /* Bit 6: MSB of Speed (1000 reserved on 10/100) */
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#define MII_MCR_CTST 0x0080 /* Bit 7: Enable collision test */
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#define MII_MCR_FULLDPLX 0x0100 /* Bit 8: Full duplex */
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#define MII_MCR_ANRESTART 0x0200 /* Bit 9: Restart auto negotiation */
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#define MII_MCR_ISOLATE 0x0400 /* Bit 10: Electronically isolate PHY from MII */
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#define MII_MCR_PDOWN 0x0800 /* Bit 11: Powerdown the PHY */
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#define MII_MCR_ANENABLE 0x1000 /* Bit 12: Enable auto negotiation */
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#define MII_MCR_SPEED100 0x2000 /* Bit 13: Select 100Mbps */
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#define MII_MCR_LOOPBACK 0x4000 /* Bit 14: Enable loopback mode */
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#define MII_MCR_RESET 0x8000 /* Bit 15: PHY reset */
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#define MII_MCR_SPEED1000 (1 << 6) /* Bit 6: MSB of Speed (1000 reserved on 10/100) */
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#define MII_MCR_CTST (1 << 7) /* Bit 7: Enable collision test */
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#define MII_MCR_FULLDPLX (1 << 8) /* Bit 8: Full duplex */
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#define MII_MCR_ANRESTART (1 << 9) /* Bit 9: Restart auto negotiation */
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#define MII_MCR_ISOLATE (1 << 10) /* Bit 10: Electronically isolate PHY from MII */
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#define MII_MCR_PDOWN (1 << 11) /* Bit 11: Powerdown the PHY */
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#define MII_MCR_ANENABLE (1 << 12) /* Bit 12: Enable auto negotiation */
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#define MII_MCR_SPEED100 (1 << 13) /* Bit 13: Select 100Mbps */
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#define MII_MCR_LOOPBACK (1 << 14) /* Bit 14: Enable loopback mode */
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#define MII_MCR_RESET (1 << 15) /* Bit 15: PHY reset */
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/* MII Status register bit definitions */
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#define MII_MSR_EXTCAP 0x0001 /* Bit 0: Extended register capability */
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#define MII_MSR_JABBERDETECT 0x0002 /* Bit 1: Jabber detect */
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#define MII_MSR_LINKSTATUS 0x0004 /* Bit 2: Link status */
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#define MII_MSR_ANEGABLE 0x0008 /* Bit 3: Auto-negotiation able */
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#define MII_MSR_RFAULT 0x0010 /* Bit 4: Remote fault */
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#define MII_MSR_ANEGCOMPLETE 0x0020 /* Bit 5: Auto-negotiation complete */
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#define MII_MSR_MFRAMESUPPRESS 0x0040 /* Bit 6: Management frame suppression */
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#define MII_MSR_ESTATEN 0x0100 /* Bit 8: Extended Status in R15 */
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#define MII_MSR_100BASET2FULL 0x0200 /* Bit 9: 100BASE-T2 half duplex able */
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#define MII_MSR_100BASET2HALF 0x0400 /* Bit 10: 100BASE-T2 full duplex able */
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#define MII_MSR_10BASETXHALF 0x0800 /* Bit 11: 10BASE-TX half duplex able */
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#define MII_MSR_10BASETXFULL 0x1000 /* Bit 12: 10BASE-TX full duplex able */
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#define MII_MSR_100BASETXHALF 0x2000 /* Bit 13: 100BASE-TX half duplex able */
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#define MII_MSR_100BASETXFULL 0x4000 /* Bit 14: 100BASE-TX full duplex able */
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#define MII_MSR_100BASET4 0x8000 /* Bit 15: 100BASE-T4 able */
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#define MII_MSR_EXTCAP (1 << 0) /* Bit 0: Extended register capability */
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#define MII_MSR_JABBERDETECT (1 << 1) /* Bit 1: Jabber detect */
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#define MII_MSR_LINKSTATUS (1 << 2) /* Bit 2: Link status */
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#define MII_MSR_ANEGABLE (1 << 3) /* Bit 3: Auto-negotiation able */
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#define MII_MSR_RFAULT (1 << 4) /* Bit 4: Remote fault */
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#define MII_MSR_ANEGCOMPLETE (1 << 5) /* Bit 5: Auto-negotiation complete */
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#define MII_MSR_MFRAMESUPPRESS (1 << 6) /* Bit 6: Management frame suppression */
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#define MII_MSR_ESTATEN (1 << 8) /* Bit 8: Extended Status in R15 */
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#define MII_MSR_100BASET2FULL (1 << 9) /* Bit 9: 100BASE-T2 half duplex able */
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#define MII_MSR_100BASET2HALF (1 << 10) /* Bit 10: 100BASE-T2 full duplex able */
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#define MII_MSR_10BASETXHALF (1 << 11) /* Bit 11: 10BASE-TX half duplex able */
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#define MII_MSR_10BASETXFULL (1 << 12) /* Bit 12: 10BASE-TX full duplex able */
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#define MII_MSR_100BASETXHALF (1 << 13) /* Bit 13: 100BASE-TX half duplex able */
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#define MII_MSR_100BASETXFULL (1 << 14) /* Bit 14: 100BASE-TX full duplex able */
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#define MII_MSR_100BASET4 (1 << 15) /* Bit 15: 100BASE-T4 able */
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/* MII ID2 register bits */
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#define MII_PHYID2_OUI 0xfc00 /* Bits 19-24 of OUI mask */
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#define MII_PHYID2_MODEL 0x03f0 /* Model number mask */
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#define MII_PHYID2_REV 0x000f /* Revision number mask */
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#define MII_PHYID2_OUI 0xfc00 /* Bits 19-24 of OUI mask */
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#define MII_PHYID2_MODEL 0x03f0 /* Model number mask */
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#define MII_PHYID2_REV 0x000f /* Revision number mask */
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#define MII_PHYID1_AM79C874 0x0022 /* ID1 value for Am79c874 */
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#define MII_PHYID2_AM79C874 0x561b /* ID2 value for Am79c874 Rev B */
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#define MII_PHYID1_AM79C874 0x0022 /* ID1 value for Am79c874 */
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#define MII_PHYID2_AM79C874 0x561b /* ID2 value for Am79c874 Rev B */
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/* Advertisement control register bit definitions */
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#define MII_ADVERTISE_SELECT 0x001f /* Bits 0-4: Selector field */
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#define MII_ADVERTISE_CSMA 0x0001 /* CSMA */
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#define MII_ADVERTISE_10BASETXHALF 0x0020 /* Bit 5: Try 10BASE-TX half duplex */
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#define MII_ADVERTISE_1000XFULL 0x0020 /* Bit 5: Try 1000BASE-X full duplex */
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#define MII_ADVERTISE_10BASETXFULL 0x0040 /* Bit 6: Try 10BASE-TX full duplex */
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#define MII_ADVERTISE_1000XHALF 0x0040 /* Bit 6: Try 1000BASE-X half duplex */
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#define MII_ADVERTISE_100BASETXHALF 0x0080 /* Bit 7: Try 100BASE-TX half duplex */
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#define MII_ADVERTISE_1000XPAUSE 0x0080 /* Bit 7: Try 1000BASE-X pause */
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#define MII_ADVERTISE_100BASETXFULL 0x0100 /* Bit 8: Try 100BASE-TX full duplex*/
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#define MII_ADVERTISE_1000XASYMPAU 0x0100 /* Bit 8: Try 1000BASE-X asym pause */
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#define MII_ADVERTISE_100BASET4 0x0200 /* Bit 9: Try 100BASE-T4 */
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#define MII_ADVERTISE_FDXPAUSE 0x0400 /* Bit 10: Try full duplex flow control */
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#define MII_ADVERTISE_ASYMPAUSE 0x0800 /* Bit 11: Try asymetric pause */
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#define MII_ADVERTISE_RFAULT 0x2000 /* Bit 13: Remote fault supported */
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#define MII_ADVERTISE_LPACK 0x4000 /* Bit 14: Ack link partners response */
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#define MII_ADVERTISE_NXTPAGE 0x8000 /* Bit 15: Next page enabled */
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#define MII_ADVERTISE_SELECT 0x001f /* Bits 0-4: Selector field */
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#define MII_ADVERTISE_CSMA (1 << 0) /* CSMA */
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#define MII_ADVERTISE_8023 (1 << 0) /* IEEE Std 802.3 */
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#define MII_ADVERTISE_8029 (2 << 0) /* IEEE Std 802.9 ISLAN-16T */
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#define MII_ADVERTISE_8025 (3 << 0) /* IEEE Std 802.5 */
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#define MII_ADVERTISE_1394 (4 << 0) /* IEEE Std 1394 */
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#define MII_ADVERTISE_10BASETXHALF (1 << 5) /* Bit 5: Try 10BASE-TX half duplex */
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#define MII_ADVERTISE_1000XFULL (1 << 5) /* Bit 5: Try 1000BASE-X full duplex */
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#define MII_ADVERTISE_10BASETXFULL (1 << 6) /* Bit 6: Try 10BASE-TX full duplex */
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#define MII_ADVERTISE_1000XHALF (1 << 6) /* Bit 6: Try 1000BASE-X half duplex */
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#define MII_ADVERTISE_100BASETXHALF (1 << 7) /* Bit 7: Try 100BASE-TX half duplex */
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#define MII_ADVERTISE_1000XPAUSE (1 << 7) /* Bit 7: Try 1000BASE-X pause */
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#define MII_ADVERTISE_100BASETXFULL (1 << 8) /* Bit 8: Try 100BASE-TX full duplex*/
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#define MII_ADVERTISE_1000XASYMPAU (1 << 8) /* Bit 8: Try 1000BASE-X asym pause */
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#define MII_ADVERTISE_100BASET4 (1 << 9) /* Bit 9: Try 100BASE-T4 */
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#define MII_ADVERTISE_FDXPAUSE (1 << 10) /* Bit 10: Try full duplex flow control */
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#define MII_ADVERTISE_ASYMPAUSE (1 << 11) /* Bit 11: Try asymetric pause */
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#define MII_ADVERTISE_RFAULT (1 << 13) /* Bit 13: Remote fault supported */
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#define MII_ADVERTISE_LPACK (1 << 14) /* Bit 14: Ack link partners response */
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#define MII_ADVERTISE_NXTPAGE (1 << 15) /* Bit 15: Next page enabled */
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/* Link partner ability register bit definitions */
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|
||||
#define MII_LPA_SELECT 0x001f /* Bits 0-4: Link partner selector field */
|
||||
#define MII_LPA_10BASETXHALF 0x0020 /* Bit 5: 10BASE-TX half duplex able */
|
||||
#define MII_LPA_1000XFULL 0x0020 /* Bit 5: 1000BASE-X full-duplex able */
|
||||
#define MII_LPA_10BASETXFULL 0x0040 /* Bit 6: 10BASE-TX full duplex able */
|
||||
#define MII_LPA_1000XHALF 0x0040 /* Bit 6: 1000BASE-X half-duplex */
|
||||
#define MII_LPA_100BASETXHALF 0x0080 /* Bit 7: 100BASE-TX half duplex able */
|
||||
#define MII_LPA_1000XPAUSE 0x0080 /* Bit 7: 1000BASE-X pause able */
|
||||
#define MII_LPA_100BASETXFULL 0x0100 /* Bit 8: 100BASE-TX full duplex able */
|
||||
#define MII_LPA_1000XASYMPAU 0x0100 /* Bit 8: 1000BASE-X asym pause able */
|
||||
#define MII_LPA_100BASET4 0x0200 /* Bit 9: 100BASE-T4 able */
|
||||
#define MII_LPA_FDXPAUSE 0x0400 /* Bit 10: Full duplex flow control able */
|
||||
#define MII_LPA_ASYMPAUSE 0x0800 /* Bit 11: Asynchronous pause able */
|
||||
#define MII_LPA_RFAULT 0x2000 /* Bit 13: Link partner remote fault request */
|
||||
#define MII_LPA_LPACK 0x4000 /* Bit 14: Link partner acknowledgement */
|
||||
#define MII_LPA_NXTPAGE 0x8000 /* Bit 15: Next page requested */
|
||||
#define MII_LPA_SELECT 0x001f /* Bits 0-4: Link partner selector field */
|
||||
#define MII_LPA_CSMA (1 << 0) /* CSMA */
|
||||
#define MII_LPA_8023 (1 << 0) /* IEEE Std 802.3 */
|
||||
#define MII_LPA_8029 (2 << 0) /* IEEE Std 802.9 ISLAN-16T */
|
||||
#define MII_LPA_8025 (3 << 0) /* IEEE Std 802.5 */
|
||||
#define MII_LPA_1394 (4 << 0) /* IEEE Std 1394 */
|
||||
#define MII_LPA_10BASETXHALF (1 << 5) /* Bit 5: 10BASE-TX half duplex able */
|
||||
#define MII_LPA_1000XFULL (1 << 5) /* Bit 5: 1000BASE-X full-duplex able */
|
||||
#define MII_LPA_10BASETXFULL (1 << 6) /* Bit 6: 10BASE-TX full duplex able */
|
||||
#define MII_LPA_1000XHALF (1 << 6) /* Bit 6: 1000BASE-X half-duplex */
|
||||
#define MII_LPA_100BASETXHALF (1 << 7) /* Bit 7: 100BASE-TX half duplex able */
|
||||
#define MII_LPA_1000XPAUSE (1 << 7) /* Bit 7: 1000BASE-X pause able */
|
||||
#define MII_LPA_100BASETXFULL (1 << 8) /* Bit 8: 100BASE-TX full duplex able */
|
||||
#define MII_LPA_1000XASYMPAU (1 << 8) /* Bit 8: 1000BASE-X asym pause able */
|
||||
#define MII_LPA_100BASET4 (1 << 9) /* Bit 9: 100BASE-T4 able */
|
||||
#define MII_LPA_FDXPAUSE (1 << 10) /* Bit 10: Full duplex flow control able */
|
||||
#define MII_LPA_ASYMPAUSE (1 << 11) /* Bit 11: Asynchronous pause able */
|
||||
#define MII_LPA_RFAULT (1 << 13) /* Bit 13: Link partner remote fault request */
|
||||
#define MII_LPA_LPACK (1 << 14) /* Bit 14: Link partner acknowledgement */
|
||||
#define MII_LPA_NXTPAGE (1 << 15) /* Bit 15: Next page requested */
|
||||
|
||||
/* Link partner ability in next page format */
|
||||
|
||||
#define MII_LPANP_MESSAGE 0x07ff /* Bits 0-10: Link partner's message code */
|
||||
#define MII_LPANP_TOGGLE 0x0800 /* Bit 11: Link partner toggle */
|
||||
#define MII_LPANP_LACK2 0x1000 /* Bit 12: Link partner can comply ACK */
|
||||
#define MII_LPANP_MSGPAGE 0x2000 /* Bit 13: Link partner message page request */
|
||||
#define MII_LPANP_LPACK 0x4000 /* Bit 14: Link partner acknowledgement */
|
||||
#define MII_LPANP_NXTPAGE 0x8000 /* Bit 15: Next page requested */
|
||||
#define MII_LPANP_MESSAGE 0x07ff /* Bits 0-10: Link partner's message code */
|
||||
#define MII_LPANP_TOGGLE (1 << 11) /* Bit 11: Link partner toggle */
|
||||
#define MII_LPANP_LACK2 (1 << 12) /* Bit 12: Link partner can comply ACK */
|
||||
#define MII_LPANP_MSGPAGE (1 << 13) /* Bit 13: Link partner message page request */
|
||||
#define MII_LPANP_LPACK (1 << 14) /* Bit 14: Link partner acknowledgement */
|
||||
#define MII_LPANP_NXTPAGE (1 << 15) /* Bit 15: Next page requested */
|
||||
|
||||
/* MII Auto-negotiation expansion register bit definitions */
|
||||
|
||||
#define MII_EXPANSION_ANEGABLE 0x0001 /* Bit 0: Link partner is auto-negotion able */
|
||||
#define MII_EXPANSION_PAGERECVD 0x0002 /* Bit 1: New link code word in LPA ability reg */
|
||||
#define MII_EXPANSION_ENABLENPAGE 0x0004 /* Bit 2: This enables npage words */
|
||||
#define MII_EXPANSION_NXTPAGEABLE 0x0008 /* Bit 3: Link partner supports next page */
|
||||
#define MII_EXPANSION_PARFAULTS 0x0010 /* Bit 4: Fault detected by parallel logic */
|
||||
#define MII_EXPANSION_ANEGABLE (1 << 0) /* Bit 0: Link partner is auto-negotion able */
|
||||
#define MII_EXPANSION_PAGERECVD (1 << 1) /* Bit 1: New link code word in LPA ability reg */
|
||||
#define MII_EXPANSION_ENABLENPAGE (1 << 2) /* Bit 2: This enables npage words */
|
||||
#define MII_EXPANSION_NXTPAGEABLE (1 << 3) /* Bit 3: Link partner supports next page */
|
||||
#define MII_EXPANSION_PARFAULTS (1 << 4) /* Bit 4: Fault detected by parallel logic */
|
||||
|
||||
/* Auto-negotiation next page advertisement */
|
||||
|
||||
#define MII_NPADVERTISE_CODE 0x07ff /* Bits 0-10: message/un-formated code field */
|
||||
#define MII_NPADVERTISE_TOGGLE 0x0800 /* Bit 11: Toggle */
|
||||
#define MII_NPADVERTISE_ACK2 0x1000 /* Bit 12: Acknowledgement 2 */
|
||||
#define MII_NPADVERTISE_MSGPAGE 0x2000 /* Bit 13: Message page */
|
||||
#define MII_NPADVERTISE_NXTPAGE 0x8000 /* Bit 15: Next page indication */
|
||||
#define MII_NPADVERTISE_CODE 0x07ff /* Bits 0-10: message/un-formated code field */
|
||||
#define MII_NPADVERTISE_TOGGLE (1 << 11) /* Bit 11: Toggle */
|
||||
#define MII_NPADVERTISE_ACK2 (1 << 12) /* Bit 12: Acknowledgement 2 */
|
||||
#define MII_NPADVERTISE_MSGPAGE (1 << 13) /* Bit 13: Message page */
|
||||
#define MII_NPADVERTISE_NXTPAGE (1 << 15) /* Bit 15: Next page indication */
|
||||
|
||||
/* MII PHYADDR register bit definitions */
|
||||
|
||||
#define MII_PHYADDR_DUPLEX 0x0080
|
||||
#define MII_PHYADDR_SPEED 0x0040
|
||||
#define DP83840_PHYADDR_DUPLEX (1 << 7)
|
||||
#define DP83840_PHYADDR_SPEED (1 << 6)
|
||||
|
||||
/* Am79c874 diagnostics register */
|
||||
|
||||
#define AM79C874_DIAG_RXLOCK 0x0100 /* Bit 8: 1=Rcv PLL locked on */
|
||||
#define AM79C874_DIAG_RXPASS 0x0200 /* Bit 9: 1=Operating in 100Base-X mode */
|
||||
#define AM79C874_DIAG_100MBPS 0x0400 /* Bit 10: 1=ANEG result is 100Mbps */
|
||||
#define AM79C874_DIAG_FULLDPLX 0x0800 /* Bit 11: 1=ANEG result is full duplex */
|
||||
#define AM79C874_DIAG_RXLOCK (1 << 8) /* Bit 8: 1=Rcv PLL locked on */
|
||||
#define AM79C874_DIAG_RXPASS (1 << 9) /* Bit 9: 1=Operating in 100Base-X mode */
|
||||
#define AM79C874_DIAG_100MBPS (1 << 10) /* Bit 10: 1=ANEG result is 100Mbps */
|
||||
#define AM79C874_DIAG_FULLDPLX (1 << 11) /* Bit 11: 1=ANEG result is full duplex */
|
||||
|
||||
/* LM3S6918 Vendor-Specific, address 0x10 */
|
||||
|
||||
#define LM3S_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/
|
||||
#define LM3S_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */
|
||||
#define LM3S_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */
|
||||
#define LM3S_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */
|
||||
#define LM3S_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */
|
||||
#define LM3S_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */
|
||||
#define LM3S_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */
|
||||
#define LM3S_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/
|
||||
#define LM3S_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/
|
||||
|
||||
/* LM3S6918 Interrupt Control/Status, address 0x11 */
|
||||
|
||||
#define LM3S_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */
|
||||
#define LM3S_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */
|
||||
#define LM3S_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */
|
||||
#define LM3S_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */
|
||||
#define LM3S_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */
|
||||
#define LM3S_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */
|
||||
#define LM3S_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */
|
||||
#define LM3S_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */
|
||||
#define LM3S_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */
|
||||
#define LM3S_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */
|
||||
#define LM3S_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
|
||||
#define LM3S_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
|
||||
#define LM3S_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
|
||||
#define LM3S_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */
|
||||
#define LM3S_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
|
||||
#define LM3S_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */
|
||||
|
||||
/* LM3S6918 Diagnostic, address 0x12 */
|
||||
|
||||
#define LM3S_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */
|
||||
#define LM3S_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */
|
||||
#define LM3S_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */
|
||||
#define LM3S_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */
|
||||
#define LM3S_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */
|
||||
|
||||
/* LM3S6918 Transceiver Control, address 0x13 */
|
||||
|
||||
#define LM3S_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */
|
||||
#define LM3S_XCVRCONTROL_TXO_MASK (3 << LM3S_XCVRCONTROL_TXO_SHIFT)
|
||||
#define LM3S_XCVRCONTROL_TXO_00DB (0 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_04DB (1 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_08DB (2 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_12DB (3 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
|
||||
|
||||
/* LED Configuration, address 0x17 */
|
||||
|
||||
#define LM3S_LEDCONFIG_LED0_SHIFT 0 /* Bits 3-0: LED0 Source */
|
||||
#define LM3S_LEDCONFIG_LED0_MASK (0x0f << LM3S_LEDCONFIG_LED0_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED0_LINKOK (0 << LM3S_LEDCONFIG_LED0_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED0_RXTX (1 << LM3S_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */
|
||||
#define LM3S_LEDCONFIG_LED0_100BASET (5 << LM3S_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM3S_LEDCONFIG_LED0_10BASET (6 << LM3S_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */
|
||||
#define LM3S_LEDCONFIG_LED0_FDUPLEX (7 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED0_OKRXTX (8 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED1_SHIFT 4 /* Bits 7-4: LED1 Source */
|
||||
#define LM3S_LEDCONFIG_LED1_MASK (0x0f << LM3S_LEDCONFIG_LED1_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED1_LINKOK (0 << LM3S_LEDCONFIG_LED1_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED1_RXTX (1 << LM3S_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */
|
||||
#define LM3S_LEDCONFIG_LED1_100BASET (5 << LM3S_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM3S_LEDCONFIG_LED1_10BASET (6 << LM3S_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */
|
||||
#define LM3S_LEDCONFIG_LED1_FDUPLEX (7 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED1_OKRXTX (8 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
|
||||
/* MDI/MDIX Control, address 0x18 */
|
||||
|
||||
#define LM3S_MDICONTROL_MDIXSD_SHIFT 0 /* Bits 3-0: Auto-Switching Seed */
|
||||
#define LM3S_MDICONTROL_MDIXSD_MASK (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT)
|
||||
#define LM3S_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */
|
||||
#define LM3S_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */
|
||||
#define LM3S_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */
|
||||
#define LM3S_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */
|
||||
|
||||
/****************************************************************************
|
||||
* Type Definitions
|
||||
|
|
|
|||
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Reference in New Issue