phone-side
/
nuttx-bb
9
0
Fork 0
Code Releases Activity

Add support for RAMTRON NVRAM devices 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3347 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2011-03-06 15:39:02 +00:00
parent f125a54038
commit 612a0c0cab
37 changed files with 1425 additions and 510 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
nuttx/ChangeLog
View File

@ -1528,3 +1528,5 @@
Uros Platise).
* drivers/mmcsd/mmcsd_sdio.c -- Correct a loop termination condition (also
reported by Uros Platise).
* drivers/mtd/ramtron.c - Driver for SPI-based RAMTRON NVRAM devices FM25V10
(and others). Contributed by Uros Platise.

6
nuttx/Documentation/NuttX.html
View File

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: March 5, 2011</p>
<p>Last Updated: March 6, 2011</p>
</td>
</tr>
</table>
@ -519,7 +519,7 @@
<td><br></td>
<td>
<p>
<li>Support for SPI-based FLASH devices.</li>
<li>Support for SPI-based FLASH and FRAM devices.</li>
</p>
</tr>
@ -2152,6 +2152,8 @@ nuttx-5.19 2011-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
Uros Platise).
* drivers/mmcsd/mmcsd_sdio.c -- Correct a loop termination condition (also
reported by Uros Platise).
* drivers/mtd/ramtron.c - Driver for SPI-based RAMTRON NVRAM devices FM25V10
(and others). Contributed by Uros Platise.
pascal-2.1 2011-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;

3
nuttx/Documentation/README.html
View File

@ -9,7 +9,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: March 5, 2010</p>
<p>Last Updated: March 6, 2010</p>
</td>
</tr>
</table>
@ -141,6 +141,7 @@
| | |- <a href="configs/us7032evb1/src/README.txt?view=log">src/README.txt</a>
| | `- <a href="configs/us7032evb1/README.txt?view=log"><b><i>README.txt</i></b></a>
| |- vsn/
| | |- <a href="configs/vsn/src/README.txt?view=log">src/README.txt</a>
| | `- <a href="configs/vsn/README.txt?view=log"><b><i>README.txt</i></b></a>
| |- xtrs/
| | |- <a href="configs/xtrs/include/README.txt?view=log">include/README.txt</a>

1
nuttx/README.txt
View File

@ -354,6 +354,7 @@ Below is a guide to the available README files in the NuttX source tree:
| | |- src/README.txt
| | `- README.txt
| |- vsn/
| | |- src/README.txt
| | `- README.txt
| |- xtrs/
| | |- include/README.txt

18
nuttx/arch/arm/src/stm32/chip.h
View File

@ -53,7 +53,7 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
# define STM32 NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */
@ -73,19 +73,19 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
# define STM32 NBTIM 0 /* No basic timers */
# define STM32 NBTIM 2 /* Two basic timers TIM6 and TIM7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NGPIO 112 /* GPIOA-G */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NGPIO 51 /* GPIOA-D */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)

2
nuttx/arch/arm/src/stm32/stm32_rcc.c
View File

@ -210,7 +210,7 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_SPI2EN;
#endif
#if CONFIG_STM32_SPI4
#if CONFIG_STM32_SPI3
/* SPI 3 clock enable */
regval |= RCC_APB1ENR_SPI3EN;

14
nuttx/arch/arm/src/stm32/stm32_sdio.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_sdio.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -1415,13 +1415,15 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
clckr = SDIO_CLKCR_MMCXFR;
break;
case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
clckr = SDIO_CLCKR_SDWIDEXFR;
break;
#endif
case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */
clckr = SDIO_CLCKR_SDXFR;
break;
case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
clckr = SDIO_CLCKR_SDWIDEXFR;
break;
};
/* Set the new clock frequency and make sure that the clock is enabled or
@ -2531,9 +2533,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
*/
stm32_configgpio(GPIO_SDIO_D0);
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
stm32_configgpio(GPIO_SDIO_D1);
stm32_configgpio(GPIO_SDIO_D2);
stm32_configgpio(GPIO_SDIO_D3);
#endif
stm32_configgpio(GPIO_SDIO_CK);
stm32_configgpio(GPIO_SDIO_CMD);

13
nuttx/arch/arm/src/stm32/stm32_spi.c
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arm/arm/src/stm32/stm32_spi.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -760,6 +760,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
uint16_t setbits;
uint32_t actual;
/* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */
if (frequency > STM32_SPI_CLK_MAX)
{
frequency = STM32_SPI_CLK_MAX;
}
/* Has the frequency changed? */
#ifndef CONFIG_SPI_OWNBUS
@ -1286,7 +1293,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
flags = irqsave();
#ifdef CONFIG_STM32_SPI1
if (port == 0)
if (port == 1)
{
uint32_t mapr;
@ -1317,7 +1324,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
else
#endif
#ifdef CONFIG_STM32_SPI2
if (port == 1)
if (port == 2)
{
/* Select SPI2 */

328
nuttx/arch/arm/src/stm32/stm32_spi.h
View File

@ -1,158 +1,170 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_spi.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H
#define __ARCH_ARM_STC_STM32_STM32_SPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ***************************************************************/
#if STM32_NSPI > 0
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
#if STM32_NSPI > 1
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */
/************************************************************************************
* arch/arm/src/stm32/stm32_spi.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_STM32_SPI_H
#define __ARCH_ARM_STC_STM32_STM32_SPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define STM32_SPI_CLK_MAX 18000000UL /* Maximum allowed speed as per specifications for all SPIs */
/* Register Offsets *****************************************************************/
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ***************************************************************/
#if STM32_NSPI > 0
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
#if STM32_NSPI > 1
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
#if STM32_NSPI > 2
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */

19
nuttx/arch/arm/src/stm32/stm32f103re_pinmap.h
View File

@ -284,17 +284,20 @@
/* SDIO */
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
# define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#endif
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
/************************************************************************************
* Public Types
************************************************************************************/

18
nuttx/arch/arm/src/stm32/stm32f103ze_pinmap.h
View File

@ -356,13 +356,17 @@
/* SDIO */
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
# define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#endif
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)

2
nuttx/configs/README.txt
View File

@ -530,6 +530,8 @@ defconfig -- This is a configuration file similar to the Linux
CONFIG_MMCSD_MMCSUPPORT - Enable support for MMC cards
CONFIG_MMCSD_HAVECARDDETECT - SDIO driver card detection is
100% accurate
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
4-bit transfer mode.
RiT P14201 OLED driver
CONFIG_LCD_P14201 - Enable P14201 support

2
nuttx/configs/stm3210e-eval/README.txt
View File

@ -400,6 +400,8 @@ STM3210E-EVAL-specific Configuration Options
CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128
CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
Default: Medium
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
4-bit transfer mode.
Configurations
^^^^^^^^^^^^^^

4
nuttx/configs/stm3210e-eval/src/up_nsh.c
View File

@ -148,8 +148,8 @@ int nsh_archinitialize(void)
#ifdef CONFIG_STM32_SPI1
/* Get the SPI port */
message("nsh_archinitialize: Initializing SPI port 0\n");
spi = up_spiinitialize(0);
message("nsh_archinitialize: Initializing SPI port 1\n");
spi = up_spiinitialize(1);
if (!spi)
{
message("nsh_archinitialize: Failed to initialize SPI port 0\n");

2
nuttx/configs/vsn/README.txt
View File

@ -399,6 +399,8 @@ VSN-specific Configuration Options
CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128
CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
Default: Medium
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
4-bit transfer mode.
Configurations
^^^^^^^^^^^^^^

54
nuttx/configs/vsn/include/board.h
View File

@ -55,6 +55,16 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* Board Configuration:
* - USART1, is the default bootloader and console
* - SPI1 is wired to expansion port
* - SPI2 is used for radio module
* - SPI3 has direct connection with FRAM
* - SDCard, conencts the microSD and shares the control lines with Sensor Interface
* to select Amplifier Gain
* - ...
*/
/* Clocking *************************************************************************/
@ -103,33 +113,44 @@
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
* to service FIFOs in interrupt driven mode.
*
* SDcard default speed has max SDIO_CK freq of 25 MHz (12.5 Mbps)
* After selection of high speed freq may be 50 MHz (25 Mbps)
* Recommended default voltage: 3.3 V
*
* \todo Not checked yet! Uros.
* HCLK=36MHz, SDIOCLK=? MHz, SDIO_CK=HCLK/(178+2)=400 KHz
* HCLK=36MHz, SDIOCLK=36 MHz, SDIO_CK=HCLK/(88+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
#define SDIO_INIT_CLKDIV (88 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: HCLK=36 MHz, SDIOCLK=36MHz, SDIO_CK=HCLK/(0+2)=18 MHz
* DMA OFF: HCLK=36 MHz, SDIOCLK=36MHz, SDIO_CK=HCLK/(1+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# ifndef CONFIG_DEBUG
# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# else
# define SDIO_MMCXFR_CLKDIV (10 << SDIO_CLKCR_CLKDIV_SHIFT)
# endif
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(0+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=12 MHz
* Extra slow down in debug mode to get rid of underruns.
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# ifndef CONFIG_DEBUG
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# else
# define SDIO_SDXFR_CLKDIV (10 << SDIO_CLKCR_CLKDIV_SHIFT)
# endif
#endif
/* LED definitions ******************************************************************/
@ -146,8 +167,6 @@
#define LED_PANIC 7 /* ... */
#define LED_IDLE 8 /* shows idle state */
/* eXternal connector pins */
/************************************************************************************
* Public Data
@ -197,6 +216,11 @@ EXTERN void up_buttoninit(void);
EXTERN uint8_t up_buttons(void);
#endif
/* Other peripherals startup routines, all returning OK on success */
EXTERN int up_sdcard(void);
EXTERN int up_ramtron(void);
#undef EXTERN
#if defined(__cplusplus)
}

26
nuttx/configs/vsn/nsh/defconfig
View File

@ -89,7 +89,7 @@ CONFIG_ARCH_BOOTLOADER=n
CONFIG_ARCH_LEDS=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CALIBRATION=n
CONFIG_ARCH_DMA=y
CONFIG_ARCH_DMA=n
#
# Identify toolchain and linker options
@ -105,7 +105,7 @@ CONFIG_STM32_DFU=n
# Individual subsystems can be enabled:
# AHB:
CONFIG_STM32_DMA1=n
CONFIG_STM32_DMA2=y
CONFIG_STM32_DMA2=n
CONFIG_STM32_CRC=n
CONFIG_STM32_FSMC=n
CONFIG_STM32_SDIO=y
@ -117,8 +117,8 @@ CONFIG_STM32_TIM5=n
CONFIG_STM32_TIM6=n
CONFIG_STM32_TIM7=n
CONFIG_STM32_WWDG=n
CONFIG_STM32_SPI2=n
CONFIG_STM32_SPI4=n
CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI3=y
CONFIG_STM32_USART2=n
CONFIG_STM32_USART3=n
CONFIG_STM32_UART4=n
@ -329,8 +329,9 @@ CONFIG_HAVE_LIBM=n
#
CONFIG_APP_DIR=examples/nsh
CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_VERBOSE=y
CONFIG_DEBUG_SYMBOLS=n
CONFIG_DEBUG_FS=y
CONFIG_MM_REGIONS=1
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
@ -465,7 +466,7 @@ CONFIG_PREALLOC_TIMERS=4
# CONFIG_FAT_SECTORSIZE - Max supported sector size
# CONFIG_FS_ROMFS - Enable ROMFS filesystem support
CONFIG_FS_FAT=y
CONFIG_FS_ROMFS=n
CONFIG_FS_ROMFS=y
#
# SPI-based MMC/SD driver
@ -477,8 +478,8 @@ CONFIG_FS_ROMFS=n
# CONFIG_MMCSD_SPICLOCK - Maximum SPI clock to drive MMC/SD card.
# Default is 20MHz.
#
CONFIG_MMCSD_NSLOTS=1
CONFIG_MMCSD_READONLY=n
CONFIG_MMCSD_NSLOTS=0
CONFIG_MMCSD_READONLY=y
CONFIG_MMCSD_SPICLOCK=12500000
#
@ -502,8 +503,9 @@ CONFIG_FS_WRITEBUFFER=n
# CONFIG_MMCSD_HAVECARDDETECT
# SDIO driver card detection is 100% accurate
#
CONFIG_SDIO_DMA=y
CONFIG_MMCSD_MMCSUPPORT=n
CONFIG_SDIO_DMA=n
CONFIG_SDIO_WIDTH_D1_ONLY=y # Added single width support
CONFIG_MMCSD_MMCSUPPORT=y
CONFIG_MMCSD_HAVECARDDETECT=n
#
@ -730,7 +732,7 @@ CONFIG_EXAMPLES_NSH_STACKSIZE=2048
CONFIG_EXAMPLES_NSH_NESTDEPTH=3
CONFIG_EXAMPLES_NSH_DISABLESCRIPT=n
CONFIG_EXAMPLES_NSH_DISABLEBG=n
CONFIG_EXAMPLES_NSH_ROMFSETC=n
CONFIG_EXAMPLES_NSH_ROMFSETC=y
CONFIG_EXAMPLES_NSH_CONSOLE=y
CONFIG_EXAMPLES_NSH_TELNET=n
CONFIG_EXAMPLES_NSH_ARCHINIT=y
@ -746,7 +748,7 @@ CONFIG_EXAMPLES_NSH_ROMFSDEVNO=0
CONFIG_EXAMPLES_NSH_ROMFSSECTSIZE=64
CONFIG_EXAMPLES_NSH_FATDEVNO=1
CONFIG_EXAMPLES_NSH_FATSECTSIZE=512
CONFIG_EXAMPLES_NSH_FATNSECTORS=1024
CONFIG_EXAMPLES_NSH_FATNSECTORS=40
CONFIG_EXAMPLES_NSH_FATMOUNTPT=/tmp
#

7
nuttx/configs/vsn/src/Makefile
View File

@ -43,13 +43,14 @@ CFLAGS += -I$(TOPDIR)/sched
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_sysclock.c up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c
CSRCS = sysclock.c boot.c leds.c buttons.c spi.c \
usbdev.c sdcard.c ramtron.c power.c
ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
CSRCS += up_nsh.c
CSRCS += nsh.c
endif
ifeq ($(CONFIG_APP_DIR),examples/usbstorage)
CSRCS += up_usbstrg.c
CSRCS += usbstrg.c
endif
COBJS = $(CSRCS:.c=$(OBJEXT))

12
nuttx/configs/vsn/src/README.txt Normal file
View File

@ -0,0 +1,12 @@
The directory contains start-up and board level functions.
Execution starts in the following order:
- sysclock, immediately after reset stm32_rcc calls external
clock configuration when
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
is set. It must be set for the VSN board.
- boot, performs initial chip and board initialization
- ...
- nsh, as central application last.

31
nuttx/configs/vsn/src/up_boot.c → nuttx/configs/vsn/src/boot.c
View File

@ -1,6 +1,6 @@
/************************************************************************************
* configs/vsn/src/up_boot.c
* arch/arm/src/board/up_boot.c
* configs/vsn/src/boot.c
* arch/arm/src/board/boot.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (c) 2011 Uros Platise. All rights reserved.
@ -47,8 +47,9 @@
#include <arch/board/board.h>
#include "stm32_gpio.h"
#include "up_arch.h"
#include "vsn-internal.h"
#include "vsn.h"
/************************************************************************************
* Definitions
@ -74,15 +75,24 @@
void stm32_boardinitialize(void)
{
#ifdef CONFIG_STM32_SPI3
#warning JTAG Port Disabled as SPI3 NVRAM/FRAM support is enabled
uint32_t val = getreg32(STM32_AFIO_MAPR);
val &= 0x00FFFFFF; // clear undefined readings ...
val |= AFIO_MAPR_DISAB; // set JTAG-DP and SW-DP Disabled
putreg32(val, STM32_AFIO_MAPR);
#endif
// Set Board Voltage to 3.3 V
board_power_setbootvoltage();
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
* stm32_spiinitialize() has been brought into the link.
*/
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2)
if (stm32_spiinitialize)
{
stm32_spiinitialize();
}
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
if (stm32_spiinitialize) stm32_spiinitialize();
#endif
/* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not
@ -91,10 +101,7 @@ void stm32_boardinitialize(void)
*/
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
if (stm32_usbinitialize)
{
stm32_usbinitialize();
}
if (stm32_usbinitialize) stm32_usbinitialize();
#endif
/* Configure on-board LEDs if LED support has been selected. */

4
nuttx/configs/vsn/src/up_buttons.c → nuttx/configs/vsn/src/buttons.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* configs/vsn-1.2/src/up_buttons.c
* configs/vsn/src/buttons.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "vsn-internal.h"
#include "vsn.h"
#ifdef CONFIG_ARCH_BUTTONS

6
nuttx/configs/vsn/src/up_leds.c → nuttx/configs/vsn/src/leds.c
View File

@ -1,6 +1,6 @@
/****************************************************************************
* configs/vsn-1.2/src/up_leds.c
* arch/arm/src/board/up_leds.c
* configs/vsn/src/leds.c
* arch/arm/src/board/leds.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
@ -48,7 +48,7 @@
#include <debug.h>
#include <arch/board/board.h>
#include "vsn-internal.h"
#include "vsn.h"
/****************************************************************************
* Definitions

89
nuttx/configs/vsn/src/nsh.c Normal file
View File

@ -0,0 +1,89 @@
/****************************************************************************
* config/vsn/src/nsh.c
* arch/arm/src/board/nsh.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include "vsn.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* PORT and SLOT number probably depend on the board configuration */
#define CONFIG_EXAMPLES_NSH_HAVEUSBDEV 1
/* Can't support USB features if USB is not enabled */
#ifndef CONFIG_USBDEV
# undef CONFIG_EXAMPLES_NSH_HAVEUSBDEV
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: nsh_archinitialize
*
* Description:
* Perform architecture specific initialization
*
****************************************************************************/
int nsh_archinitialize(void)
{
up_ramtron();
up_sdcard();
return OK;
}

57
nuttx/configs/vsn/src/power.c Normal file
View File

@ -0,0 +1,57 @@
/****************************************************************************
* config/vsn/src/ramtron.c
* arch/arm/src/board/ramtron.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <arch/board/board.h>
#include "vsn.h"
void board_power_register(void);
void board_power_adjust(void);
void board_power_status(void);
void board_power_setbootvoltage(void)
{
stm32_configgpio(GPIO_PVS);
}
void board_power_reboot(void);
void board_power_off(void);

87
nuttx/configs/vsn/src/ramtron.c Normal file
View File

@ -0,0 +1,87 @@
/****************************************************************************
* config/vsn/src/ramtron.c
* arch/arm/src/board/ramtron.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#ifdef CONFIG_STM32_SPI3
# include <nuttx/spi.h>
# include <nuttx/mtd.h>
#endif
#include "vsn.h"
int up_ramtron(void)
{
#ifdef CONFIG_STM32_SPI3
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
int retval;
/* Get the SPI port */
message("nsh_archinitialize: Initializing SPI port 3\n");
spi = up_spiinitialize(3);
if (!spi)
{
message("nsh_archinitialize: Failed to initialize SPI port 3\n");
return -ENODEV;
}
message("nsh_archinitialize: Successfully initialized SPI port 3\n");
message("nsh_archinitialize: Bind SPI to the SPI flash driver\n");
mtd = ramtron_initialize(spi);
if (!mtd)
{
message("nsh_archinitialize: Failed to bind SPI port 0 to the SPI FLASH driver\n");
return -ENODEV;
}
message("nsh_archinitialize: Successfully bound SPI port 0 to the SPI FLASH driver\n");
retval = ftl_initialize(0,NULL, mtd);
message("FTL returned with %d\n", retval);
#endif
return OK;
}

120
nuttx/configs/vsn/src/sdcard.c Normal file
View File

@ -0,0 +1,120 @@
/****************************************************************************
* config/vsn/src/sdcard.c
* arch/arm/src/board/sdcard.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#ifdef CONFIG_STM32_SDIO
# include <nuttx/sdio.h>
# include <nuttx/mmcsd.h>
#endif
#include "vsn.h"
#define CONFIG_EXAMPLES_NSH_HAVEMMCSD 1
#if defined(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO) && CONFIG_EXAMPLES_NSH_MMCSDSLOTNO != 0
# error "Only one MMC/SD slot"
# undef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
#endif
#ifndef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
# define CONFIG_EXAMPLES_NSH_MMCSDSLOTNO 0
#endif
/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support
* is not enabled.
*/
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO)
# undef CONFIG_EXAMPLES_NSH_HAVEMMCSD
#endif
#ifndef CONFIG_EXAMPLES_NSH_MMCSDMINOR
# define CONFIG_EXAMPLES_NSH_MMCSDMINOR 0
#endif
int up_sdcard(void)
{
/* Mount the SDIO-based MMC/SD block driver */
#ifdef CONFIG_EXAMPLES_NSH_HAVEMMCSD
FAR struct sdio_dev_s *sdio;
int ret;
/* First, get an instance of the SDIO interface */
message("nsh_archinitialize: Initializing SDIO slot %d\n",
CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
sdio = sdio_initialize(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
if (!sdio)
{
message("nsh_archinitialize: Failed to initialize SDIO slot %d\n",
CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
return -ENODEV;
}
/* Now bind the SPI interface to the MMC/SD driver */
message("nsh_archinitialize: Bind SDIO to the MMC/SD driver, minor=%d\n",
CONFIG_EXAMPLES_NSH_MMCSDMINOR);
ret = mmcsd_slotinitialize(CONFIG_EXAMPLES_NSH_MMCSDMINOR, sdio);
if (ret != OK)
{
message("nsh_archinitialize: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n");
/* Then let's guess and say that there is a card in the slot. I need to check to
* see if the VSN board supports a GPIO to detect if there is a card in
* the slot.
*/
sdio_mediachange(sdio, true);
#endif
return OK;
}

37
nuttx/configs/vsn/src/up_spi.c → nuttx/configs/vsn/src/spi.c
View File

@ -1,6 +1,6 @@
/************************************************************************************
* configs/vsn/src/up_spi.c
* arch/arm/src/board/up_spi.c
* configs/vsn/src/spi.c
* arch/arm/src/board/spi.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
@ -42,20 +42,20 @@
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi.h>
#include <arch/board/board.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/spi.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_internal.h"
#include "vsn-internal.h"
#include "vsn.h"
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
/************************************************************************************
* Definitions
@ -97,16 +97,15 @@
void weak_function stm32_spiinitialize(void)
{
/* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c.
/* NOTE: Clocking for SPI1 and/or SPI2 and SPI3 was already provided in stm32_rcc.c.
* Configurations of SPI pins is performed in stm32_spi.c.
* Here, we only initialize chip select pins unique to the board
* architecture.
* Here, we only initialize chip select pins unique to the board architecture.
*/
#ifdef CONFIG_STM32_SPI1
/* Configure the SPI-based FLASH CS GPIO */
#ifdef CONFIG_STM32_SPI3
stm32_configgpio(GPIO_FLASH_CS);
// Configure the SPI-based FRAM CS GPIO
stm32_configgpio(GPIO_FRAM_CS);
#endif
}
@ -139,13 +138,6 @@ void weak_function stm32_spiinitialize(void)
void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
if (devid == SPIDEV_FLASH)
{
/* Set the GPIO low to select and high to de-select */
stm32_gpiowrite(GPIO_FLASH_CS, !selected);
}
}
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@ -170,6 +162,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
if (devid == SPIDEV_FLASH)
{
/* Set the GPIO low to select and high to de-select */
stm32_gpiowrite(GPIO_FRAM_CS, !selected);
}
}
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)

2
nuttx/configs/vsn/src/up_sysclock.c → nuttx/configs/vsn/src/sysclock.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* configs/vsn-1.2/src/up_sysclock.c
* configs/vsn/src/sysclock.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
*

215
nuttx/configs/vsn/src/up_nsh.c
View File

@ -1,215 +0,0 @@
/****************************************************************************
* config/vsn/src/up_nsh.c
* arch/arm/src/board/up_nsh.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
*
* Authors: Gregory Nutt <spudmonkey@racsa.co.cr>
* Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#ifdef CONFIG_STM32_SPI1
# include <nuttx/spi.h>
# include <nuttx/mtd.h>
#endif
#ifdef CONFIG_STM32_SDIO
# include <nuttx/sdio.h>
# include <nuttx/mmcsd.h>
#endif
#include "vsn-internal.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* For now, don't build in any SPI1 support -- NSH is not using it */
#undef CONFIG_STM32_SPI1
/* PORT and SLOT number probably depend on the board configuration */
#ifdef CONFIG_ARCH_BOARD_VSN
# define CONFIG_EXAMPLES_NSH_HAVEUSBDEV 1
# define CONFIG_EXAMPLES_NSH_HAVEMMCSD 1
# if defined(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO) && CONFIG_EXAMPLES_NSH_MMCSDSLOTNO != 0
# error "Only one MMC/SD slot"
# undef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
# endif
# ifndef CONFIG_EXAMPLES_NSH_MMCSDSLOTNO
# define CONFIG_EXAMPLES_NSH_MMCSDSLOTNO 0
# endif
#else
/* Add configuration for new STM32 boards here */
# undef CONFIG_EXAMPLES_NSH_HAVEUSBDEV
# undef CONFIG_EXAMPLES_NSH_HAVEMMCSD
#endif
/* Can't support USB features if USB is not enabled */
#ifndef CONFIG_USBDEV
# undef CONFIG_EXAMPLES_NSH_HAVEUSBDEV
#endif
/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support
* is not enabled.
*/
#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO)
# undef CONFIG_EXAMPLES_NSH_HAVEMMCSD
#endif
#ifndef CONFIG_EXAMPLES_NSH_MMCSDMINOR
# define CONFIG_EXAMPLES_NSH_MMCSDMINOR 0
#endif
/* Debug ********************************************************************/
#ifdef CONFIG_CPP_HAVE_VARARGS
# ifdef CONFIG_DEBUG
# define message(...) lib_lowprintf(__VA_ARGS__)
# else
# define message(...) printf(__VA_ARGS__)
# endif
#else
# ifdef CONFIG_DEBUG
# define message lib_lowprintf
# else
# define message printf
# endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: nsh_archinitialize
*
* Description:
* Perform architecture specific initialization
*
****************************************************************************/
int nsh_archinitialize(void)
{
#ifdef CONFIG_STM32_SPI1
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
#endif
#ifdef CONFIG_EXAMPLES_NSH_HAVEMMCSD
FAR struct sdio_dev_s *sdio;
int ret;
#endif
/* Configure SPI-based devices */
#ifdef CONFIG_STM32_SPI1
/* Get the SPI port */
message("nsh_archinitialize: Initializing SPI port 0\n");
spi = up_spiinitialize(0);
if (!spi)
{
message("nsh_archinitialize: Failed to initialize SPI port 0\n");
return -ENODEV;
}
message("nsh_archinitialize: Successfully initialized SPI port 0\n");
/* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */
message("nsh_archinitialize: Bind SPI to the SPI flash driver\n");
mtd = m25p_initialize(spi);
if (!mtd)
{
message("nsh_archinitialize: Failed to bind SPI port 0 to the SPI FLASH driver\n");
return -ENODEV;
}
message("nsh_archinitialize: Successfully bound SPI port 0 to the SPI FLASH driver\n");
#warning "Now what are we going to do with this SPI FLASH driver?"
#endif
/* Create the SPI FLASH MTD instance */
/* The M25Pxx is not a give media to implement a file system..
* its block sizes are too large
*/
/* Mount the SDIO-based MMC/SD block driver */
#ifdef CONFIG_EXAMPLES_NSH_HAVEMMCSD
/* First, get an instance of the SDIO interface */
message("nsh_archinitialize: Initializing SDIO slot %d\n",
CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
sdio = sdio_initialize(CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
if (!sdio)
{
message("nsh_archinitialize: Failed to initialize SDIO slot %d\n",
CONFIG_EXAMPLES_NSH_MMCSDSLOTNO);
return -ENODEV;
}
/* Now bind the SPI interface to the MMC/SD driver */
message("nsh_archinitialize: Bind SDIO to the MMC/SD driver, minor=%d\n",
CONFIG_EXAMPLES_NSH_MMCSDMINOR);
ret = mmcsd_slotinitialize(CONFIG_EXAMPLES_NSH_MMCSDMINOR, sdio);
if (ret != OK)
{
message("nsh_archinitialize: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n");
/* Then let's guess and say that there is a card in the slot. I need to check to
* see if the VSN board supports a GPIO to detect if there is a card in
* the slot.
*/
sdio_mediachange(sdio, true);
#endif
return OK;
}

6
nuttx/configs/vsn/src/up_usbdev.c → nuttx/configs/vsn/src/usbdev.c
View File

@ -1,6 +1,6 @@
/************************************************************************************
* configs/svsn/src/up_usbdev.c
* arch/arm/src/board/up_boot.c
* configs/svsn/src/usbdev.c
* arch/arm/src/board/boot.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (c) 2011 Uros Platise. All rights reserved.
@ -53,7 +53,7 @@
#include "up_arch.h"
#include "stm32_internal.h"
#include "vsn-internal.h"
#include "vsn.h"
/************************************************************************************
* Definitions

4
nuttx/configs/vsn/src/up_usbstrg.c → nuttx/configs/vsn/src/usbstrg.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* configs/vsn/src/up_usbstrg.c
* configs/vsn/src/usbstrg.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (c) 2011 Uros Platise. All rights reserved.
@ -51,7 +51,7 @@
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "vsn-internal.h"
#include "vsn.h"
#ifdef CONFIG_STM32_SDIO

55
nuttx/configs/vsn/src/vsn-internal.h → nuttx/configs/vsn/src/vsn.h
View File

@ -1,6 +1,6 @@
/************************************************************************************
* configs/vsn/src/vsn-internal.h
* arch/arm/src/board/vsn-internal.n
* configs/vsn/src/vsn.h
* arch/arm/src/board/vsn.n
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (c) 2011 Uros Platise. All rights reserved.
@ -44,6 +44,7 @@
* Included Files
************************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
@ -52,20 +53,6 @@
* Definitions
************************************************************************************/
/* How many SPI modules does this chip support? The LM3S6918 supports 2 SPI
* modules (others may support more -- in such case, the following must be
* expanded).
*/
#if STM32_NSPI < 1
# undef CONFIG_STM32_SPI1
# undef CONFIG_STM32_SPI2
#elif STM32_NSPI < 2
# undef CONFIG_STM32_SPI2
#endif
/* VSN 1.2 GPIOs **************************************************************/
/* LED */
#define GPIO_LED (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2)
@ -74,6 +61,32 @@
#define GPIO_PUSHBUTTON (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
/* Power Management Pins */
#define GPIO_PVS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN7)
/* FRAM */
#define GPIO_FRAM_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN15)
/* Debug ********************************************************************/
#ifdef CONFIG_CPP_HAVE_VARARGS
# ifdef CONFIG_DEBUG
# define message(...) lib_lowprintf(__VA_ARGS__)
# else
# define message(...) printf(__VA_ARGS__)
# endif
#else
# ifdef CONFIG_DEBUG
# define message lib_lowprintf
# else
# define message printf
# endif
#endif
/************************************************************************************
* Public Types
************************************************************************************/
@ -108,14 +121,18 @@ extern void weak_function stm32_spiinitialize(void);
extern void weak_function stm32_usbinitialize(void);
/************************************************************************************
* Name: stm32_extcontextsave
* Power Module
*
* Description:
* Save current GPIOs that will used by external memory configurations
*
* - Provides power related board operations, such as voltage selection,
* proper reboot sequence, and power-off
************************************************************************************/
extern void board_power_setbootvoltage(void); // Default voltage at boot time
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_VSN_1_2_SRC_VSN_INTERNAL_H */

10
nuttx/drivers/mmcsd/mmcsd_sdio.c
View File

@ -2077,6 +2077,7 @@ static void mmcsd_mediachange(FAR void *arg)
static int mmcsd_widebus(FAR struct mmcsd_state_s *priv)
{
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
int ret;
/* Check if the SD card supports this feature (as reported in the SCR) */
@ -2145,6 +2146,13 @@ static int mmcsd_widebus(FAR struct mmcsd_state_s *priv)
fdbg("WARNING: Card does not support wide-bus operation\n");
return -ENOSYS;
#else /* CONFIG_SDIO_WIDTH_D1_ONLY */
fvdbg("Wide-bus operation is disabled\n");
return -ENOSYS;
#endif /* CONFIG_SDIO_WIDTH_D1_ONLY */
}
/****************************************************************************
@ -2613,7 +2621,7 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv)
elapsed = g_system_timer - start;
}
while (elapsed < TICK_PER_SEC && ret != OK);
while( elapsed < TICK_PER_SEC ); /* On successful reception while 'breaks', see above. */
/* We get here when the above loop completes, either (1) we could not
* communicate properly with the card due to errors (and the loop times

2
nuttx/drivers/mmcsd/mmcsd_sdio.h
View File

@ -1,7 +1,7 @@
/********************************************************************************************
* drivers/mmcsd/mmcsd_sdio.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without

3
nuttx/drivers/mtd/Make.defs
View File

@ -34,5 +34,4 @@
############################################################################
MTD_ASRCS =
MTD_CSRCS = ftl.c m25px.c at45db.c
MTD_CSRCS = ftl.c m25px.c at45db.c ramtron.c

6
nuttx/drivers/mtd/ftl.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* drivers/mtd/ftl.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -182,7 +182,7 @@ static ssize_t ftl_read(FAR struct inode *inode, unsigned char *buffer,
{
struct ftl_struct_s *dev;
fvdbg("sector: %d nsectors: %d sectorsize: %d\n");
fvdbg("sector: %d nsectors: %d\n", start_sector, nsectors);
DEBUGASSERT(inode && inode->i_private);
dev = (struct ftl_struct_s *)inode->i_private;
@ -360,7 +360,7 @@ static ssize_t ftl_write(FAR struct inode *inode, const unsigned char *buffer,
{
struct ftl_struct_s *dev;
fvdbg("sector: %d nsectors: %d sectorsize: %d\n");
fvdbg("sector: %d nsectors: %d\n", start_sector, nsectors);
DEBUGASSERT(inode && inode->i_private);
dev = (struct ftl_struct_s *)inode->i_private;

668
nuttx/drivers/mtd/ramtron.c Executable file
View File

@ -0,0 +1,668 @@
/************************************************************************************
* drivers/mtd/ramtron.c
* Driver for SPI-based RAMTRON NVRAM Devices FM25V10 and others (not tested)
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <spudmonkey@racsa.co.cr>
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* OPTIONS:
* - additional non-jedec standard device: FM25H20
* must be enabled with the CONFIG_RAMTRON_FRAM_NON_JEDEC=y
*
* NOTE:
* - frequency is fixed to desired max by RAMTRON_INIT_CLK_MAX
* if new devices with different speed arrive, then SETFREQUENCY()
* needs to handle freq changes and INIT_CLK_MAX must be reduced
* to fit all devices. Note that STM32_SPI driver is prone to
* too high freq. parameters and limit it within physical constraints.
*
* TODO:
* - add support for sleep
* - add support for faster read FSTRD command
*/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <errno.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/ioctl.h>
#include <nuttx/spi.h>
#include <nuttx/mtd.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* RAMTRON devices are flat!
* For purpose of the VFAT file system we emulate the following configuration:
*/
#define RAMTRON_EMULATE_SECTOR_SHIFT 9
#define RAMTRON_EMULATE_PAGE_SHIFT 9
/* RAMTRON Indentification register values */
#define RAMTRON_MANUFACTURER 0x7F
#define RAMTRON_MEMORY_TYPE 0xC2
/* Instructions:
* Command Value N Description Addr Dummy Data */
#define RAMTRON_WREN 0x06 /* 1 Write Enable 0 0 0 */
#define RAMTRON_WRDI 0x04 /* 1 Write Disable 0 0 0 */
#define RAMTRON_RDSR 0x05 /* 1 Read Status Register 0 0 >=1 */
#define RAMTRON_WRSR 0x01 /* 1 Write Status Register 0 0 1 */
#define RAMTRON_READ 0x03 /* 1 Read Data Bytes A 0 >=1 */
#define RAMTRON_FSTRD 0x0b /* 1 Higher speed read A 1 >=1 */
#define RAMTRON_WRITE 0x02 /* 1 Write A 0 1-256 */
#define RAMTRON_SLEEP 0xb9 // TODO:
#define RAMTRON_RDID 0x9f /* 1 Read Identification 0 0 1-3 */
#define RAMTRON_SN 0xc3 // TODO:
/* Status register bit definitions */
#define RAMTRON_SR_WIP (1 << 0) /* Bit 0: Write in progress bit */
#define RAMTRON_SR_WEL (1 << 1) /* Bit 1: Write enable latch bit */
#define RAMTRON_SR_BP_SHIFT (2) /* Bits 2-4: Block protect bits */
#define RAMTRON_SR_BP_MASK (7 << RAMTRON_SR_BP_SHIFT)
# define RAMTRON_SR_BP_NONE (0 << RAMTRON_SR_BP_SHIFT) /* Unprotected */
# define RAMTRON_SR_BP_UPPER64th (1 << RAMTRON_SR_BP_SHIFT) /* Upper 64th */
# define RAMTRON_SR_BP_UPPER32nd (2 << RAMTRON_SR_BP_SHIFT) /* Upper 32nd */
# define RAMTRON_SR_BP_UPPER16th (3 << RAMTRON_SR_BP_SHIFT) /* Upper 16th */
# define RAMTRON_SR_BP_UPPER8th (4 << RAMTRON_SR_BP_SHIFT) /* Upper 8th */
# define RAMTRON_SR_BP_UPPERQTR (5 << RAMTRON_SR_BP_SHIFT) /* Upper quarter */
# define RAMTRON_SR_BP_UPPERHALF (6 << RAMTRON_SR_BP_SHIFT) /* Upper half */
# define RAMTRON_SR_BP_ALL (7 << RAMTRON_SR_BP_SHIFT) /* All sectors */
#define RAMTRON_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */
#define RAMTRON_DUMMY 0xa5
/************************************************************************************
* Private Types
************************************************************************************/
struct ramtron_parts_s
{
const char *name;
uint8_t id1, id2;
uint32_t size;
uint8_t addr_len;
uint32_t speed;
};
/* This type represents the state of the MTD device. The struct mtd_dev_s
* must appear at the beginning of the definition so that you can freely
* cast between pointers to struct mtd_dev_s and struct ramtron_dev_s.
*/
struct ramtron_dev_s
{
struct mtd_dev_s mtd; /* MTD interface */
FAR struct spi_dev_s *dev; /* Saved SPI interface instance */
uint8_t sectorshift;
uint8_t pageshift;
uint16_t nsectors;
uint32_t npages;
const struct ramtron_parts_s *part; /* part instance */
};
/************************************************************************************
* Supported Part Lists
************************************************************************************/
// Defines the initial speed compatible with all devices. In case of RAMTRON
// the defined devices within the part list have all the same speed.
#define RAMTRON_INIT_CLK_MAX 40000000UL
static struct ramtron_parts_s ramtron_parts[] =
{
{
.size = 32*1024,
.addr_len = 2,
.id1 = 0x22,
.id2 = 0x00,
.speed = 40000000,
.name = "FM25V02",
},
{
.size = 32*1024,
.addr_len = 2,
.id1 = 0x22,
.id2 = 0x01,
.speed = 40000000,
.name = "FM25VN02",
},
{
.size = 64*1024,
.addr_len = 2,
.id1 = 0x23,
.id2 = 0x00,
.speed = 40000000,
.name = "FM25V05",
},
{
.size = 64*1024,
.addr_len = 2,
.id1 = 0x23,
.id2 = 0x01,
.speed = 40000000,
.name = "FM25VN05",
},
{
.size = 128*1024,
.addr_len = 3,
.id1 = 0x24,
.id2 = 0x00,
.speed = 40000000,
.name = "FM25V10",
},
{
.size = 128*1024,
.addr_len = 3,
.id1 = 0x24,
.id2 = 0x01,
.speed = 40000000,
.name = "FM25VN10",
},
#ifdef CONFIG_RAMTRON_FRAM_NON_JEDEC
{
.size = 256*1024,
.addr_len = 3,
.id1 = 0xff,
.id2 = 0xff,
.speed = 40000000,
.name = "FM25H20",
},
{
.name = NULL,
}
#endif
};
/************************************************************************************
* Private Function Prototypes
************************************************************************************/
/* Helpers */
static void ramtron_lock(FAR struct spi_dev_s *dev);
static inline void ramtron_unlock(FAR struct spi_dev_s *dev);
static inline int ramtron_readid(struct ramtron_dev_s *priv);
static void ramtron_waitwritecomplete(struct ramtron_dev_s *priv);
static void ramtron_writeenable(struct ramtron_dev_s *priv);
static inline void ramtron_pagewrite(struct ramtron_dev_s *priv, FAR const uint8_t *buffer,
off_t offset);
/* MTD driver methods */
static int ramtron_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks);
static ssize_t ramtron_bread(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR uint8_t *buf);
static ssize_t ramtron_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf);
static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buffer);
static int ramtron_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
/************************************************************************************
* Private Data
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: ramtron_lock
************************************************************************************/
static void ramtron_lock(FAR struct spi_dev_s *dev)
{
/* On SPI busses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the busses for a sequence of
* transfers. The bus should be locked before the chip is selected.
*
* This is a blocking call and will not return until we have exclusiv access to
* the SPI buss. We will retain that exclusive access until the bus is unlocked.
*/
(void)SPI_LOCK(dev, true);
/* After locking the SPI bus, the we also need call the setfrequency, setbits, and
* setmode methods to make sure that the SPI is properly configured for the device.
* If the SPI buss is being shared, then it may have been left in an incompatible
* state.
*/
SPI_SETMODE(dev, SPIDEV_MODE3);
SPI_SETBITS(dev, 8);
(void)SPI_SETFREQUENCY(dev, RAMTRON_INIT_CLK_MAX);
}
/************************************************************************************
* Name: ramtron_unlock
************************************************************************************/
static inline void ramtron_unlock(FAR struct spi_dev_s *dev)
{
(void)SPI_LOCK(dev, false);
}
/************************************************************************************
* Name: ramtron_readid
************************************************************************************/
static inline int ramtron_readid(struct ramtron_dev_s *priv)
{
uint16_t manufacturer, memory, capacity, part;
int i;
fvdbg("priv: %p\n", priv);
/* Lock the SPI bus, configure the bus, and select this FLASH part. */
ramtron_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send the "Read ID (RDID)" command and read the first three ID bytes */
(void)SPI_SEND(priv->dev, RAMTRON_RDID);
for (i=0; i<6; i++) manufacturer = SPI_SEND(priv->dev, RAMTRON_DUMMY);
memory = SPI_SEND(priv->dev, RAMTRON_DUMMY);
capacity = SPI_SEND(priv->dev, RAMTRON_DUMMY); // fram.id1
part = SPI_SEND(priv->dev, RAMTRON_DUMMY); // fram.id2
/* Deselect the FLASH and unlock the bus */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
ramtron_unlock(priv->dev);
// Select part from the part list
for (priv->part = ramtron_parts;
priv->part->name != NULL && !(priv->part->id1 == capacity && priv->part->id2 == part);
priv->part++);
if (priv->part->name) {
fvdbg("RAMTRON %s of size %d bytes (mf:%02x mem:%02x cap:%02x part:%02x)\n",
priv->part->name, priv->part->size, manufacturer, memory, capacity, part);
priv->sectorshift = RAMTRON_EMULATE_SECTOR_SHIFT;
priv->nsectors = priv->part->size / (1 << RAMTRON_EMULATE_SECTOR_SHIFT);
priv->pageshift = RAMTRON_EMULATE_PAGE_SHIFT;
priv->npages = priv->part->size / (1 << RAMTRON_EMULATE_PAGE_SHIFT);
return OK;
}
fvdbg("RAMTRON device not found\n");
return -ENODEV;
}
/************************************************************************************
* Name: ramtron_waitwritecomplete
************************************************************************************/
static void ramtron_waitwritecomplete(struct ramtron_dev_s *priv)
{
uint8_t status;
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, RAMTRON_RDSR);
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, RAMTRON_DUMMY);
}
while ((status & RAMTRON_SR_WIP) != 0);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Complete\n");
}
/************************************************************************************
* Name: ramtron_writeenable
************************************************************************************/
static void ramtron_writeenable(struct ramtron_dev_s *priv)
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Write Enable (WREN)" command */
(void)SPI_SEND(priv->dev, RAMTRON_WREN);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Enabled\n");
}
/************************************************************************************
* Name: ramtron_sendaddr
************************************************************************************/
static inline void ramtron_sendaddr(const struct ramtron_dev_s *priv, uint32_t addr)
{
DEBUGASSERT(priv->part->addr_len == 3 || priv->part->addr_len == 2);
if (priv->part->addr_len == 3)
(void)SPI_SEND(priv->dev, (addr >> 16) & 0xff);
(void)SPI_SEND(priv->dev, (addr >> 8) & 0xff);
(void)SPI_SEND(priv->dev, addr & 0xff);
}
/************************************************************************************
* Name: ramtron_pagewrite
************************************************************************************/
static inline void ramtron_pagewrite(struct ramtron_dev_s *priv, FAR const uint8_t *buffer,
off_t page)
{
off_t offset = page << priv->pageshift;
fvdbg("page: %08lx offset: %08lx\n", (long)page, (long)offset);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
* improve performance.
*/
ramtron_waitwritecomplete(priv);
/* Enable the write access to the FLASH */
ramtron_writeenable(priv);
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Page Program (PP)" command */
(void)SPI_SEND(priv->dev, RAMTRON_WRITE);
/* Send the page offset high byte first. */
ramtron_sendaddr(priv, offset);
/* Then write the specified number of bytes */
SPI_SNDBLOCK(priv->dev, buffer, 1 << priv->pageshift);
/* Deselect the FLASH: Chip Select high */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Written\n");
}
/************************************************************************************
* Name: ramtron_erase
************************************************************************************/
static int ramtron_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks)
{
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
fvdbg("On RAMTRON devices erasing makes no sense, returning as OK\n");
return (int)nblocks;
}
/************************************************************************************
* Name: ramtron_bread
************************************************************************************/
static ssize_t ramtron_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR uint8_t *buffer)
{
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
ssize_t nbytes;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
nbytes = ramtron_read(dev, startblock << priv->pageshift, nblocks << priv->pageshift, buffer);
if (nbytes > 0)
{
return nbytes >> priv->pageshift;
}
return (int)nbytes;
}
/************************************************************************************
* Name: ramtron_bwrite
************************************************************************************/
static ssize_t ramtron_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR const uint8_t *buffer)
{
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
size_t blocksleft = nblocks;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* Lock the SPI bus and write each page to FLASH */
ramtron_lock(priv->dev);
while (blocksleft-- > 0)
{
ramtron_pagewrite(priv, buffer, startblock);
startblock++;
}
ramtron_unlock(priv->dev);
return nblocks;
}
/************************************************************************************
* Name: ramtron_read
************************************************************************************/
static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buffer)
{
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
* improve performance.
*/
ramtron_waitwritecomplete(priv);
/* Lock the SPI bus and select this FLASH part */
ramtron_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read from Memory " instruction */
(void)SPI_SEND(priv->dev, RAMTRON_READ);
/* Send the page offset high byte first. */
ramtron_sendaddr(priv, offset);
/* Then read all of the requested bytes */
SPI_RECVBLOCK(priv->dev, buffer, nbytes);
/* Deselect the FLASH and unlock the SPI bus */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
ramtron_unlock(priv->dev);
fvdbg("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
/************************************************************************************
* Name: ramtron_ioctl
************************************************************************************/
static int ramtron_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
{
FAR struct ramtron_dev_s *priv = (FAR struct ramtron_dev_s *)dev;
int ret = -EINVAL; /* Assume good command with bad parameters */
fvdbg("cmd: %d \n", cmd);
switch (cmd)
{
case MTDIOC_GEOMETRY:
{
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg);
if (geo)
{
/* Populate the geometry structure with information need to know
* the capacity and how to access the device.
*
* NOTE: that the device is treated as though it where just an array
* of fixed size blocks. That is most likely not true, but the client
* will expect the device logic to do whatever is necessary to make it
* appear so.
*/
geo->blocksize = (1 << priv->pageshift);
geo->erasesize = (1 << priv->sectorshift);
geo->neraseblocks = priv->nsectors;
ret = OK;
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
geo->blocksize, geo->erasesize, geo->neraseblocks);
}
}
break;
case MTDIOC_BULKERASE:
fvdbg("BULDERASE: Makes no sense in ramtron. Let's confirm operation as OK\n");
ret = OK;
break;
case MTDIOC_XIPBASE:
default:
ret = -ENOTTY; /* Bad command */
break;
}
fvdbg("return %d\n", ret);
return ret;
}
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: ramtron_initialize
*
* Description:
* Create an initialize MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
************************************************************************************/
FAR struct mtd_dev_s *ramtron_initialize(FAR struct spi_dev_s *dev)
{
FAR struct ramtron_dev_s *priv;
fvdbg("dev: %p\n", dev);
/* Allocate a state structure (we allocate the structure instead of using
* a fixed, static allocation so that we can handle multiple FLASH devices.
* The current implementation would handle only one FLASH part per SPI
* device (only because of the SPIDEV_FLASH definition) and so would have
* to be extended to handle multiple FLASH parts on the same SPI bus.
*/
priv = (FAR struct ramtron_dev_s *)malloc(sizeof(struct ramtron_dev_s));
if (priv)
{
/* Initialize the allocated structure */
priv->mtd.erase = ramtron_erase;
priv->mtd.bread = ramtron_bread;
priv->mtd.bwrite = ramtron_bwrite;
priv->mtd.read = ramtron_read;
priv->mtd.ioctl = ramtron_ioctl;
priv->dev = dev;
/* Deselect the FLASH */
SPI_SELECT(dev, SPIDEV_FLASH, false);
/* Identify the FLASH chip and get its capacity */
if (ramtron_readid(priv) != OK)
{
/* Unrecognized! Discard all of that work we just did and return NULL */
free(priv);
priv = NULL;
}
}
/* Return the implementation-specific state structure as the MTD device */
fvdbg("Return %p\n", priv);
return (FAR struct mtd_dev_s *)priv;
}