PIC32MZ: Review DEVCFG setting; adjust a few to match example code
This commit is contained in:
Gregory Nutt
parent
9f92936a07
commit
5e3a3cbca8
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@ -340,13 +340,14 @@ menu "Device Configuration 0 (DEVCFG0)"
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config PIC32MZ_DEBUGGER_ENABLE
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bool "Background debugger enable"
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default n
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default y if CONFIG_DEBUG
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default n if !CONFIG_DEBUG
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---help---
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Background Debugger Enable
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config PIC32MZ_JTAG_ENABLE
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bool "JTAG enable"
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default y
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default n
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---help---
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JTAG Enable
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@ -358,7 +359,8 @@ config PIC32MZ_ICESEL_CH2
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config PIC32MZ_TRACE_ENABLE
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bool "Trace enable"
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default n
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default y if CONFIG_DEBUG
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default n if !CONFIG_DEBUG
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---help---
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Trace Enable
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@ -368,14 +370,22 @@ menu "Device Configuration 1 (DEVCFG1)"
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config CONFIG_PIC32MZ_OSCIOFNC
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int "CLKO Enable"
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default 0
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default 1
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range 0 1
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---help---
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Enable CLK0 output on power up. Options:
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1: CLKO output disabled
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0: CLKO output signal active on the OSC2 pin
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config PIC32MZ_WDTENABLE
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bool "Watchdog enable"
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default 0
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---help---
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Enabled watchdog on power up. Default 0 (watchdog can be enabled later by software).
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Enabled watchdog on power up.
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1: Watchdog enabled, cannot be disabled
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0: Watchdog disabled, can be enabled
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endmenu
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@ -359,6 +359,8 @@
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# define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */
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# define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */
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#define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */
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# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */
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# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */
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#define DEVCFG2_RWO 0xbff88008 /* Bits 3, 15, 19-29, 31: Reserved, write as one */
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@ -419,9 +421,15 @@
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# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
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# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
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# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
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#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */
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#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */
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# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */
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# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */
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#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */
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# define DEVCFG1_WDT_NORMAL (1 << 22) /* Bit 22=1: Watchdog normal mode */
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# define DEVCFG1_WDT_WINDOW (0 << 22) /* Bit 22=0: Watchdog window mode */
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#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */
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# define DEVCFG1_FWDT_ENABLED (1 << 23) /* Bit 23=1: Watchdog enabled, cannot be disabled */
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# define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */
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#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */
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#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT)
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# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */
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@ -448,6 +456,8 @@
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# define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */
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#define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */
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#define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */
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# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */
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# define DEVCFG0_BOOT_MICROMIPS (0 << 6) /* Bit 6=0: Boot code and Exception code is microMIPS */
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#define DEVCFG0_FECCCON_SHIFT (8) /* Bit 8-9: Dynamic Flash ECC Configuration bits */
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#define DEVCFG0_FECCCON_MASK (3 << DEVCFG0_FECCCON_SHIFT)
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# define DEVCFG0_FECCCON_ECC (0 << DEVCFG0_FECCCON_SHIFT) /* Flash ECC enabled (locked) */
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@ -455,12 +465,17 @@
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# define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */
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# define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */
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#define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */
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# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */
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# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */
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#define DEVCFG0_DBGPER_SHIFT (12) /* Bits 12-14: Debug Mode CPU Access Permission bits */
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#define DEVCFG0_DBGPER_MASK (7 << DEVCFG0_DBGPER_SHIFT)
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# define DEVCFG0_DBGPER_GROUP0 (1 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 0 regions */
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# define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */
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# define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */
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# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */
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#define DEVCFG0_EJTAGBEN (1 << 30) /* Bit 30: EJTAG Boot Enable bit */
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# define DEVCFG0_EJTAG_NORMAL (1 << 30) /* Bit 30=1: Normal EJTAG functionality */
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# define DEVCFG0_EJTAG_REDUCED (0 << 30) /* Bit 30=0: Reduced EJTAG functionality */
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#define DEVCFG0_RW0 0xbfff8880 /* Bits 7, 11, 15-29, 31: Reserved, write as one */
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@ -152,6 +152,7 @@
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#ifndef CONFIG_PIC32MZ_USERID /* User ID */
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# define CONFIG_PIC32MZ_USERID 0x584e /* "NX" */
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#endif
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#define ADEVCFG3_USERID 0x1234
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#ifndef CONFIG_PIC32MZ_FMIIEN /* Ethernet MII enable: 0=RMII 1=MII */
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# define CONFIG_PIC32MZ_FMIIEN 1 /* MII enabled */
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@ -251,12 +252,17 @@
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# error "Unsupported BOARD_PLL_ODIV"
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#endif
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#if BOARD_POSC_FREQ == 12000000
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# define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL_12MHZ
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#else
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# define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL_24MHZ
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#endif
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/* Not yet configurable settings (REVISIT) */
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/* System PLL Input Clock Select bit */
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#define CONFIG_PIC32MZ_FPLLICLK 0 /* POSC is selected as input to the System PLL */
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/* USB PLL Input Frequency Select bit */
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#define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL
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/* DEVCFG1 */
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/* Configurable settings */
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@ -375,16 +381,17 @@
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#undef CONFIG_PIC32MZ_FWDTEN
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#if CONFIG_PIC32MZ_WDTENABLE
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDTEN
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_ENSABLED
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#else
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# define CONFIG_PIC32MZ_FWDTEN 0
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# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_DISABLED
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#endif
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#define ADEVCFG1_FWDTEN DEVCFG1_FWDT_DISABLED
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/* Not yet configurable settings */
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#define CONFIG_PIC32MZ_DMTINV DEVCFG1_FNOSC_FRCDIV
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#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM
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#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WINDIS
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#define CONFIG_PIC32MZ_DMTINV DEVCFG1_DMTINV_127_128
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#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM_STOP
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#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WDT_NORMAL
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#define CONFIG_PIC32MZ_FWDTWINSZ DEVCFG1_FWDTWINSZ_25
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#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MASK
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#define CONFIG_PIC32MZ_FDMTEN 0
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@ -422,11 +429,11 @@
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/* Not yet configurable settings */
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#define CONFIG_PIC32MZ_BOOTISA 0 /* microMIPS always */
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#define CONFIG_PIC32MZ_BOOTISA DEVCFG0_BOOT_MICROMIPS
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#define CONFIG_PIC32MZ_FECCCON DEVCFG0_FECCCON_DISWR
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#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP
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#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_MASK
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#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAGBEN
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#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF
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#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL
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#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL
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/************************************************************************************
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* Public Types
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@ -699,7 +699,7 @@ devcfg0:
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.type adevcfg, object
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adevcfg:
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adevcfg3:
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.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
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.long ADEVCFG3_USERID << DEVCFG3_USERID_SHIFT | \
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CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \
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CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \
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CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \
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@ -720,7 +720,7 @@ adevcfg1:
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CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
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CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
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CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
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CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
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ADEVCFG1_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
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CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
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CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
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DEVCFG1_RWO
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@ -61,6 +61,8 @@
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#define BOARD_FNOSC_SPLL 1 /* Use system PLL */
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#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
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#define BOARD_POSC_SWITCH 1 /* Enable clock switching */
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#undef BOARD_POSC_FSCM /* Disable clock monitoring */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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@ -143,7 +145,7 @@
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/* Watchdog pre-scaler (re-visit) */
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#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
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#define BOARD_WD_PRESCALER 1048576 /* Watchdog pre-scaler */
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/* LED definitions **********************************************************/
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/* LED Configuration ********************************************************/
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@ -152,14 +152,14 @@ CONFIG_PIC32MZ_UART1=y
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# Device Configuration 0 (DEVCFG0)
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#
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# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
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CONFIG_PIC32MZ_JTAG_ENABLE=y
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# CONFIG_PIC32MZ_ICESEL_CH2 is not set
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# CONFIG_PIC32MZ_JTAG_ENABLE is not set
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CONFIG_PIC32MZ_ICESEL_CH2=y
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# CONFIG_PIC32MZ_TRACE_ENABLE is not set
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#
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# Device Configuration 1 (DEVCFG1)
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#
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CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0
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CONFIG_CONFIG_PIC32MZ_OSCIOFNC=1
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# CONFIG_PIC32MZ_WDTENABLE is not set
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#
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@ -683,7 +683,6 @@ CONFIG_EXAMPLES_NSH=y
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#
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# CONFIG_NETUTILS_CODECS is not set
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# CONFIG_NETUTILS_FTPC is not set
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# CONFIG_NETUTILS_FTPD is not set
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# CONFIG_NETUTILS_JSON is not set
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# CONFIG_NETUTILS_SMTP is not set
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# CONFIG_NETUTILS_TFTPC is not set
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