Add RTC and WDG header files
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2080 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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/************************************************************************************
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* arch/arm/src/stm32/stm32_rtc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
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#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */
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#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */
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#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */
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#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */
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#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */
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#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */
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#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */
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#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */
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#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */
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#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET)
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#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET)
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#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET)
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#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET)
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#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET)
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#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET)
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#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET)
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#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET)
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#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET)
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#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* RTC control register High (16-bit) */
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#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable*/
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#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable*/
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#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable*/
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/* RTC control register low (16-bit) */
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#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag*/
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#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag*/
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#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag*/
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#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag*/
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#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag*/
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#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF*/
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/* RTC prescaler load register high (16-bit) */
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#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */
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#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT)
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/* RTC prescaler divider register high (16-bit) */
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#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */
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#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */
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/************************************************************************************
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* arch/arm/src/stm32/stm32_wdg.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H
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#define __ARCH_ARM_SRC_STM32_STM32_WDG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
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#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
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#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
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#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
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#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
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#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
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#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32_IWDG_KR (STM32_IWDG_OFFSET+STM32_IWDG_KR_OFFSET)
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#define STM32_IWDG_PR (STM32_IWDG_OFFSET+STM32_IWDG_PR_OFFSET)
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#define STM32_IWDG_RLR (STM32_IWDG_OFFSET+STM32_IWDG_RLR_OFFSET)
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#define STM32_IWDG_SR (STM32_IWDG_OFFSET+STM32_IWDG_SR_OFFSET)
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#define STM32_WWDG_CR (STM32_WWDG_OFFSET+STM32_WWDG_CR_OFFSET)
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#define STM32_WWDG_CFR (STM32_WWDG_OFFSET+STM32_WWDG_CFR_OFFSET)
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#define STM32_WWDG_SR (STM32_WWDG_OFFSET+STM32_WWDG_SR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Key register (32-bit) */
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#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
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#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
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/* Prescaler register (32-bit) */
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#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
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#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
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# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
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# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
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# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
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# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
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# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
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# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
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/* Reload register (32-bit) */
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#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
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#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
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/* Status register (32-bit) */
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#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
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#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
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/* Control Register (32-bit) */
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#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
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#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
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#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
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/* Configuration register (32-bit) */
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#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
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#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
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#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
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#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
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# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
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# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
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# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
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# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
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#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
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/* Status register (32-bit) */
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#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */
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